CN111834329B - 一种半导体封装结构及其制造方法 - Google Patents

一种半导体封装结构及其制造方法 Download PDF

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CN111834329B
CN111834329B CN202010614283.4A CN202010614283A CN111834329B CN 111834329 B CN111834329 B CN 111834329B CN 202010614283 A CN202010614283 A CN 202010614283A CN 111834329 B CN111834329 B CN 111834329B
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刘恺
王孙艳
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JCET Group Co Ltd
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Abstract

本发明涉及一种半导体封装结构及其制造方法,所述封装结构它包括线路内芯(1),所述线路内芯(1)包括上金属板(1.1)和下金属板(1.2),所述上金属板(1.1)和下金属板(1.2)之间填充有塑料(2),所述上金属板(1.1)正面设置有内引脚(4),所述下金属板(1.2)背面设置有外引脚(5),所述内引脚(3)上设置有芯片(7),所述芯片(7)和焊线(8)外围包封有塑封料(9)。本发明直接在线路内芯中填充塑封料,不需使用玻璃纤维层,不需要开孔后再在孔中植入导电物质,简化了制造工艺,减少了制作成本,同时通过其结构比较稳定,在温度发生变化时不容易发生翘曲。

Description

一种半导体封装结构及其制造方法
技术领域
本发明涉及一种半导体封装结构及其制造方法,属于半导体封装技术领域。
背景技术
传统的基板封装结构的制造工艺流程如下所示:
步骤一、参见图13,取一玻璃纤维材料制成的基板;
步骤二、参见图14,在玻璃纤维基板上所需的位置上开孔;
步骤三、参见图15,在玻璃纤维基板的背面披覆一层铜箔;
步骤四、参见图16,在玻璃纤维基板打孔的位置填入导电物质;
步骤五、参见图17,在玻璃纤维基板的正面披覆一层铜箔;
步骤六、参见图18,在玻璃纤维基板表面披覆光阻膜;
步骤七、参见图19,将光阻膜在需要的位置进行曝光显影开窗;
步骤八、参见图20,将完成开窗的部分进行蚀刻;
步骤九、参见图21,将基板表面的光阻膜剥除;
步骤十、参见图22,在铜箔线路层的表面进行防焊漆(俗称绿漆)的披覆;
步骤十一、参见图23,在防焊漆需要进行后工序的装片以及打线键合的区域进行开窗;
步骤十二、参见图24,在步骤十一进行开窗的区域进行电镀,相对形成基岛和引脚;
步骤十三、完成后续的装片、打线、包封、切割等相关工序。
上述传统基板封装结构存在以下不足和缺陷:
1、传统的基板制造需在玻璃纤维基板上开孔,再在孔中植入导电物质,并在玻璃纤维基板上披覆铜箔,其制造工艺非常复杂,成本较高;
2、传统的基板有一层的玻璃纤维材料,同样的也多了一层玻璃纤维的成本;玻璃纤维本身就是一种发泡物质,所以容易因为放置的时间与环境吸入水分以及湿气,直接影响到可靠性的安全能力或是可靠性的等级;
3、传统的基板仅在需要进行电性连接的地方设置上下导通金属柱,所以金属柱并没有均匀分布,这就会导致基板在温度发生变化时容易发生翘曲。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种半导体封装结构及其制造方法,其直接在线路内芯中填充塑料,不需使用玻璃纤维层,不需要开孔后再在孔中植入导电物质,简化了制造工艺,减少了制作成本,同时通过其结构比较稳定,在温度发生变化时不容易发生翘曲。
本发明解决上述问题所采用的技术方案为:一种半导体封装结构,它包括线路内芯,所述线路内芯包括上金属板和下金属板,所述上金属板和下金属板之间通过复数个金属柱相连接,所述上金属板和下金属板之间填充有塑料,所述金属柱被包覆于塑料内,所述上金属板正面设置有内引脚,所述下金属板背面设置有外引脚,所述内引脚上设置有芯片,所述芯片外围包封有塑封料,所述金属柱有两种形式,分别为连接金属柱和虚拟金属柱,所述连接金属柱起电性连接和机械支撑作用,所述虚拟金属柱仅起机械支撑作用。
可选的,复数个金属柱呈阵列式排布。
可选的,所述上金属板和下金属板外围包覆有绿漆。
可选的,所述上金属板外围包覆的绿漆上表面与内引脚上表面齐平;所述下金属板外围包覆的绿漆下表面与外引脚下表面齐平。
可选的,引脚区域的连接金属柱与连接金属柱顶部之间和底部之间分别通过上层金属板和下层金属板相连。
可选的,引脚区域的连接金属柱与虚拟金属柱仅顶部之间或底部之间相连。
可选的,引脚区域的虚拟金属柱与虚拟金属柱仅顶部之间或底部之间相连。
可选的,引脚区域外的虚拟金属柱与虚拟金属柱顶部之间和底部之间分别通过上层金属板和下层金属板相连。
可选的,引脚区域的连接金属柱与连接金属柱底部之间不通过下层金属板相连。
一种半导体封装结构的制造方法,所述方法包括以下步骤:
步骤一、取一线路内芯,线路内芯包括上金属板和下金属板,上金属板和下金属板之间通过复数个金属柱相连接;
步骤二、在线路内芯的上金属板和下金属板之间填充塑料;
步骤三、对上金属板和下金属板表面部分区域进行化学蚀刻,直至露出塑料和部分金属柱;
步骤四,在步骤三完成蚀刻后的上金属板和下金属板外围涂覆绿漆;
步骤五,对上金属板和下金属板表面的绿漆进行曝光、显影从而去除部分绿漆,以露出上金属板和下金属板后续需要进行电镀作业的图形区域;
步骤六,通过电镀在上金属板正面形成内引脚,在下金属板背面形成外引脚;
步骤七,在步骤六形成的内引脚上植入芯片;
步骤八,芯片外围采用塑封料进行塑封;
步骤九,切割制得单颗半导体封装结构。
与现有技术相比,本发明的优点在于:
1、本发明直接在线路内芯中填充塑料,不需使用玻璃纤维层,不需要开孔再在孔中植入导电物质,简化了制造工艺,减少了制作成本,提高了封装体的安全性和可靠性,减少了玻璃纤维材料带来的环境污染;
2、本发明的封装结构中平均分布有金属柱,部分用于连接内引脚与外引脚,部分为虚拟金属柱,其未用于电性连接但仍起到支撑作用,所以其结构比较稳定,在温度发生变化时不容易发生翘曲。
附图说明
图1为本发明一种半导体封装结构实施例1的剖面示意图。
图2为本发明一种半导体封装结构实施例2的剖面示意图。
图3~图12为本发明一种半导体封装结构制造方法的流程示意图。
图13~图24为传统的基板封装结构制造方法的流程示意图。
其中:
线路内芯1
上金属板1.1
下金属板1.2
金属柱1.3
连接金属柱1.3a
虚拟金属柱1.3b
塑料2
内引脚3
外引脚4
粘结物质或焊料5
芯片6
塑封料7
绿漆8。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
实施例1:
如图1所示,本发明涉及的一种半导体封装结构,它包括线路内芯1,所述线路内芯1包括上金属板1.1和下金属板1.2,所述上金属板1.1和下金属板1.2之间通过复数个阵列式排布的金属柱1.3电性和机械连接,所述上金属板1.1和下金属板1.2之间填充有塑料2,所述金属柱1.3被包覆于塑料2内,所述上金属板1.1正面设置有内引脚3,所述下金属板1.2背面设置有外引脚4,所述内引脚3上通过粘结物质或焊料5设置有芯片6,所述芯片6外围包封有塑封料7;
所述上金属板1.1和下金属板1.2外围包覆有绿漆8;
所述上金属板1.1外围包覆的绿漆6上表面与内引脚3上表面齐平;
所述下金属板1.2外围包覆的绿漆6下表面与外引脚4下表面齐平;
所述金属柱1.3有两种形式,分别为连接金属柱1.3a和虚拟金属柱1.3b,所述连接金属柱1.3a起电性连接和机械支撑作用,所述虚拟金属柱1.3b仅起机械支撑作用;
所述塑料2为热固性塑料,可以是酚醛塑料、环氧塑料、氨基塑料、不饱和聚酯、醇酸塑料等;
引脚区域(包括内引脚3区域和外引脚4区域)的连接金属柱1.3a与连接金属柱1.3a顶部之间和底部之间分别通过上层金属板1.1和下层金属板1.2相连;
引脚区域(包括内引脚3区域和外引脚4区域)的连接金属柱1.3a与虚拟金属柱1.3b顶部之间通过上层金属板1.1相连或底部之间通过下层金属板1.2相连;
引脚区域(包括内引脚3区域和外引脚4区域)的虚拟金属柱1.3b与虚拟金属柱1.3b顶部之间通过上层金属板1.1相连或底部之间通过下层金属板1.2相连;
引脚区域(包括内引脚3区域和外引脚4区域)外的虚拟金属柱1.3b与虚拟金属柱1.3b顶部之间和底部之间分别通过上层金属板1.1和下层金属板1.2相连。
实施例2:
如图2所示,实施例2与实施例1的区别在于:引脚区域(包括内引脚3区域和外引脚4区域)的连接金属柱1.3a与连接金属柱1.3a底部之间不通过下层金属板1.2相连。
其制造方法如下:
步骤一、参见图3,取一线路内芯,所述线路内芯包括上金属板和下金属板,所述上金属板和下金属板为平整的金属板,所述上金属板和下金属板之间通过复数个金属柱电性和机械连接;图4为上金属板与金属柱未结合时的示意图,复数个金属柱呈阵列排布于上金属板和下金属板之间,金属柱有两种形式,分别为连接金属柱和虚拟金属柱,所述连接金属柱起电性连接和机械支撑作用,所述虚拟金属柱在后续形成的封装结构中仅起机械支撑作用;
步骤二、参见图5,在线路内芯外围通过一次性注射成型包覆塑料,所述上金属板的下表面、下金属板的上表面和金属柱包覆在塑料中,所述上金属板的上表面和下金属板的下表面暴露在塑料之外,所述塑料为热固性塑料,可以是酚醛塑料、环氧塑料、氨基塑料、不饱和聚酯、醇酸塑料等;
步骤三、参见图6,在上金属板正面及下金属板背面贴覆或印刷可进行曝光显影的光阻材料,以保护后续蚀刻金属层工艺作业;光阻材料可以是光阻膜,也可以是光刻胶。利用曝光显影设备对金属板表面的光阻材料进行曝光、显影从而去除部分光阻材料,以露出金属板需要进行蚀刻的图形区域。对金属板上完成曝光显影的区域进行化学蚀刻,化学蚀刻直至露出塑料。蚀刻药水可以采用氯化铜或者是氯化铁或者其它可以进行化学蚀刻的药水。去除金属板表面的光阻膜,去除光阻膜的方法可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜,在完成蚀刻以后,连接金属柱起到电性连接内引脚与外引脚的作用和机械支撑作用,虚拟金属柱不起电性连接作用,仅起到机械支撑作用;
步骤四,参见图7,在步骤三完成蚀刻的上金属板和下金属板外围涂覆绿漆,绿漆完全包覆上金属板、下金属板以及步骤三蚀刻暴露出的塑料;
步骤五,参见图8,利用曝光显影设备对金属板表面的绿漆进行曝光、显影从而去除部分绿漆,以露出金属板需要进行电镀作业的图形区域;
步骤六,参见图9,在完成步骤五的金属板正反面开窗区域电镀表面金属层,表面金属层电镀完成后即在上金属板正面形成内引脚,在下金属板背面形成外引脚;
步骤七,参见图10,在步骤六形成的内引脚表面涂覆粘结物质或焊料,然后在粘结物质或焊料上植入芯片;
步骤八,参见图11,将步骤七的芯片外围采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、喷涂方式或是用贴膜方式,所述可以采用有填料物质或是无填料物质的环氧树脂;
步骤九,参见图12,将步骤八完成塑封的半成品进行切割作业,使原本阵列式塑封体切割独立开来,制得半导体封装结构。
上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。

Claims (9)

1.一种半导体封装结构,其特征在于:它包括线路内芯(1),所述线路内芯(1)包括上金属板(1.1)和下金属板(1.2),所述上金属板(1.1)和下金属板(1.2)之间通过复数个金属柱(1.3)相连接,所述上金属板(1.1)和下金属板(1.2)之间填充有塑料(2),所述金属柱(1.3)被包覆于塑料(2)内,所述上金属板(1.1)正面设置有内引脚(3),所述下金属板(1.2)背面设置有外引脚(4),所述内引脚(3)上设置有芯片(6),所述芯片(6)外围包封有塑封料(7),所述金属柱(1.3)有两种形式,分别为连接金属柱(1.3a)和虚拟金属柱(1.3b),所述连接金属柱(1.3a)起电性连接和机械支撑作用,所述虚拟金属柱(1.3b)仅起机械支撑作用,复数个金属柱(1.3)呈阵列式排布。
2.根据权利要求1所述的一种半导体封装结构,其特征在于:所述上金属板(1.1)和下金属板(1.2)外围包覆有绿漆(8)。
3.根据权利要求2所述的一种半导体封装结构,其特征在于:所述上金属板(1.1)外围包覆的绿漆(8)上表面与内引脚(3)上表面齐平;所述下金属板(1.2)外围包覆的绿漆(8)下表面与外引脚(4)下表面齐平。
4.根据权利要求1所述的一种半导体封装结构,其特征在于:引脚区域的连接金属柱(1.3a)与连接金属柱(1.3a)顶部之间和底部之间分别通过上层金属板(1.1)和下层金属板(1.2)相连。
5.根据权利要求1所述的一种半导体封装结构,其特征在于:引脚区域的连接金属柱(1.3a)与虚拟金属柱(1.3b)仅顶部之间或底部之间相连。
6.根据权利要求1所述的一种半导体封装结构,其特征在于:引脚区域的虚拟金属柱(1.3b)与虚拟金属柱(1.3b)仅顶部之间或底部之间相连。
7.根据权利要求1所述的一种半导体封装结构,其特征在于:引脚区域外的虚拟金属柱(1.3b)与虚拟金属柱(1.3b)顶部之间和底部之间分别通过上层金属板(1.1)和下层金属板(1.2)相连。
8.根据权利要求1所述的一种半导体封装结构,其特征在于:引脚区域的连接金属柱(1.3a)与连接金属柱(1.3a)底部之间不通过下层金属板(1.2)相连。
9.一种半导体封装结构的制造方法,其特征在于所述方法包括以下步骤:
步骤一、取一线路内芯,线路内芯包括上金属板和下金属板,上金属板和下金属板之间通过复数个金属柱相连接,金属柱有两种形式,分别为连接金属柱和虚拟金属柱所述连接金属柱起电性连接和机械支撑作用,所述虚拟金属柱仅起机械支撑作用,复数个金属柱呈阵列式排布;
步骤二、在线路内芯的上金属板和下金属板之间填充塑料;
步骤三、对上金属板和下金属板表面部分区域进行化学蚀刻,直至露出塑料和部分金属柱;
步骤四,在步骤三完成蚀刻后的上金属板和下金属板外围涂覆绿漆;
步骤五,对上金属板和下金属板表面的绿漆进行曝光、显影从而去除部分绿漆,以露出上金属板和下金属板后续需要进行电镀作业的图形区域;
步骤六,通过电镀在上金属板正面形成内引脚,在下金属板背面形成外引脚;
步骤七,在步骤六形成的内引脚上植入芯片;
步骤八,芯片外围采用塑封料进行塑封;
步骤九,切割制得单颗半导体封装结构。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101194360A (zh) * 2005-06-06 2008-06-04 罗姆股份有限公司 接插件及半导体装置
CN103441111A (zh) * 2013-06-25 2013-12-11 华进半导体封装先导技术研发中心有限公司 一种三维封装互连结构及其制作方法
CN204067330U (zh) * 2014-07-03 2014-12-31 天水华天科技股份有限公司 一种基板片式载体csp封装件
US20150115420A1 (en) * 2013-10-31 2015-04-30 Navas Khan Oratti Kalandar Sensor die grid array package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102209B1 (en) * 2003-08-27 2006-09-05 National Semiconductor Corporation Substrate for use in semiconductor manufacturing and method of making same
JP5215605B2 (ja) * 2007-07-17 2013-06-19 ラピスセミコンダクタ株式会社 半導体装置の製造方法
DE102008024704A1 (de) * 2008-04-17 2009-10-29 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil und Verfahren zur Herstellung eines optoelektronischen Bauteils

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101194360A (zh) * 2005-06-06 2008-06-04 罗姆股份有限公司 接插件及半导体装置
CN103441111A (zh) * 2013-06-25 2013-12-11 华进半导体封装先导技术研发中心有限公司 一种三维封装互连结构及其制作方法
US20150115420A1 (en) * 2013-10-31 2015-04-30 Navas Khan Oratti Kalandar Sensor die grid array package
CN204067330U (zh) * 2014-07-03 2014-12-31 天水华天科技股份有限公司 一种基板片式载体csp封装件

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