CN104769713A - 包括用于嵌入和/或隔开半导体裸芯的独立膜层的半导体器件 - Google Patents

包括用于嵌入和/或隔开半导体裸芯的独立膜层的半导体器件 Download PDF

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Publication number
CN104769713A
CN104769713A CN201380052391.5A CN201380052391A CN104769713A CN 104769713 A CN104769713 A CN 104769713A CN 201380052391 A CN201380052391 A CN 201380052391A CN 104769713 A CN104769713 A CN 104769713A
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China
Prior art keywords
rete
substrate
naked core
bare chip
semiconductor device
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CN201380052391.5A
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CN104769713B (zh
Inventor
叶宁
邱进添
S.厄帕德亚尤拉
付鹏
吕忠
俞志明
Y.张
王丽
P.K.雷
王伟利
邰恩勇
K.H.王
莫金理
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Shandi Trading Shanghai Co ltd
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Publication of CN104769713A publication Critical patent/CN104769713A/zh
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Abstract

公开了包括多个堆叠的半导体裸芯的半导体封装体和形成所述半导体封装体的方法。为了简化对控制器裸芯的引线键合要求,控制器裸芯可以以倒装芯片布置直接安装到基板上,而不需要控制器裸芯之外的引线键合体或足印。然后,可以将隔垫物层附着到基板,在控制器裸芯周围,以提供要安装一个或多个闪存裸芯的平表面。隔垫物层可以设置为各种不同的配置。

Description

包括用于嵌入和/或隔开半导体裸芯的独立膜层的半导体器件
背景技术
便携式消费电子产品的强劲增长需要促进了对高容量存储装置的需求。诸如闪存存储卡的非易失性半导体存储器装置正变得越来越广泛用于满足对数字信息存储和交换的日益增长的需要。它们的便携性、多用些和稳定的设计、以及其高可靠性和大容量已经使得这种存储器器件理想地用于各种电子设备,包括例如,数码相机、数字音乐播放器、视频游戏机、PDA和蜂窝电话。
虽然已知了多种封装体配置,但是通常闪存存储卡可以制造为系统级封装体(SiP)或多芯片模块(MCM),其中,在小足印基板上安装和互连多个裸芯。该基板通常可以包括刚性的介电基底,其具有在一面或两面上蚀刻的导电层。在裸芯和(一个或多个)导电层之间形成电连接,且(一个或多个)导电层提供用于将裸芯连接到主机设备的电引线结构。一旦进行在裸芯和基板之间的电连接,则典型地在模塑化合物中包封该装配件,以提供保护性封装。
图1和图2中示出了传统半导体封装体20的剖面侧视图和俯视图(在图2中没有示出模塑化合物)。典型的封装体包括附着到基板26的的多个半导体裸芯,诸如闪存裸芯22和控制器裸芯24。在裸芯制造工艺期间,可以在半导体裸芯22、24上形成多个裸芯键合垫。类似地,可以在基板26上形成多个接触垫30。裸芯22可以被附着在基板26上,然后裸芯24可以被安装在裸芯22上。然后,可以通过在相应的裸芯键合垫28和接触垫30对之间附着引线键合体32来将所有裸芯电耦合到基板。一旦完成了所有电连接,则可以在模塑化合物34中包封这些裸芯和引线键合体,以密封该封装并保护这些裸芯和引线键合体。
为了最高效地使用封装足印,已知上下堆叠半导体裸芯,无论是完全彼此重叠还是带有偏移地重叠,如图1和2所示。在偏移配置中,一个裸芯被堆叠在另一裸芯的顶上使得下方裸芯的键合垫被暴露。偏移配置提供方便地接近在堆叠中的每个半导体裸芯上的键合垫的优点。
为了增加半导体封装中的存储器容量、同时维持或减少该封装的总体尺寸,存储器裸芯的尺寸相比于封装体的总体尺寸已经变大。如此,存储器裸芯的足印通常几乎与基板的足印一样大。因此,半导体封装体内的用于向下引线键合到基板的空间是宝贵的。具体地,在存在多个堆叠的闪存裸芯22的情况下,可能变得难以对于所有接触焊垫找到基板上的空间进行所有必需的电连接。在实际半导体封装体中,裸芯键合垫、接触垫和引线键合体的数量将比图1和2中所示的多得多。图1和2中示出的数量是为了清楚的原因而极大地减少了。另外,图1和2仅包括一对半导体裸芯22。可以在裸芯堆叠中存在更多的裸芯,这使得更加难以对于所需的所有引线键合体找到空间。
控制器裸芯24通常小于存储器裸芯22。因此,常规地,控制器裸芯24置于存储器裸芯堆叠的顶上。但是,在有已经焊接到基板的多个堆叠的半导体裸芯的情况下,通常难以对于所有所需的控制器裸芯引线键合体在基板上找到空间。另外,期望增加半导体器件操作的速度,即使在半导体器件内的半导体裸芯的数量增加的情况下。由于这些因素,一些半导体封装体被制造为控制器裸芯直接焊接到基板。
为了随后将存储器裸芯焊接到控制器的顶上,底层存储器裸芯被提供有液体粘合剂的层。底层裸芯被施加到控制器裸芯的顶上,使得控制器裸芯和引线键合体嵌入到液体粘合剂层内。然后,该液体粘合剂层固化。
该操作具有某些缺点。例如,液体粘合剂易于溢流到底层存储器裸芯的上表面,在此处,它可能污染裸芯键合垫,且阻碍对于基板的适当引线键合。另外,通常在底层裸芯的顶上添加附加的存储器裸芯以形成存储器裸芯的堆叠。传统设计的另一问题是在第一站(用液体粘合剂)附着底层裸芯,然后,该封装体被移动到第二站,在第二站,(使用裸芯粘附粘合剂)安装堆叠中的剩余裸芯。其他问题包括在液体粘合剂固化之前底层存储器裸芯的移动、在嵌入到液体粘合剂时对控制器裸芯或引线键合体的损坏、和在固化时对底层存储器裸芯的损坏以及在液体粘合剂和底层存储器裸芯之间的热失配。
附图说明
图1是传统半导体封装体的剖面侧视图。
图2是传统基板和引线键合的半导体裸芯的俯视图。
图3是根据本发明的实施例的半导体器件的整体制造工艺的流程图。
图4是根据本技术的一个实施例的在制造工艺中的第一步的半导体器件的侧视图,该半导体器件包括表面安装到基板的控制器裸芯。
图5是图4所示的半导体器件的俯视图。
图6是根据本技术的一个实施例的在制造工艺中的第二步的半导体器件的侧视图,该半导体器件包括在基板上形成的膜层。
图7是图6所示的半导体器件的俯视图。
图8是根据本技术的一个实施例的在制造工艺中的第三步的半导体器件的侧视图,该半导体器件包括在基板上安装的裸芯堆叠。
图9是示出在本技术的一个实施例中的将膜层固化到最终C-阶段的温度和持续时间的绘图。
图10是根据本技术的一个实施例的成品半导体器件的侧视图。
图11是在本技术的可选实施例中的包括安装到基板的裸芯堆叠的半导体器件的侧视图。
图12是在本技术的另一可选实施例中的包括安装到基板的裸芯堆叠的半导体器件的侧视图。
图13-16是根据本技术的其他实施例的在基板上的膜层的替换配置。
具体实施方式
现在将参考图3到16来描述本技术,图3到16在实施例中涉及包括独立地施加到基板的用于嵌入表面安装的控制器裸芯和/或无源组件、或用于将存储器裸芯堆叠与表面安装的控制器裸芯和/或无源组件隔开的膜层的半导体器件。要理解,本发明可以按许多不同的形式来实施,且不应该被限制为在此阐述的实施例。而是,提供这些实施例以便本公开充分和完整,且充分地向本领域技术人员传达该发明。确实,本发明旨在覆盖这些实施例的替换、修改和等同物,这些都被包括在由所附权利要求所限定的本发明的范围和精神中。另外,在本发明的以下详细描述中,阐述大量具体细节以便提供对本发明的全面了解。但是,本领域技术人员将清楚,可以不用这种具体细节来实践本发明。
在此可能使用的术语“顶部”和“底部”、“上方”和“下方”和“垂直”和“水平”仅用于举例和图示目的,且不意图限制本发明的描述,所引用的项目可以在位置和方向上交换。
将参考图3的流程图和图4到16的俯视和侧视图来说明本发明的实施例。虽然图4到16每个示出了单个器件100、或其一部分,但是要理解,该器件100可以与基板面板上的多个其他封装体100一起被批处理,以实现规模的经济。基板面板上的封装体100的行和列的数量可以改变。
基板面板开始有多个基板102(再次,在图4到16中示出一个这样的基板)。基板102可以是各种不同的芯片承载介质,包括印刷电路板(PCB)、引线框架或带自动键合(TAB)带。在基板102是PCB的情况下,基板可以由具有顶部导电层105和底部导电层107的核心103形成。核心103可以由诸如例如聚酰亚胺薄片、包括FR4和FR5的环氧树脂、双马来酰亚胺-三嗪(BT)等的各种介电材料形成。虽然不是本发明所必要的,但是该核心可以具有在40微米(μm)到200μm之间的厚度,虽然在可选实施例中该核心的厚度可以在该范围之外变化。在可选实施例中,该核心103可以是陶瓷或有机的。
围绕核心的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或已知用于基板面板上的其他金属和材料形成。导电层可以具有大约10μm到25μm的厚度,虽然在可选实施例中这些层的厚度可以在该范围之外变化。
图3是根据本发明的实施例的形成半导体器件的制造工艺的流程图。在步骤200中,基板102被钻孔以在基板102上定义贯通通孔104。所示的通孔104(在图中仅编号了一些通孔)仅是示例,且基板可以包括比图中示出的多得多的通孔104,且它们可以处于与图中示出的位置不同的位置。接下来在步骤202中,在顶部和底部导电层的一个或两者上形成导电图案。导电图案可以包括电迹线106和接触垫108。迹线106和接触垫108(在图中仅编号了一些)仅是示例,且基板102可以包括比图中示出的更多迹线和/或接触垫,且它们可以处于与图中示出的位置不同的位置。
在实施例中,成品半导体器件100装配件可以用作BGA封装体。基板102的下表面可以包括用于接收如下所述的焊球的接触垫108。在其他实施例中,成品半导体器件100可以是LGA封装体,其包括在主机设备内可移除地耦合成品器件100的触指。在这种实施例中,下表面可以包括触指,而不是接收焊球的接触垫。基板102的顶部和/或底部表面上的导电图案可以通过各种已知工艺、包括例如各种光刻工艺来形成。
再次参考图3,然后,可以在步骤204中,在自动光学检查(AOI)中检查基板102。一旦被检查,在步骤206中可以将焊接掩膜110施加到基板。在施加了焊接掩膜后,在步骤208中,在已知电镀或薄膜沉积工艺中,在导电图案上的接触垫、触指和任何其他焊接区域可以被镀上Ni/Au、合金42等。然后,基板102可以在自动检查工艺(步骤210)中且在最终视觉检查(步骤212)中被检查和测试,以查验电操作,且查看污染、划痕和变色。假设基板102通过了检查,可以接下来在步骤214中将无源组件112附着到基板。一个或多个无源组件可以包括例如一个或多个电容器、电阻器和/或电感器,虽然可构思其他组件。示出的无源组件112(在图中仅编号了一些)仅是示例,且在其他实施例中,数量、类型和位置可以改变。
接下来,在步骤216中,可以将诸如例如ASIC的控制器裸芯114附着且电耦合到基板102。在控制器裸芯114的上表面上的裸芯键合垫118可以经由引线键合体116电耦合到接触垫108。引线键合体116和裸芯键合垫118中的仅一些被编号和示出。引线键合工艺可以是诸如反向球焊工艺的已知的工艺,虽然可构思其他引线键合工艺。在其他实施例中,在倒装芯片工艺中,可以将控制器114安装到接触垫108,在该情况下,可以省略引线键合体116。
现在参考图7的侧视图,在步骤218中,可以在基板102上形成膜层。在传统设计中,液体粘合剂被施加到底部存储器裸芯,且然后,存储器裸芯被安装在基板上,使得引线键合的控制器裸芯嵌入到液体粘合剂内。如在背景部分中描述的,该方法具有如下问题,包括液体粘合剂溢流到存储器裸芯的上面、在将存储器裸芯和液体粘合剂降到控制器裸芯和引线键合体上时对控制器裸芯和/或控制器裸芯引线键合体的损坏。
这些缺点被本技术解决,本技术在实施例中在步骤218中将膜层120沉积到基板上,完整地嵌入了控制器裸芯114、引线键合体116和无源组件112。可以单独施加膜层120(而不施加在存储器裸芯的下表面上)在图6的侧视图中且在图7的俯视图中示出了在基板102上的膜层120的一个例子。
在实施例中,膜层120可以是环氧的,其在各例子中具有包括低溢流、无空泡、低内应力、低翘曲和非导电的属性。这种膜层的例子包括来自在德国的杜塞尔多夫具有公司总部的Henkel AG&Co.KGaA的6202C环氧树脂。可以在可选实施例中使用其他环氧树脂,包括例如来自台湾的YizTech公司的BS1001环氧树脂和来自在美国的明尼苏达州的St.Paul具有公司总部的3M公司的AHS-996E环氧树脂。要理解,在其他实施例中可以使用其他环氧树脂和与环氧树脂不同的SMT粘合剂用于膜层120。
在例子中,膜层120可以作为A阶段液体或低粘度膏体直接印刷在基板102的表面,在焊接掩膜层110和控制器裸芯114的顶上粘度。可以使用诸如来自英格兰的Dorset的DEK International的Horizon 02i印刷机的薄膜印刷机,虽然在其他实施例中可以使用其他印刷机用于施加膜层120。
在一个例子中,模板(stencil)可以位于基板102的面板上,且可以将液体或膏体在模板顶上印刷到基板上。模板具有多个开口,开口的位置和形状上方与控制器裸芯114匹配。因此,当将A阶段环氧树脂施加到表面时,除了开口所在的位置之外,基板的所有位置均被屏蔽了环氧树脂。结果是,A阶段膜层120以例如图7所示的形状被施加到控制器裸芯114上方。基板102上的层120的形状和位置可以被提供为匹配要被安装在基板102上的底层裸芯的形状和位置,如以下描述的。但是,在其他实施例中,模板可以具有其他形状的开口,以形成其他形状的膜层120,也如以下描述的。在其他实施例中,可以不使用模板来施加膜层120。
适当的模板的一个例子是电铸的(eformed)模板、诸如来自在美国新泽西州的South Plainfield中具有公司总部的Cookson Performance Materials的Alpha Form Nickel模板。还可以使用诸如例如由不锈钢制造的那种的其他模板。在施加了A阶段环氧树脂之后,可以使用橡胶辊来保证A阶段环氧树脂在模板的开口内的填满且均匀的覆盖。在施加液体或膏体环氧树脂之后,可以在模板的表面上方与模板接触地移动橡胶辊,使得环氧树脂以均匀施加的层进入(即,迫使向下进入)模板的开口中。
在实施例中,橡胶辊可以被集成为印刷头装配件的部分,使得随着由印刷头装配件施加它而由橡胶辊摊开A阶段环氧树脂。用于此用途的集成的印刷头装配件和橡胶辊的例子是来自DEK International的泵式印刷橡胶辊。在其他实施例中,印刷头装配件和橡胶辊可以是分离的。
在实施例中,膜层可以具有150μm到250μm的厚度,尽管其可以比这个更薄或更厚,这部分地取决于裸片的数量和成品半导体器件的规格、以及控制器裸芯114、引线键合体116和无源组件112的的高度。在其他实施例中,可以通过除了印刷以外的方法来施加膜层120。这种其他例子包括薄膜沉积技术和喷射分配技术。在一个例子中,A阶段膜层120可以具有30,000cPat25℃、在5rpm的Brookfield CP51的初始粘度,尽管要理解,在其他实施例中A阶段液体的粘度可以比这更高或更低。
在实施例中,在基板102上形成膜层120之后,可以在步骤220中且如图8所示地将一个或多个半导体裸芯130安装到基板102、在膜层120上。半导体裸芯130可以例如是诸如NAND闪存裸芯的存储器裸芯,但在其他实施例中在步骤220中可以将其他类型的裸芯130安装到基板。图8示出其中安装四个裸芯130的实施例,但在其他实施例中可以存在更多或更少的半导体裸芯130。
在实施例中,半导体裸芯130的每个可以包括在裸芯130的下表面上的裸芯粘附粘合剂132,用于将裸芯彼此附着和附着到膜层120。裸芯粘附粘合剂可以是例如在5μm和20μm厚之间的膜,尽管在其他实施例中其可以比这更薄或更厚。可以在将裸芯130从晶片分离之前或之后施加裸芯粘附粘合剂132。当在裸芯130是晶片的一部分时被施加时,裸芯粘附粘合可以在晶片背侧涂覆工艺中施加为B阶段环氧树脂。作为一个例子,裸芯粘附粘合剂132可以是来自在日本具有总部的Nitto-Denko公司的EM-710H-P。裸芯粘附粘合剂132的另一例子是来自Henkel AG&Co.KGaA的8988UV环氧树脂,在将裸芯130附着到膜层120上之前固化为B阶段。
注意,底层裸芯130a上的裸芯粘附粘合剂不被用来嵌入控制器114或引线键合体116。如此,底层裸芯130a还可以包括与其他半导体裸芯相同的B阶段裸芯粘附粘合剂132。因此,可以将裸芯粘附粘合剂132均匀地施加到每个半导体裸芯130(包括裸芯130a),例如在裸芯130仍然被附着在一起作为半导体晶片的一部分时;然后裸芯粘附粘合剂132被固化到B阶段。,底层裸芯130a可以在与剩余裸芯130的相同工艺工具中施加。如在此使用的,B阶段是热固性粘合剂和/或环氧树脂的反应中的中间阶段,在该阶段中,该材料是稳定的,且在存储或运输时通常维持其形状,但其可能当时被加热时软化,使得其可以接合到与粘合剂和/或环氧树脂接触的表面。
为了将裸芯130附着到基板102,底层裸芯130a抵靠基板102,使得裸芯粘附粘合剂抵靠膜层120安置。如上所述,膜层120可以作为A阶段液体或膏体施加到基板。在如下所述的实施例中,膜层120可以在底层裸芯130a被置于基板102上之前被固化到B阶段。这允许在存储和/或运输基板面板时膜层120保持稳定和未损伤。在另一实施例中,膜层120可以在底层裸芯130a被置于基板102上之前被固化到C阶段。C阶段是在热固性的粘合剂和/或环氧树脂的反应中的最终阶段,在该阶段中,材料是固态且不溶的,例如由材料中的分子彼此交联导致。以下更详细描述其中当裸芯130a置于其上时膜层120是B阶段环氧树脂和当裸芯130a置于其上时膜层120是C阶段环氧树脂的例子。
在当裸芯130a置于其上时膜层是B阶段环氧树脂的例子中,通过在125°C处加热膜层120达90分钟来将A阶段膜层120固化到B阶段。可构思其他加热温度和时间。取决于膜层120的材料,在其他实施例中可以通过紫外线照射来将膜层固化到B阶段。该B阶段加热步骤可以在模板内施加A阶段膜层120之后且在移除模板之前进行。在其他实施例中,其可以在移除了模板之后进行。
当底层裸芯130a置于B阶段膜层120上时,基板可以被加热以软化B阶段膜层120以提升膜层120和底层裸芯130a上的裸芯粘附粘合剂132之间的附着力。施加的热可以将膜层120和下方的裸芯130上的裸芯粘附粘合剂132两者固化为彼此牢固地粘合的C阶段固体。在一个例子中,在与裸芯粘附粘合剂132接触之后,可以通过用30分钟将膜层120从室温升温至100℃并在100℃持续另外的30分钟来将B阶段膜层120固化到其最终C阶段。在另一例子中,可以通过用30分钟将膜层120从室温升温至175℃并在175℃持续另外的30分钟来进行到C阶段环氧树脂的该固化。可以在上述范围之间的任何温度进行将膜层120固化到C阶段的其他例子。
另外,可以在其他实施例中以比上述例子更高和更低的温度和持续时间来进行将膜层120固化到C阶段。另外,将层120固化到C阶段可以具有多个加热阶段,例如如图9所示。可构思多个加热阶段的其他例子,其中,图9所示的温度和时间段的任何可以改变。取决于膜层120的材料,在其他实施例中可以超声波地将膜层固化到C阶段。
在当裸芯130a置于其上时膜层是C阶段环氧树脂的例子中,根据上述B阶段和C阶段固化方法的任何,A阶段膜层120可以被固化到B阶段,且随后被固化到C阶段。在另一实施例中,A阶段膜层120可以直接固化到C阶段。这也可以通过上述任何C阶段固化方法来进行。一些环氧树脂旨在从A阶段直接固化到C阶段。这些环氧树脂在此被称为可A阶段化环氧树脂。其他环氧树脂旨在从A阶段固化到中间的B阶段、然后固化到C阶段。这些环氧树脂在此被称为可B阶段化环氧树脂。在当裸芯130a置于其上时膜层是C阶段环氧树脂的例子中,可以使用可A阶段化或可B阶段化环氧树脂。在该实施例中,最终的C阶段膜层120不将底层裸芯130a粘合到基板。底层裸芯130a上的裸芯粘附粘合剂132将裸芯130a接合到固体膜层120(在与将膜层120固化到C阶段的步骤分离的固化步骤中)。
在如上所述将底层裸芯130a置于膜层120上之后,裸芯堆叠中的附加的裸芯130可以被类似地置于该裸芯堆叠中。然后,在步骤224中,可以通过如图8所示在裸芯130上的裸芯键合垫和基板102上的接触垫108之间形成的引线键合体136,将每个裸芯130电耦合到基板。虽然所有引线键合体被示出为从半导体裸芯130的单个边缘延伸,但是要理解,裸芯130可以具有在两个或更多边缘周围的裸芯键合垫和引线键合体。另外,堆叠中的裸芯130可以彼此引线键合,取代或附加于每个裸芯130被引线键合到基板102。
在实施例中,每个裸芯130可以在其置于基板上时被引线键合到基板102。在其他实施例中,所有裸芯可以置于基板上,且然后,所有裸芯可以被引线键合到基板。在实施例中,在所有裸芯都置于裸芯堆叠中之后、且在所有裸芯被引线键合到基板之前或之后,每个裸芯130上的裸芯粘附粘合剂132可以被固化以将裸芯彼此接合且将裸芯接合到基板。在当裸芯130置于裸芯堆叠中时膜层120是B阶段环氧树脂的实施例中,可以与每个裸芯130上的裸芯粘附粘合剂132同时将膜层120固化到最终C阶段。在其他实施例中,B阶段膜层120和裸芯粘附粘合剂132的最终固化可以稍后进行,例如在如下描述的模塑包封工艺期间进行。
在安装裸芯堆叠和引线键合之后,在步骤226中且如图10所示,裸芯堆叠、引线键合体和基板的至少一部分可以被包封在模塑化合物140中。模塑化合物140可以包括例如固态环氧树脂、酚醛树脂、熔融石英、结晶石英、碳黑和/或金属羟化物。这种模塑化合物可从例如在日本都有总部的Sumitomo公司和Nitto-Denko公司得到。可构思来自其他制造商的其他模塑化合物。可以根据各种已知工艺来施加模塑化合物,所述工艺包括通过转移模塑或注射模塑技术。在其他实施例中,可以通过FFT(薄自由流动(Flow Free Thin))压缩模塑来进行包封工艺。
如图10所示,在步骤226中包封了在面板上的裸芯之后,对于器件是BGA封装体的实施例,在步骤228中,可以将焊球142焊接到各个封装体的下表面上的接触垫108。在封装体是LGA封装体的情况下,可以跳过步骤226。
在步骤230中可以从面板上单片化各个封装体,以形成图10所示的成品半导体器件100。通过各种切割方法的任一种,单片化每个半导体器件100,所述切割方法包括锯割、水流切割、激光切割、水引导的激光切割、干介质切割和金刚石涂覆线切割。虽然直线切割将通常限定矩形或正方形的半导体器件100,但是要理解在本发明的其他实施例中,半导体器件100可以具有与矩形和正方形不同的形状。
一旦切割为封装100体,可以在步骤232中测试这些封装体,以确定这些封装体是否适当地运作。如在现有技术中已知,这种测试可以包括电测试、写入(burn in)和其他测试。可选地,在步骤234中,在例如半导体器件是LGA封装体的情况下,成品半导体器件可以被包封在盖帽(未示出)内。
成品半导体封装100可以例如是存储卡,诸如例如MMC卡、SD卡、多用途卡、微SD卡、存储棒、紧致SD卡、ID卡、PCMCIA卡、SSD卡、芯片卡、智能卡、USB卡、MCP类嵌入式卡存储等。
在上述实施例中,在附着存储器裸芯之前,膜层120可以被固化到C阶段,因为底层裸芯130a包括用于将底层裸芯安装到基板102的裸芯粘附粘合剂132。在图11所示的另一实施例中,可以从底层裸芯130a省略裸芯粘附粘合剂132。在这种实施例中,可仅使用膜层120来将底层裸芯130a附着到基板102。在这种实施例中,膜层可以在被形成到基板上之后被固化到B阶段。此后,裸芯130a可以置于膜层120上,膜层被加热以软化该层,且膜层被固化到C阶段,如上述,使得膜层120将裸芯130a接合到基板。
在上述实施例中,使用膜层120以覆盖表面安装的控制器114和无源组件112且支持存储器裸芯130。在图12所示的另一实施例中,膜层120可以支持存储器裸芯130且根据上述实施例的任一而被形成(在将裸芯130置于其上之前形成为B阶段或C阶段)。但是,在该实施例中,控制器114和/或无源组件112可以被置于基板上,在膜层120之外。在此,膜层120可以用作隔垫物以在基板上提供与存储器裸芯堆叠隔离的空间,以用于表面安装诸如例如控制器裸芯114的组件。
如上所述,在实施例中,膜层120的形状和位置可以与其上安装的底层裸芯130a的形状和位置匹配。但是,在其他实施例中,膜层120可以具有各种不同的形状。图13-16呈现一些、非限制的例子。在图13和14中,膜层120被形成以具有例如在控制器裸芯114上方的开口150。开口150可以具有任何形状或大小,或在膜层120的足印内的任何位置。图14和15示出膜层形成为多个离散的部分的例子。在其他实施例中,基板102上的离散部分的数量、形状、大小和位置可以改变。膜层120的这些和其他配置可以如上所述以所期望的开口通过图案化模板来提供,,通过这些开口,膜层120初始作为液体或膏体施加并随后被固化。
总之,在一个例子中,本技术涉及一种半导体器件,其包括:基板:表面安装到所述基板的电组件;在所述基板上形成的膜层,所述电组件至少部分地嵌入到所述膜层内;以及所述至少一个半导体裸芯,包括一个半导体裸芯,其具有将所述半导体裸芯附着到所述膜层的裸芯粘附粘合剂。
在另一个例子中,本技术涉及一种半导体器件,包括:基板:表面安装到所述基板的电组件;在所述基板上形成的膜层,所述膜层与所述基板上的电组件隔开;以及所述至少一个半导体裸芯,包括一个半导体裸芯,其具有将所述半导体裸芯附着到所述膜层的裸芯粘附粘合剂。
在另一例子中,本技术涉及一种形成半导体器件的方法,包括如下步骤:(a)将电组件安装到基板;(b)将膜层施加到所述基板,所述电组件至少部分地嵌入到所述膜层内;(c)在所述步骤(b)中将所述电组件至少部分地嵌入到所述膜层内之后,将膜层固化到至少B阶段;(d)将半导体裸芯放置到所述膜层上;以及(e)将所述半导体裸芯附着到所述膜层。
在另一例子中,本技术涉及一种形成半导体器件的方法,包括如下步骤:(a)将控制器裸芯安装到基板上;(b)将A阶段膜层施加到所述基板,所述控制器裸芯至少部分地嵌入到所述膜层内;(c)在所述步骤(b)中将所述电组件至少部分地嵌入到所述膜层内之后,将膜层固化到C阶段;(d)将半导体裸芯置于所述膜层上,所述半导体裸芯包括在所述半导体裸芯和所述膜层之间的半导体裸芯的表面上的裸芯粘附粘合剂;以及(e)通过固化所述裸芯粘附粘合剂层将所述半导体裸芯附着到所述膜层。
已经为了图示和描述的目的呈现了本发明的前述描述。不旨在穷举或限制本发明到公开的精确形式。在上述教导下,许多修改和变化是可能的。选择上述实施例以便最佳地说明本发明的原理及其实际应用,由此使得本领域技术人员能够最佳地在各种实施例中使用本发明,且设想适用于实际使用的各种修改。本发明的范围旨在由所附的权利要求来限定。

Claims (28)

1.一种半导体器件,包括:
基板:
表面安装到所述基板的电组件;
在所述基板上形成的膜层,所述电组件至少部分地嵌入到所述膜层内;以及
所述至少一个半导体裸芯,包括一个半导体裸芯,其具有将所述半导体裸芯附着到所述膜层的裸芯粘附粘合剂。
2.根据权利要求1所述的半导体器件,其中,所述膜层是可B阶段环氧树脂。
3.根据权利要求1所述的半导体器件,其中,所述膜层是可A阶段环氧树脂。
4.根据权利要求1所述的半导体器件,其中,所述膜层在所述基板上形成的形状和位置与所述基板上的半导体裸芯的形状和位置匹配。
5.根据权利要求1所述的半导体器件,其中,所述电组件是控制器裸芯。
6.根据权利要求1所述的半导体器件,其中,所述电组件是无源组件。
7.根据权利要求1所述的半导体器件,其中,所述至少一个半导体裸芯包括至少一个存储器裸芯。
8.根据权利要求1所述的半导体器件,还包括将所述电组件电耦合到所述基板的引线键合体,所述引线键合体嵌入到所述膜层中。
9.根据权利要求1所述的半导体器件,其中,所述半导体器件是闪存封装体。
10.一种半导体器件,包括:
基板:
表面安装到所述基板的电组件;
在所述基板上形成的膜层,所述膜层与所述基板上的电组件隔开;以及
所述至少一个半导体裸芯,包括一个半导体裸芯,其具有将所述半导体裸芯附着到所述膜层的裸芯粘附粘合剂。
11.根据权利要求10所述的半导体器件,其中,所述膜层是可B阶段环氧树脂。
12.根据权利要求10所述的半导体器件,其中,所述膜层是可A阶段环氧树脂。
13.根据权利要求10所述的半导体器件,其中,所述膜层在所述基板上形成的形状和位置与所述基板上的半导体裸芯的形状和位置匹配。
14.根据权利要求10所述的半导体器件,其中,所述电组件是控制器裸芯和无源组件中的一种。
15.一种形成半导体器件的方法,包括如下步骤:
(a)将电组件安装到基板;
(b)将膜层施加到所述基板,所述电组件至少部分地嵌入到所述膜层内;
(c)在所述步骤(b)中将所述电组件至少部分地嵌入到所述膜层内之后,将膜层固化到至少B阶段;
(d)将半导体裸芯置于所述膜层上;以及
(e)将所述半导体裸芯附着到所述膜层。
16.根据权利要求15所述的方法,其中,所述步骤(b)包括在所述基板上印刷液体或膏体环氧树脂的步骤。
17.根据权利要求15所述的方法,其中,所述步骤(b)包括通过薄膜沉积和喷射分配中的一种在所述基板上沉积液体或膏体环氧树脂的步骤。
18.根据权利要求15所述的方法,其中,所述步骤(b)包括将模板置于所述基板上方的步骤,所述模板包括定义基板上的膜层的形状和位置的开口,所述膜层被施加在所述模板上且在所述开口内。
19.根据权利要求18所述的方法,其中所述步骤(b)还包括使用橡胶辊使得所述液体或膏体进入所述模板的开口内。
20.根据权利要求15所述的方法,其中所述步骤(c)包括将所述膜层固化到B阶段和将所述半导体裸芯置于所述B阶段环氧树脂上的步骤。
21.根据权利要求20所述的方法,还包括在将所述半导体裸芯置于所述膜层上之后将所述膜层固化到C阶段的步骤。
22.根据权利要求21所述的方法,其中,所述将所述膜层固化到C阶段的步骤作为将半导体裸芯附着到所述膜层的步骤(e)的一部分进行。
23.根据权利要求15所述的方法,其中所述步骤(c)包括将所述膜层固化到C阶段和将所述半导体裸芯置于所述C阶段环氧树脂上的步骤。
24.根据权利要求23所述的方法,其中,所述步骤(e)包括用半导体裸芯的表面上形成的与所述膜层接触的裸芯粘附粘合剂来将半导体裸芯附着到所述膜层的步骤。
25.一种形成半导体器件的方法,包括如下步骤:
(a)将控制器裸芯安装到基板上;
(b)将A阶段膜层施加到所述基板,所述控制器裸芯至少部分地嵌入到所述膜层内;
(c)在所述步骤(b)中将所述电组件至少部分地嵌入到所述膜层内之后,将膜层固化到C阶段;
(d)将半导体裸芯置于所述膜层上,所述半导体裸芯包括在所述半导体裸芯和所述膜层之间的半导体裸芯的表面上的裸芯粘附粘合剂;以及
(e)通过固化所述裸芯粘附粘合剂层将所述半导体裸芯附着到所述膜层。
26.根据权利要求25所述的方法,其中,所述步骤(b)包括通过丝网印刷、薄膜沉积和喷射分配中的一种在所述基板上施加液体或膏体的步骤。
27.根据权利要求25所述的方法,其中,所述步骤(b)包括将模板置于所述基板上方的步骤,所述模板包括定义基板上的膜层的形状和位置的开口,所述膜层被施加在所述模板上且在所述开口内。
28.根据权利要求27所述的方法,其中所述步骤(b)还包括使用橡胶辊使得所述液体或膏体进入所述模板的开口内。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810661A (zh) * 2016-03-16 2016-07-27 三星半导体(中国)研究开发有限公司 集成电源模块的封装件
CN110211952A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置
CN110391218A (zh) * 2018-04-23 2019-10-29 晟碟半导体(上海)有限公司 具有裸芯翘起控制的半导体装置
CN111081559A (zh) * 2018-10-19 2020-04-28 细美事有限公司 裸芯接合装置和方法以及基板接合装置和方法
US11139277B2 (en) 2019-06-28 2021-10-05 Western Digital Technologies, Inc. Semiconductor device including contact fingers on opposed surfaces

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
JP2016167523A (ja) * 2015-03-09 2016-09-15 株式会社東芝 半導体装置および電子機器
US9673183B2 (en) * 2015-07-07 2017-06-06 Micron Technology, Inc. Methods of making semiconductor device packages and related semiconductor device packages
KR20180004413A (ko) * 2016-07-04 2018-01-12 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US20180088628A1 (en) * 2016-09-28 2018-03-29 Intel Corporation Leadframe for surface mounted contact fingers
KR102592640B1 (ko) 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
EP3481161A1 (en) * 2017-11-02 2019-05-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with transistor components arranged side by side
JP2020053655A (ja) 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
TWI665770B (zh) * 2018-12-13 2019-07-11 力成科技股份有限公司 半導體封裝結構及其製法
US11315003B2 (en) * 2019-08-14 2022-04-26 Federal Card Services, LLC RFID enabled metal transaction cards
US11094673B2 (en) * 2019-11-22 2021-08-17 Western Digital Technologies, Inc. Stacked die package with curved spacer
US11942430B2 (en) 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
WO2023034642A1 (en) 2021-09-06 2023-03-09 Metaland Llc Encapsulating a metal inlay with thermosetting resin and method for making a metal transaction card
US20230137512A1 (en) * 2021-11-03 2023-05-04 Western Digital Technologies, Inc. Stacked ssd semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200836306A (en) * 2007-02-16 2008-09-01 Powertech Technology Inc Multi-chip stack package
CN101292352A (zh) * 2005-09-01 2008-10-22 美光科技公司 微电子成像单元和以晶片级制造微电子成像单元的方法
US20100027233A1 (en) * 2008-07-31 2010-02-04 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
CN102163595A (zh) * 2010-02-05 2011-08-24 海力士半导体有限公司 堆叠半导体封装

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100302593B1 (ko) 1998-10-24 2001-09-22 김영환 반도체패키지및그제조방법
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
JP2005275802A (ja) * 2004-03-24 2005-10-06 Omron Corp 電波読み取り可能なデータキャリアの製造方法および該製造方法に用いる基板並びに電子部品モジュール
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
KR100690960B1 (ko) 2004-06-24 2007-03-09 삼성전자주식회사 스크린 프린팅 공정을 갖는 반도체 칩 패키지 제조 방법
WO2007026392A1 (ja) 2005-08-30 2007-03-08 Spansion Llc 半導体装置およびその製造方法
US7550834B2 (en) 2006-06-29 2009-06-23 Sandisk Corporation Stacked, interconnected semiconductor packages
US7993939B2 (en) * 2006-07-21 2011-08-09 Stats Chippac Ltd. Integrated circuit package system with laminate base
CN101026148A (zh) 2007-03-27 2007-08-29 日月光半导体制造股份有限公司 光电芯片的多芯片增层封装构造及其制造方法
CN100547607C (zh) 2007-04-02 2009-10-07 力成科技股份有限公司 可分割记忆体磁区的模组化记忆卡装置
JP2009032013A (ja) 2007-07-26 2009-02-12 Toshiba Corp 半導体装置及びその製造方法
KR100887558B1 (ko) 2007-08-27 2009-03-09 앰코 테크놀로지 코리아 주식회사 반도체 패키지
JP4498403B2 (ja) 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US7612436B1 (en) 2008-07-31 2009-11-03 Micron Technology, Inc. Packaged microelectronic devices with a lead frame
KR101060730B1 (ko) 2009-09-02 2011-08-30 에스티에스반도체통신 주식회사 적층형 usb 메모리 장치 및 그 제조 방법
JP2011129894A (ja) 2009-11-18 2011-06-30 Toshiba Corp 半導体装置
US8404518B2 (en) * 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
JP2012129464A (ja) 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
US20120235188A1 (en) * 2011-03-15 2012-09-20 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Method and Apparatus for a Flat Top Light Source
JP2012216644A (ja) * 2011-03-31 2012-11-08 Toshiba Corp 半導体装置及びその製造方法
US8476111B2 (en) 2011-06-16 2013-07-02 Stats Chippac Ltd. Integrated circuit packaging system with intra substrate die and method of manufacture thereof
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101292352A (zh) * 2005-09-01 2008-10-22 美光科技公司 微电子成像单元和以晶片级制造微电子成像单元的方法
TW200836306A (en) * 2007-02-16 2008-09-01 Powertech Technology Inc Multi-chip stack package
US20100027233A1 (en) * 2008-07-31 2010-02-04 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
CN102163595A (zh) * 2010-02-05 2011-08-24 海力士半导体有限公司 堆叠半导体封装

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810661A (zh) * 2016-03-16 2016-07-27 三星半导体(中国)研究开发有限公司 集成电源模块的封装件
CN106920786A (zh) * 2016-03-16 2017-07-04 三星半导体(中国)研究开发有限公司 集成电源模块的封装件
US10109602B2 (en) 2016-03-16 2018-10-23 Samsung Electronics Co., Ltd. Package integrated with a power source module
CN106920786B (zh) * 2016-03-16 2018-11-06 三星半导体(中国)研究开发有限公司 集成电源模块的封装件
CN110211952A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置
CN110211952B (zh) * 2018-02-28 2023-08-01 铠侠股份有限公司 半导体装置
CN110391218A (zh) * 2018-04-23 2019-10-29 晟碟半导体(上海)有限公司 具有裸芯翘起控制的半导体装置
CN111081559A (zh) * 2018-10-19 2020-04-28 细美事有限公司 裸芯接合装置和方法以及基板接合装置和方法
CN111081559B (zh) * 2018-10-19 2024-01-16 细美事有限公司 裸芯接合装置和方法以及基板接合装置和方法
US11139277B2 (en) 2019-06-28 2021-10-05 Western Digital Technologies, Inc. Semiconductor device including contact fingers on opposed surfaces

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