CN110517999A - 一种引线框架结构及其封装结构 - Google Patents
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Abstract
本发明涉及一种引线框架结构及其封装结构,所述引线框架结构包括基岛、引脚,所述基岛包括外基岛(1)和内基岛(2),所述引脚包括外引脚(3)和内引脚(4),所述内基岛(2)四角位置通过导电线(5)延伸到切割道金属(6),所述外引脚(3)延伸到切割道金属(6),所述内引脚(4)设置在外引脚(3)的上方,所述内引脚(4)通过外引脚(3)与切割道金属(6)相连。本发明种引线框架结构及其封装结构,它可使引线框架封装体具备EMI电磁屏蔽需求,以满足复杂电磁环境、5G市场下QFN类封装体的电磁屏蔽要求。
Description
技术领域
本发明涉及一种引线框架结构及其封装结构,属于半导体封装技术领域。
背景技术
作为已公知的引线封装如四方扁平引线(QFN)封装,其产品上的内引线端和相对的外引线端全部通过连杆连接至切割道上的引线框,封装切割后连杆部分残留在塑封体侧壁。
随着5G时代的临近,半导体封装器件处于更加复杂的电磁环境中,原无需电磁屏蔽需求的器件,也需要考虑来自外界其他高频信号的干扰或影响。
现业界常规EMI屏蔽技术,在塑封体正面和四个侧壁形成一层金属导电EMI层,并接地,从而满足产品电磁屏蔽需求。然而QFN类引线封装器件,因其侧壁有导电线连杆残留,若侧壁覆盖上EMI金属层,则导致所有引线全部短接,造成功能失效。
如何让引线封装器件(如QFN封装)满足日益复杂的电磁环境,是需要本技术领域急需解决的。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种引线框架结构及其封装结构,它可使引线框架封装体具备EMI电磁屏蔽需求,以满足复杂电磁环境、5G市场下QFN类封装体的电磁屏蔽要求。
本发明解决上述问题所采用的技术方案为:一种引线框架结构,它包括基岛、引脚,所述基岛包括外基岛和内基岛,所述引脚包括外引脚和内引脚,所述内基岛四角位置通过导电线延伸到切割道金属,所述外引脚延伸到切割道金属,所述内引脚设置在外引脚的上方,所述内引脚通过外引脚与切割道金属相连。
一种引线框架的封装结构,它包括引线框架,所述引线框架包括基岛和引脚,所述基岛包括外基岛和内基岛,所述引脚包括外引脚和内引脚,所述内基岛上通过粘结性材料设置有芯片,所述芯片与内引脚之间通过金属线相连接,所述基岛、引脚和芯片外围包封有塑封料形成塑封体,所述内基岛四角位置通过导电线延伸至塑封体侧面,所述内引脚不露出塑封体侧面,所述外引脚露出塑封体侧面,所述外引脚背离基岛的侧面与芯片塑封体侧面外围形成有一圈台阶,所述塑封料正面和四个侧面设置有屏蔽层,所述基岛通过导电线与屏蔽层相连接。
优选的,所述台阶高度高于外引脚高度,低于内引脚高度。
优选的,所述导电线不是整片金属,由分散的多个导电线组成。
优选的,单颗封装结构侧面设置有一圈边缘导电线,所述边缘导电线与引脚不导通,所述边缘导电线通过导电线与屏蔽层相连接。
优选的,单颗封装结构侧面露出多条单独的导电线侧面,多条单独的导线线间隔设置于相邻的两个引脚之间。
与现有技术相比,本发明的优点在于:
1、本发明可使引线框架封装体具备电磁屏蔽需求,以满足复杂电磁环境、5G市场下QFN类封装体的电磁屏蔽要求;
2、本发明通过导电线外露且导电线可根据需要设置不同位置,同时内引脚不裸露,外引脚内缩,使整个封装体四个侧壁接地部分与外层屏蔽层的接触面积增加,可降低外界电磁信号通过引脚部分缺口影响产品芯片性能;
3、本发明当切割形成台阶后,外引脚外侧壁可见,满足引脚侧面浸润需求,提高封装体与PCB板的焊接强度。
附图说明
图1为本发明一种引线框架的示意图。
图2为本发明一种引线框架正面的示意图。
图3为本发明一种引线框架背面的示意图。
图4为本发明一种引线框架的封装结构的示意图。
图5为本发明一种引线框架的封装结构的立体示意图。
图6~图9为本发明一种引线框架EMI封装结构工艺方法的各工序流程图。
图10为图4中封装结构实施例3的结构示意图。
图11为图4中封装结构实施例4的结构示意图。
图12为图4中封装结构实施例5的结构示意图。
其中:
外基岛1
内基岛2
外引脚3
内引脚4
导电线5
切割道金属6
粘结性材料7
芯片8
金属线9
塑封料10
台阶11
屏蔽层12
边缘导电线13。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
参见图1~图3,本发明涉及的一种引线框架结构,它包括基岛、引脚,所述基岛包括外基岛1和内基岛2,所述引脚包括外引脚3和内引脚4,所述内基岛2四角位置通过导电线5延伸到切割道金属6,所述外引脚3延伸到切割道金属6,所述内引脚4设置在外引脚3的上方,所述内引脚4通过外引脚3与切割道金属6相连。
实施例1:
参见图4、图5,本发明涉及的一种引线框架的封装结构,它包括引线框架,所述引线框架包括基岛和引脚,所述基岛包括外基岛1和内基岛2,所述引脚包括外引脚3和内引脚4,所述内基岛2上通过粘结性材料7设置有芯片8,所述芯片8与内引脚4之间通过金属线9相连接,所述基岛、引脚和芯片8外围包封有塑封料10形成塑封体,所述内基岛2四角位置通过导电线5延伸至塑封体侧面,所述内引脚4不露出塑封体侧面,所述内外引脚3露出塑封体侧面,所述外引脚3背离基岛的侧面与芯片外围塑封体侧面形成有一圈台阶11,所述塑封料10正面和四个侧面设置有屏蔽层12,所述基岛通过导电线5与屏蔽层12相连接,从而使整个封装体形成一个屏蔽罩。
其工艺方法包括以下步骤:
步骤一、参见图6(其中图6a为正面视图,图6b为背面视图,图6c为剖视图),取一引线框架,所述引线框架包括基岛、引脚和切割道金属6,基岛包括外基岛和内基岛,引脚包括外引脚和内引脚,内基岛四角位置通过导电线5与切割道金属6相连接,外引脚3延伸到切割道金属6,内引脚4通过外引脚3与切割道金属6相连接,在上述引线框架上依次进行点胶、装片、键合和塑封工艺;
步骤二、参见图7(其中图7a为正面视图,图7b为背面视图,图7c为剖视图),对引线框架背面沿切割道金属进行切割形成台阶11,采用一定宽度的刀片A,刀片A宽度超出切割道金属宽度且不会切到内引脚,切割的深度超出外引脚的厚度但不得超出整个引脚的厚度,切割后外引脚的侧面露出,部分导电线的部分侧面露出;
步骤三、参见图8(其中图8a为正面视图,图8b为背面视图,图8c为剖视图),沿切割道金属切割,切割刀片B宽度小于刀片A宽度,将切割道金属切除,使整体结构切成单颗封装体,导电线的侧面完全露出,经过两次切割,导电线侧面曾台阶形,但内引脚的侧面不裸露在外;
步骤四、引线框架背面进行表面处理,将露出的外引脚和外基岛进行表面处理,以提供良好的焊接性;
步骤五、参见图9,溅镀,在切割后的单颗封装体正面和四个侧面溅镀上一层或多层金属层形成屏蔽层12,屏蔽层12通过封装体的侧面露出的导电线接地,在溅镀制程前,可以在封装体背面裸露的外引脚表面、外基岛表面涂布一层保护胶,如高温定型胶,以防止溅镀金属与引脚连接导致短路,在溅镀制程完成后,去除保护胶。
实施例2:
参见图10,实施例2与实施例1的区别在于:导电线5不是整片金属,由分散的导电线组成,以分散应力和增加基岛的结构强度。
实施例3:
参见图11,实施例3与实施例1的区别在于:单颗封装结构侧面除了露出导电线侧面外,还留有一圈一定宽度的边缘导电线13,用以增加屏蔽层的接地效果。
实施例4:
参见图12,实施例4与实施例2的区别在于:单颗封装体侧面露出多条单独的导电线侧面,以间隔不同引脚间的信号干扰。
上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (6)
1.一种引线框架结构,其特征在于:它包括基岛、引脚,所述基岛包括外基岛(1)和内基岛(2),所述引脚包括外引脚(3)和内引脚(4),所述内基岛(2)四角位置通过导电线(5)延伸到切割道金属(6),所述外引脚(3)延伸到切割道金属(6),所述内引脚(4)设置在外引脚(3)的上方,所述内引脚(4)通过外引脚(3)与切割道金属(6)相连。
2.一种引线框架的封装结构,其特征在于:它包括引线框架,所述引线框架包括基岛和引脚,所述基岛包括外基岛(1)和内基岛(2),所述引脚包括外引脚(3)和内引脚(4),所述内基岛(2)上通过粘结性材料(7)设置有芯片(8),所述芯片(8)与内引脚(4)之间通过金属线(9)相连接,所述基岛、引脚和芯片(8)外围包封有塑封料(10)形成塑封体,所述内基岛(2)四角位置通过导电线(5)延伸至塑封体侧面,所述内引脚(4)不露出塑封体侧面,所述外引脚(3)露出塑封体侧面,所述外引脚(3)背离基岛的侧面与芯片外围塑封体侧面外围形成有一圈台阶(11),所述塑封料(10)正面和四个侧面设置有屏蔽层(12),所述基岛通过导电线(5)与屏蔽层(12)相连接。
3.根据权利要求2所述的一种引线框架的封装结构,其特征在于:所述台阶(11)高度高于外引脚(3)高度,低于内引脚(4)高度。
4.根据权利要求2所述的一种引线框架的封装结构,其特征在于:所述导电线(5)不是整片金属,由分散的多个导电线组成。
5.根据权利要求2所述的一种引线框架的封装结构,其特征在于:单颗封装结构侧面设置有一圈边缘导电线(13),所述边缘导电线(13)与引脚不导通,所述边缘导电线(13)通过导电线(5)与屏蔽层(12)相连接。
6.根据权利要求2所述的一种引线框架的封装结构,其特征在于:单颗封装结构侧面露出多条单独的导电线侧面,多条单独的导线线间隔设置于相邻的两个引脚之间。
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CN113745170A (zh) * | 2021-08-30 | 2021-12-03 | 西安微电子技术研究所 | 一种减少玻璃裂纹的金属外壳引线结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102479767A (zh) * | 2010-11-24 | 2012-05-30 | 宇芯(毛里求斯)控股有限公司 | 具有电磁屏蔽的半导体器件封装 |
US20120218729A1 (en) * | 2011-02-28 | 2012-08-30 | Rf Micro Devices, Inc. | Microshield on standard qfn package |
CN109494209A (zh) * | 2018-10-08 | 2019-03-19 | 江苏长电科技股份有限公司 | 一种侧壁可浸润超薄封装结构及其制造方法 |
CN109545770A (zh) * | 2013-11-20 | 2019-03-29 | 日月光半导体制造股份有限公司 | 半导体封装结构 |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102479767A (zh) * | 2010-11-24 | 2012-05-30 | 宇芯(毛里求斯)控股有限公司 | 具有电磁屏蔽的半导体器件封装 |
US20120218729A1 (en) * | 2011-02-28 | 2012-08-30 | Rf Micro Devices, Inc. | Microshield on standard qfn package |
CN109545770A (zh) * | 2013-11-20 | 2019-03-29 | 日月光半导体制造股份有限公司 | 半导体封装结构 |
CN109494209A (zh) * | 2018-10-08 | 2019-03-19 | 江苏长电科技股份有限公司 | 一种侧壁可浸润超薄封装结构及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113745170A (zh) * | 2021-08-30 | 2021-12-03 | 西安微电子技术研究所 | 一种减少玻璃裂纹的金属外壳引线结构 |
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