CN102479767A - 具有电磁屏蔽的半导体器件封装 - Google Patents

具有电磁屏蔽的半导体器件封装 Download PDF

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CN102479767A
CN102479767A CN2011103770067A CN201110377006A CN102479767A CN 102479767 A CN102479767 A CN 102479767A CN 2011103770067 A CN2011103770067 A CN 2011103770067A CN 201110377006 A CN201110377006 A CN 201110377006A CN 102479767 A CN102479767 A CN 102479767A
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lead
lead frame
connecting rod
encapsulation
wire
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R·S·圣安东尼奥
M·H·麦克埃里格哈恩
A·苏巴吉奥
A·C·托里亚加
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Advanced Interconnect Technology Ltd
Unisem (Mauritius) Holdings Ltd
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Advanced Interconnect Technology Ltd
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Abstract

本公开涉及具有电磁屏蔽的半导体器件封装。半导体器件的封装包括对RF干扰进行屏蔽。该封装具有引线框，引线框具有引线和连杆。引线具有连接到器件的内端和具有处于封装侧面的暴露面的外端。连杆也包含具有处于封装侧面的暴露面的端。覆盖引线框的模制料形成侧面的一部分。导电屏蔽物形成封装的顶表面，并且由此向下延伸以形成封装侧面的上部。连杆端处的暴露面具有比引线端的暴露面的上边缘高的上边缘。因此，屏蔽物与邻近其暴露面的连杆电接触，而与引线电隔离。

Description

具有电磁屏蔽的半导体器件封装
技术领域
本公开涉及半导体器件的封装。更具体地，本公开涉及屏蔽了电磁干扰(EMI)的四方扁平无引线(QFN)半导体器件封装。
背景技术
在基于引线框的半导体器件封装中，通过导电引线框在至少一个半导体器件和诸如印刷电路板的外部电路之间传输电信号。引线框包括多根引线，每一根具有内引线端和相对的外引线端。内引线端与器件上的输入/输出焊盘电连接，并且外引线端提供封装体之外的端子。在外引线端终止在封装体面上的情况下，封装被称为“无引线”封装。公知的无引线封装的示例包括四方扁平无引线(QFN)封装，其具有设置在正方形封装体底部的外缘周围的四组引线。在本申请人一同拥有的、于2004年8月11日提交的美国专利No.7563648中公开了QFN封装以及制造该封装的方法，该专利在此通过引用而将其全部内容并入。
在无引线封装中，通常使用导线接合(wire bonding)法、载带自动键合(TAB)法或者倒装芯片法将半导体器件连接到内引线端。在导线接合或者TAB法中，内引线端在距离器件的一定距离上终止，并且通过细直径导线或者导电带与器件顶上的输入/输出(I/O)焊盘电互连。可以由引线围绕的支撑焊盘来支撑器件。在倒装芯片法中，引线框的内引线端在器件下延伸，并且倒装器件，以便器件上的I/O焊盘通过直接电连接(例如，焊料连接)接触内引线端。
在现代封装技术中，使用互连的引线框矩阵来允许同时制造多个封装。这类技术通常包括使用焊料、环氧树脂、双面粘合带等将器件紧固到矩阵中每个引线框的中央支撑焊盘。接下来，将每个引线框的引线导线接合到器件上的I/O焊盘。在导线接合后，使用例如转移或者注入模制工艺将器件、键合导线和引线的至少一部分包封在塑料中。接下来，通过锯切或者冲压将封装单元化(singulate)，露出每个封装的引线的剩余部分以电连接到外部电路。
在图1A中示出了典型的单元化的QFN封装(其中使用导线接合技术连接器件)的截面图。器件1通过粘合层2紧固到支撑焊盘3；导线4将器件顶表面上的I/O焊盘连接到引线14。通过模制料(moldingcompound)5(例如，聚合树脂)覆盖器件、导线接合连接和引线。接下来，通过刀片、喷水器等锯切将封装11与相邻封装分离；锯切操作使得封装面和引线14的一部分露出。
如图1B中所示，在另一种QFN封装布置中，封装12具有与封装11类似的特征，除了蚀刻引线15以在锯切之前去除它们厚度的大约一半。引线15因而被称为“半蚀刻”引线，而引线14是“全”引线。模制料5覆盖引线，以使得封装12(在被单元化之后)具有模制料而非导电材料的角17。
图1C中示出了具有全引线并且由冲压工艺单元化的QFN封装。在封装13中，模制料具有斜边18并且引线16的顶表面的一部分露出。
在封装11-13中，半导体器件1密封在模制料5中(例如，树脂聚合物块)，其提供器件的环境保护。然而，这类设备仍然易于受到电磁干扰(EMI)、特别是降低器件性能的射频(RF)干扰的影响。因此，期望提供具有EMI屏蔽和环境屏蔽的半导体器件封装。
在上述QFN封装中，提供RF屏蔽提出了可以结合图2理解的挑战。图2示出了在单元化之前具有相邻角的4个封装的俯视图。每个封装具有器件支撑焊盘21和引线22(图2中仅示出了与每个焊盘相对的四根引线)。焊盘21通过连杆25连接；引线通过连杆28连接。焊盘通常与连杆共面并且与引线的相邻端共面(例如，在封装11中焊盘3的顶表面8与引线14的顶表面9共面)。有效的RF屏蔽物应当与焊盘电接触，但不与共面引线电接触。在单元化之后(沿着边界线26切割并由此去除连杆28)，每个封装将具有分别与引线22和连杆25一同在23和27露出的面。期望为封装提供RF屏蔽物，以使得器件的上面和下面都被屏蔽，即，在避免与引线短路的同时覆盖模制料的顶部并且还连接到导电支撑焊盘。
发明内容
根据本公开的一个方面，提供了一种具有对RF干扰的屏蔽的半导体器件的封装。该封装包括具有引线和连杆的引线框。引线具有连接到器件的内端和具有暴露面的延伸到封装侧面的外端。连杆具有延伸到封装侧面、也具有暴露面的端。模制料覆盖引线框并且形成封装侧面的一部分。导电屏蔽物覆盖引线框上面的模制料以形成封装的顶表面。连杆的该端的暴露面具有相对于引线的该端的暴露面的上边缘垂直位移的上边缘。因此，屏蔽物与邻近其暴露面的连杆电接触，而与引线电隔离。
根据本公开的另一方面，一种制造半导体器件的封装的方法包括一下步骤：提供包括引线和连杆的引线框，其中引线和连杆的每一个具有顶表面和底表面。在引线和连杆它们各自的外端处(邻近引线框的边界)形成凹槽；在引线中相对于其顶表面形成凹槽，并且在连杆中相对于其底表面形成凹槽。施加模制料以覆盖引线框。接下来，执行切割处理以形成切口，该切口部分垂直地延伸穿过引线框边界上的模制料并且与第一和第二凹槽对齐，从而露出连杆的一部分。形成覆盖模制料并且处于切口的两侧和底部的导电屏蔽材料层，以使屏蔽材料与连杆的暴露部分电接触。接下来，在引线框的边界且与切口对齐地执行单元化处理，从而形成封装侧面。封装侧面因而包括设置在其上部、模制料的暴露部分、引线外端的暴露面和连杆该端的暴露面上的屏蔽材料。
在上述方法中，可以使用块料模制(block mold)工艺施加模制料。又根据本公开的另一方面，使用口袋模制(pocket mold)工艺施加模制料，以使模制料不覆盖引线框邻近引线框边界的部分。因此，在无需切割处理的情况下，导电屏蔽材料层接触引线框的该部分。可以通过锯切或者冲压执行随后的单元化处理。
在以下的附图和说明书中阐述了本发明各个实施例的细节。通过说明书、附图和权利要求，本发明的其它特征、目的和优点将会明显。
附图说明
图1A示意性地例示了具有全引线并且通过锯切单元化的QFN封装的截面图。
图1B示意性地例示了具有半蚀刻引线并且通过锯切单元化的QFN封装的截面图。
图1C示意性地例示了具有全引线并且通过冲压单元化的QFN封装的截面图。
图2示意性地例示了在单元化之前具有相邻角的4个封装的俯视图。
图3A和3B分别例示了根据本公开实施例的引线和连杆的半蚀刻。
图4A-4F例示了根据本公开实施例的受屏蔽且被单元化的器件封装的形成。
图5A和5B分别是图4D的部分锯切在引线和连杆处的局部视图。
图5C和5D分别是与图5A和5B相比更深的部分锯切在引线和连杆处的局部视图。
图6A和6B分别是具有图4F的窄锯切的图5A和5B的引线和连杆的局部视图。
图6C和6D分别是具有图4F的窄锯切的图5C和5D的引线和连杆的局部视图。
图7是根据本公开实施例的半导体器件封装的引线框的俯视立体图。
图8是图7的引线框的角的局部视图。
图9是示出根据本公开实施例的具有电磁屏蔽的封装的角的局部视图。
图10A和10B例示了根据本公开实施例的受屏蔽的器件封装的形成，其中使用块料模制工艺形成封装。
图11A和11B例示了根据本公开另一实施例的受屏蔽的器件封装的形成，其中使用口袋模制工艺形成封装。
图12例示了根据本公开又另一实施例的受屏蔽的器件封装的形成，其中使用口袋模制工艺形成封装。
具体实施方式
根据本公开的实施例，形成具有半蚀刻引线和半蚀刻连杆的QFN封装。图3A示出了相邻引线框的引线22；在单元化处理中沿着边界26分离这些引线。从顶表面30开始蚀刻引线，以在其中形成凹槽31，边界26接近其中心线。凹槽31具有接近引线22的一半厚度的深度31a；表面52形成凹槽31的底部。
如图3B中所示，从底表面32开始蚀刻连杆25，以在其中形成凹槽33，边界26接近其中心线。凹槽33具有接近连杆25的一半厚度的深度33b。在图3B所示的实施例中，凹槽33仅比单元化通道稍宽。在其它实施例中，凹槽33可以朝着管芯焊盘横向延伸，以半蚀刻全部或者基本上全部连杆25。
图4A给出了半蚀刻处理之后的引线框的截面图。在每一个相邻的引线框中(即，在单元化之前)，每根引线22具有接近焊盘21的内端和延伸至边界26的外端。在各自的半蚀刻处理中形成了凹槽31和33之后，器件支撑焊盘21、引线22和连杆25的基本上共面的底表面被粘附到表面40。在所示的实施例中，表面40形成在粘合带上。接下来，如图4B中所示，使用粘合材料42将器件41附着于支撑焊盘并且通过导线44将器件41连接到引线。如图4C中所示，通过模制料45包封器件。而且，模制料45覆盖引线框的暴露面并且填充引线框中位于其顶表面和底表面的凹槽(包括凹槽31和33)。
接下来，如图4D中所示，执行部分单元化处理；沿着边界线26形成锯切口46。锯切口的深度为使得该切口的底部与引线22的顶表面30的平面平齐，或者稍低。
图5A和5B是示出关于引线和连杆的部分切割处理的结果的局部视图。如图5A中所示，锯切口46的底部46b与引线22的顶表面30几乎共面。然而，引线没有露出，因为锯切口与凹槽31对齐；因此，切口的底部46b没有延伸到位于凹槽31的底部的金属表面52。将锯片的宽度选择为远远窄于凹槽31，以使得锯切的微小失准将不会导致引线露出。相对照地，如图5B中所示，锯切口46至少向下延伸到连杆25的顶表面的平面，以使连杆表面的一部分53露出。
图5C和5D例示了关于锯切口46的深度可获得的工艺窗口。在图5C中，锯切口比图5A中的深，但只要锯切口的底部保持在凹槽表面52之上，则引线的表面不会露出。因此，锯切口46的深度的工艺窗口与凹槽31的深度31a有关。类似地，在图5D中，锯切口比图5B中的深，以使锯切口46进一步延伸进连杆25，除表面部分53之外还露出垂直表面54。
在一个实施例中，引线框的厚度(即，表面30和32之间的距离)是8密耳(0.008英寸或者0.02毫米)，凹槽31和33的深度31a和33b通常是引线框厚度的50％到大约65％，或者4密耳(0.004英寸或者0.10毫米)到大约5.2密耳(0.0052英寸或者0.13毫米)。因此，图5D中的锯切口46可以在穿过表面30之后延伸大约0.05mm(50μm)以保证露出表面部分53而避免露出表面52。
如图4E中所示，在模制料45的顶表面以及在锯切口46的侧面和底表面上沉积RF屏蔽的导电材料50。可以通过各种工艺(例如，喷涂、浸涂(dip)、浸镀(immersion)、电镀等)施加屏蔽材料。如图4E中所示，屏蔽材料50不与引线22接触。然而，由于锯切口46露出了连杆表面的一部分53，所以屏蔽材料接触连杆25。
在该实施例中，在沉积材料50之后去除底表面上的保护粘合带。替代地，如果RF屏蔽材料与引线框的最终材料(例如，Sn)相同，则可以在去除粘合带之后沉积屏蔽物。还可以在去除粘合带之后执行屏蔽材料的无电镀或者电解电镀。
如图4F中所示，由形成锯切口51的第二锯切处理来执行最终的单元化。在该实施例中，使用比第一锯切更窄的锯片。图6A和6B是分别示出引线和连杆处的第二锯切的结果的局部视图。在图6A和6B中，屏蔽材料设置在各单元化的封装的侧面上，并且向下延伸到引线框的顶表面30的平面。由于上述的半蚀刻处理，屏蔽材料50不与引线22接触，但接触连杆25。如图6A中所示，锯切口51使位于引线22的一端并且邻近引线框的底表面32的区域124露出。锯切口51将凹槽31(由模制料45填充)划分为两段126，每一段邻近顶表面30。凹槽段126的侧壁64没有露出并且通过模制料45与屏蔽材料50隔开。如图6B中所示，锯切口51使位于连杆25的一端并且邻近引线框的顶表面30的区域94露出。屏蔽材料50向下延伸到露出区域94并且与其相连。锯切口51将连杆25的凹槽33(由模制料45填充)划分为两段96，每一段从锯切口51所形成的角和底表面32开始横向延伸。如上面关于图3B所述，凹槽33可以朝着管芯焊盘横向延伸，以半蚀刻全部或者基本上全部连杆25。因此，在每一个单元化的封装中，凹槽96可以沿着连杆25的整个长度延伸。
通过区域124和表面52的交点限定露出区域124的上边缘；通过区域94和表面30的交点限定露出区域94的上边缘。作为形成凹槽31的结果，表面30高于表面52。因此，通过凹槽31的深度31a确定区域94和124的各上边缘在封装侧面上的垂直位移。
在第一锯切延伸到引线框的顶表面30的平面之下的情况下(图5C和5D)，图6C和6D分别示出了第二锯切的结果。在图6C中，与图6A中相比，屏蔽材料50朝着引线22的端进一步延伸，但仍然不与引线接触。在图6D中，屏蔽材料50覆盖连杆25的暴露端，并因此如同图6B中一样与连杆电接触。
第二锯切处理具有相对于切口51的深度而言的宽工艺窗口。锯切口51(从表面32开始延伸)仅仅需要穿过锯切口46的底部的屏蔽材料；因此，锯切口51的深度不取决于锯切口46的深度。选择第二锯片的宽度以使得即使第一和第二锯片存在微小失准，第二锯切也能穿过锯切口46的底部，并且使得第二锯片不损坏锯切口46的侧壁上的屏蔽材料50。因此，锯片宽度的差别至少是所沉积的屏蔽材料的厚度的两倍。有利的是，翻转引线框的底部来执行第二锯切处理，以从表面32开始向下进行第二锯切。
图7中示出了根据本公开实施例的单元化的封装的引线框。(出于清楚的目的，省略了模制料和屏蔽材料。)引线22(以及它们与器件支撑焊盘21相对的内端)延伸至封装的四侧，以使它们外端上的表面124在封装的侧面露出。连杆25(与器件支撑焊盘21一体)从焊盘开始朝着封装的角对角地延伸。连杆终止于在封装侧面上露出的表面94。
图8是示出图7引线框的一个角的局部视图。引线22和连杆25具有共同的顶表面30和底表面32。应当理解，表面30和32分别延伸到管芯焊盘的顶表面和底表面。然而，在封装侧面，引线22具有凹槽126，而连杆25具有凹槽96。因此，暴露面124和94处在相对于顶表面和底表面的不同高度上。如上所述，由于表面30高于表面52，暴露面124和94的上边缘具有由引线中凹槽31的深度31a给出的垂直位移。如上面关于图3B和6B所述，凹槽96可以从封装面开始朝着管芯焊盘延伸，以使连杆25(在具有与引线22共面的顶表面30时)可以具有接近引线厚度的一半的厚度。
图9示出了包括模制料45和屏蔽材料50的相同引线框角。屏蔽材料50覆盖模制料45且形成封装的顶表面，并且向下延伸以形成封装侧面的上部。表面94相对于表面124(其邻近引线框的底表面)垂直位移。屏蔽材料50与表面94相连续，并由此电连接到连杆25和器件支撑焊盘21，但与表面124隔离。因此，在器件的上面、四周和下面提供RF屏蔽，而封装的引线具有暴露面124以电连接至外部电路。
图9例示了锯切口46使连杆25的顶表面露出，但基本上不切进连杆(参见图6B)的情况。在此情况下，屏蔽物50与连杆接触但基本上不覆盖露出的端表面94。在锯切口46更深(参见图6D)的情况下，屏蔽物覆盖连杆端的至少一部分，以减小处于连杆端的暴露面的高度。
将会认识到，可以通过块料模制或者口袋模制施加模制料(例如，聚合树脂)。而且，可以在模制处理中施加屏蔽材料。图10A和10B例示了根据本公开实施例的具有模制屏蔽物的块料模制封装的形成。在块料模制处理中，通过模制料145覆盖引线框阵列，以不露出意欲连接到屏蔽物的引线框部分。因此，需要部分切割处理(图10A)来露出每个引线框的一部分。接下来，可以在模制料上施加屏蔽材料150(例如，通过注入模制工艺)，填充锯切口46，接触引线框，并且在封装的顶部形成层(图10B)。可以使用合适的工艺(锯切、激光切割、水切(water ablation)等)将封装单元化。
图11A和11B例示了根据本公开又一实施例的具有模制屏蔽物的口袋模制封装的形成。在图11A中示出了具有由口袋模制施加的模制料245的引线框的阵列。口袋模制工艺在模制料245中沿着引线框之间的边界留下空腔246(图11A)。因此，露出意欲连接到屏蔽物的引线框部分(在这些实施例中，连杆的外端)。因此，不需要部分切割处理。接下来，可以在模制料上施加屏蔽材料250(例如，通过注入模制工艺)，填充空腔246，接触引线框，并且在封装的顶部形成层(图11B)。如前一实施例中一样，可以使用多种工艺中的任何一种将封装单元化。
在另一实施例中，如图12所示，形成具有由口袋模制施加的模制料245的引线框的阵列，如图11A中一样；接下来，在模制料245的顶表面沉积用于RF屏蔽的导电材料350的共形层。可以通过喷涂或者另外的合适工艺(例如，浸涂、浸镀、电镀等)施加屏蔽材料350。在该实施例中，可以通过冲压以及锯切、激光切割、水切等将封装单元化。
上述封装的每一个具有附着于支撑焊盘并且与引线导线连接的单个器件。在本公开的又一实施例中，可以按单层或者按叠层布置将多个器件附着于焊盘。还可以在封装中包含无源元件并且在施加RF屏蔽物之前将无源元件与器件和/或引线进行导线连接；因此，可以提供受屏蔽的系统级封装。在附加实施例中，可以按倒装芯片的布置将器件附着于引线。为了向器件提供更完全的屏蔽，可以在器件下面(即，与器件相对并且远离器件)设置连接到屏蔽物但不与器件接触的导体。
尽管已经根据特定实施例描述了本公开，但鉴于前述说明，很显然，许多替代、修改及变化对于本领域技术人员而言将是明显的。因此，本公开意欲涵盖落入本公开和下列权利要求的范围和精神之内的所有这类替代、修改和变化。

Claims (25)

1.一种半导体器件的封装，包含：
引线框，包括
引线，具有连接到所述器件的内端和延伸到所述封装的侧面的外端，所述引线的所述外端具有在所述封装的所述侧面露出的第一表面，以及
连杆，具有延伸到所述封装的所述侧面的一端，所述连杆的所述端具有在所述封装的所述侧面露出的第二表面；
模制料，覆盖所述引线框并且形成所述封装的所述侧面的一部分；以及
导电屏蔽物，覆盖所述引线框上方的所述模制料以形成所述封装的顶表面并且由此向下延伸以形成所述封装的所述侧面的上部，
其中所述第二表面具有相对于所述第一表面的上边缘垂直位移的上边缘，以及
所述屏蔽物与邻近所述第二表面的所述连杆电接触，而与所述引线电隔离。
2.如权利要求1所述的封装，还包含：连接到所述连杆并由此连接到所述屏蔽物的用于所述器件的支撑焊盘。
3.如权利要求2所述的封装，还包含：所述半导体器件，所述半导体器件附着于所述支撑焊盘并且电连接至所述引线。
4.如权利要求1所述的封装，其中
所述引线框具有顶表面和底表面，
所述引线和所述连杆的顶表面和底表面除了凹槽部分之外分别与所述引线框的所述顶表面和所述底表面共面。
5.如权利要求4所述的封装，其中所述引线的所述外端具有相对于所述引线框的所述顶表面的凹槽部分，以使所述第一表面邻近所述引线框的所述底表面，而所述第一表面的所述上边缘低于所述引线框的所述顶表面。
6.如权利要求5所述的封装，其中所述凹槽部分的顶表面低于所述连杆的所述顶表面。
7.如权利要求4所述的封装，其中所述连杆的至少一个端部分具有相对于所述引线框的所述底表面的凹槽部分，以使所述第二表面邻近所述引线框的所述顶表面，而所述第二表面的下边缘在所述引线框的所述底表面之上。
8.如权利要求1所述的封装，其中所述屏蔽物覆盖所述连杆在所述封装的所述侧面的所述端的一部分。
9.如权利要求4所述的封装，其中
所述引线框具有由其所述顶表面和所述底表面之间的距离给出的厚度，
所述引线的所述外端相对于所述引线框的所述顶表面凹入接近所述厚度一半，并且
所述连杆的所述端相对于所述引线框的所述底表面凹入接近所述厚度一半。
10.如权利要求1所述的封装，还包含：所述半导体器件，所述半导体器件以倒装芯片的布置附着于所述引线。
11.如权利要求10所述的封装，还包含：连接到所述连杆且与所述半导体器件相对、并且与其分开的导体。
12.一种制造半导体器件的封装的方法，包含：
提供包括引线和连杆的引线框，所述引线框具有顶表面和底表面，
在邻近所述引线框的边界的所述引线的外端处形成所述引线中相对于所述顶表面的第一凹槽；
在邻近所述引线框的边界的所述连杆的至少一端处形成所述连杆中相对于所述底表面的第二凹槽；
施加覆盖所述引线框的模制料；
执行切割处理以形成切口，该切口部分垂直地延伸穿过位于所述引线框的所述边界上的所述模制料并且与所述第一凹槽和所述第二凹槽对齐，从而露出所述连杆的一部分，
形成覆盖所述模制料并且位于所述切口的侧面和底部上的导电屏蔽材料层，以使所述屏蔽材料与所述连杆的所述露出部分电接触；
在所述引线框的所述边界并且与所述切口对齐地执行单元化处理，从而形成封装侧面，所述封装侧面包括
在其上部设置的屏蔽材料，
所述模制料的露出部分，
位于所述引线的所述外端处的露出的第一表面，以及
位于所述连杆的所述端处的露出的第二表面。
13.如权利要求12所述的方法，其中所述引线框还包含：连接到所述连杆的器件支撑焊盘。
14.如权利要求13所述的方法，还包含：提供所述半导体器件，将所述半导体器件附着于所述支撑焊盘并且将所述半导体器件电连接到所述引线。
15.如权利要求12所述的方法，其中
所述引线的顶表面和底表面与所述连杆的顶表面和底表面分别基本上共面，以使所述引线和所述连杆的每一个具有基本上相等的厚度，并且
所述第一凹槽和所述第二凹槽的每一个形成有大约所述厚度一半的深度。
16.如权利要求12所述的方法，其中使用具有第一厚度的锯执行所述切割处理，并且所述单元化处理是使用具有比所述第一厚度小的第二厚度的锯执行的附加切割处理。
17.如权利要求12所述的方法，其中使用锯执行所述切割处理，并且所述单元化处理是冲压处理。
18.如权利要求12所述的方法，其中所述引线框设置在粘合带上，并且还包含：在所述形成屏蔽材料层的步骤之后去除所述粘合带的步骤。
19.如权利要求12所述的方法，其中通过喷涂、浸涂、浸镀、电镀、无电镀和电解电镀中的一种或更多种形成所述屏蔽材料层。
20.如权利要求12所述的方法，其中使用块料模制施加所述模制料。
21.如权利要求20所述的方法，其中所述形成所述屏蔽材料层的步骤包含所述屏蔽材料的注入模制。
22.一种制造半导体器件的封装的方法，包含：
提供包括引线和连杆的引线框，所述引线框具有顶表面和底表面，
在邻近所述引线框的边界的所述引线的外端处形成所述引线中相对于所述顶表面的第一凹槽；
在邻近所述引线框的边界的所述连杆的至少一端处形成所述连杆中相对于所述底表面的第二凹槽；
使用口袋模制工艺在所述引线框上施加模制料，以使所述模制料不覆盖所述引线框的邻近所述引线框的所述边界的部分；
形成覆盖所述模制料并且与所述模制料没有覆盖的所述引线框的所述部分接触的导电屏蔽材料层；
在所述引线框的所述边界并且与所述第一凹槽和所述第二凹槽对齐地执行单元化处理，从而形成封装侧面，所述封装侧面包括
在其上部设置的屏蔽材料，
所述模制料的露出部分，
位于所述引线的所述外端处的露出的第一表面，以及
位于所述连杆的所述端处的露出的第二表面。
23.如权利要求22所述的方法，其中所述单元化处理是切割处理和冲压处理中的一种。
24.如权利要求22所述的方法，其中通过喷涂、浸涂、浸镀、电镀、无电镀和电解电镀中的一种或更多种形成屏蔽材料层。
25.如权利要求22所述的方法，其中所述形成所述屏蔽材料层的步骤包含所述屏蔽材料的注入模制。
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