CN102931161B - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN102931161B
CN102931161B CN201210428108.1A CN201210428108A CN102931161B CN 102931161 B CN102931161 B CN 102931161B CN 201210428108 A CN201210428108 A CN 201210428108A CN 102931161 B CN102931161 B CN 102931161B
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those
pin
semiconductor package
pins
chip carrier
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CN102931161A (zh
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余林旺
胡平正
张哲钦
蔡裕方
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种半导体封装件及其制造方法，包括一芯片座、设置于芯片座上的一芯片及设置于芯片座旁的一第一引脚。第一引脚包含一接触部、实质上沿芯片座方向延伸的一延伸部及设置于接触部及延伸部之间的一凹曲侧表面。具有一凹曲侧表面的一第二引脚也设置于芯片座旁。第一引脚的凹曲侧表面的方向相反于第二引脚的凹曲侧表面。

Description

半导体封装件及其制造方法
技术领域
本发明涉及一种半导体单元及其制作方法，且特别是涉及一种四方扁平无引脚（QuadFlatNoLead,QFN）封装结构及其制作方法。
背景技术
半导体封装技术包含有许多封装形态，四方扁平无引脚封装即为其中之一，四方扁平无引脚封装具有较短的信号传递路径及相对较快的信号传递速度，因此四方扁平无引脚封装适用于高频传输（例如射频频带）的芯片封装，且为低脚位（lowpincount）封装型态的主流之一。
在四方扁平无引脚封装的制造方法中，多个芯片被固定于一导线架基材的多个芯片座上。这些芯片经由接合引线（bondingwires）电连接至导线架的引脚（leads）。这些引脚、接合引线与芯片被模制化合物（moldingcompound）或包封材料（encapsulant）封装与保护。这些引脚的底部暴露于封装材料之外以电连接至一外接装置，此基材可被分割出个别的四方扁平无引脚封装。
当四方扁平无引脚封装的尺寸增加时，芯片与引脚之间的距离增加，由于电信号需要传输较长距离，因而降低了封装的表现。其中一个解决方法是增加引脚的延伸部以减少接合引线的长度。然而，当引脚的延伸部被暴露于包封材料之外且未连接于任何外接装置时，暴露于空气下的引脚的延伸部便容易氧化。
发明内容
为解决上述问题，本发明提出一种半导体封装件包括一芯片座、设置于芯片座上的一芯片及设置于芯片座旁的一第一引脚。第一引脚包含一接触部、实质上沿芯片座方向延伸的一延伸部及设置于接触部及延伸部之间的一凹曲侧表面。具有一凹曲侧表面的一第二引脚也设置于芯片座旁。第一引脚的凹曲侧表面的方向相反于第二引脚的凹曲侧表面。
本发明还提出一种半导体封装件，包括一芯片座、设置于芯片座上的一芯片以及设置于芯片座旁的一第一引脚。第一引脚包含一凹曲侧表面，第一引脚的凹曲侧表面朝向半导体封装件的一下表面。一第二引脚设置于芯片座及第一引脚之间，第二引脚包含一凹曲侧表面，第二引脚的凹曲侧表面朝向半导体封装件的一上表面。
本发明再提出一种多个半导体封装件的制造方法，包括下列步骤，设置多个芯片于多个导线架上，其中每一导线架包含相对的一上表面与一下表面、一凹穴、多个第一凹口及多个第二凹口，其中（1）这些第一凹口形成于下表面且定义出多个第一引脚、多个延伸部以及连接这些第一引脚的这些延伸部的多个支持肋，（2）这些第二凹口形成于上表面且定义出多个第二引脚与多个芯片座，（3）这些凹穴的深度小于这些第二凹口的深度，（4）至少一第一凹口连通于至少一第二凹口。本方法还进一步包含芯片通过多个接合引线电连接于这些延伸部及这些第二引脚。本方法还进一步包含形成一封装板体以覆盖这些芯片及这些接合引线且填充这些第一凹口及这些第二凹口。本方法还进一步包含自这些下表面移除每一引脚架的一部分与封装板体的一部分以电性隔离这些芯片、这些第一引脚及这些第二引脚。本方法还进一步包含通过切割封装板体且移除这些支持肋而将每一芯片分开以形成这些半导体封装件。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1F是本发明的一实施例的一种导线架的制造方法的步骤的剖面示意图；
图1G至图1N是本发明的一实施例的一种半导体封装件的制造方法的步骤的剖面示意图；
图2是图1F的导线架的上表面的局部俯视示意图；
图3是本发明的一实施例的另一种半导体封装件的剖面示意图。
主要单元符号说明
10、30：掩模层
12、14、20：图案化掩模层
40：加热块
50：保护层
100、200：半导体封装件
110：导线架条
110a：导电基材
110b：金属层
110c：导线架
111：上表面
112：下表面
113：芯片座
113a：凹穴
113b：外表面
113c：曲内表面
114：第一凹口
114a：凹入部分
115：第二凹口
116：第一引脚
116a：外表面
116b：凹曲侧表面
117：延伸部
117b：下表面
118：第二引脚
118a：外表面
118b：凹曲侧表面
119：支持肋
119a：连结杆
120：芯片
130：接合引线
160：模制化合物
160a：下表面
170：焊球
210b：第二金属层
具体实施方式
请参考图1A，其绘示一导电基材110a具有相对的一上表面111及一下表面112。导电基材110a的材料可以是铜、铁或是其他导电材料。一掩模层10被形成以全面地覆盖在导电基材110a的上表面111，且以一图案化掩模层20覆盖导电基材110a的下表面112的一部分。在本实施例中，掩模层10与图案化掩模层20可以是一干膜光致抗蚀剂或一湿膜光致抗蚀剂。
请参考图1B，以上述图案化掩模层20当作蚀刻掩模，一半蚀刻程序作用于导电基材110a的下表面112以在导电基材110a上未被图案化掩模层20覆盖的部分形成第一凹口114。第一凹口114定义出可用来当作外部引脚的第一引脚116。当此半蚀刻程序作用时，掩模层10覆盖且保护导电基材110a的上表面111。完成此半蚀刻程序后，掩模层10与图案化掩模层20被移除。
请参考图1C，一掩模层30被用来全面覆盖下表面112且填入第一凹口114。一金属层110b选择性地电镀于上表面111，且一图案化掩模层12被形成以覆盖金属层110b。金属层110b为一抗氧化层，例如为一表面处理层，举例来说可以是金、钯、镍、上述成分的混合物或是其他材料等。请参阅图2，图案化掩模层12定义出多个芯片座113、第一引脚116、第一引脚116的延伸部117、可用来当作内部引脚118的第二引脚118及支持肋119的图案。延伸部117与第一引脚116一体且向内并朝向对应的芯片座113延伸。
图1C’描述了相似于图1C的实施例的另一实施例，除了图1C’的实施例中金属层110b的图案不同于图1C的实施例。由于图案化掩模层12被当作蚀刻掩模使用，金属层110b只形成于用来当作接点的区域。
请参考图1D，使用图案化掩模层12来当作一蚀刻掩模，一半蚀刻程序作用于导电基材110a的上表面111以在导电基材110a上未被图案化光致抗蚀剂层12覆盖的部分形成多个第二凹口115与这些芯片座113的多个凹穴113a。这些第二凹口115与这些凹穴113a的侧面具有凹曲的轮廓。
请参阅图1E，一第二图案化掩模层14被形成以覆盖这些凹穴113a。使用图案化掩模层12与第二图案化掩模层14作为蚀刻掩模，还有一半蚀刻程序作用于导电基材110a以增加第二凹口115的深度。在此半蚀刻程序完成之后，部分第二凹口115连通于第一凹口114，以使这些第一引脚116与这些第二引脚118可在电性上及物理上相互隔绝。值得注意的是，在图1E中，第一凹口114与第二凹口115似乎是被分开的，但在移除掩模层30后，第一凹口114连通于第二凹口115（如图1F所示）。
请参阅图1F，在图案化掩模层12、第二图案掩模阻层14与掩模层30被移除之后，即完成具有多个导线架110c的一导线架条（leadframestrip）110。每一导线架110c具有芯片座113、凹穴113a、第一凹口114、第二凹口115、第一引脚116、第一引脚116的延伸部117、第二引脚118及金属层110b。请参阅图2，这些第一引脚116被连接至这些支持肋119，这些支持肋119被连接至这些连结杆（tiebars）119a，且这些连结杆119a被连接至这些芯片座113以托住这些芯片座113。第一引脚116与第二引脚118具有凹曲的轮廓。芯片座113的凹穴113a的深度d1小于第二凹口115的深度d2，此在将芯片座113与第二引脚118隔绝的过程后，可保留芯片座113的部分厚度。其在图1L中的步骤中有更详细的叙述。凹穴113a也具有一平坦区域，用以放置一芯片。此外，支持肋119被设置在两邻近的第一引脚116之间。在本实施例中，支持肋119被使用去连接多个引脚架110c，以便同时制造多个半导体封装件。在本实施例中以两个导线架被支持肋119连接为例，以表现出导线架实际上以阵列的方式制作的状况。
图1G至图1N是依照本发明的一实施例的一种半导体封装件的制造方法的步骤的剖面示意图。请参阅图1G，这些芯片120被设置于芯片座113的凹穴113a内。这些芯片120可以被例如是粘着层、银胶（colloidalsilver）或是其他适合的材料固定于凹穴113a内。凹穴113a具有朝向芯片120的一曲内表面113c。
请参阅图1H，芯片120利用多个接合引线130以电连接至第一引脚116的延伸部117、第二引脚118及芯片座113。一加热块（heatingblock）40可被使用来支撑且加热导线架条110的第一引脚116及第二引脚118。加热块40设置于下表面112且伸入第一凹口114以支撑第一引脚116的延伸部117。加热块40可加热接合引线130与延伸部170之间的界面以增强共晶结合。此外，由于芯片120经由连接于芯片120及延伸部117之间的接合引线130电连接至第一引脚116，相较于不具有延伸部117的结构，本实施例的半导体封装件100的接合引线130的长度可被缩短。
请参阅图1I，一保护膜50被粘附于导线架条110的下表面112。保护膜50例如可以是一预模胶带（pre-moldtape）。保护膜50不延伸入第一凹口114。
请参阅图1J，一模制化合物160被形成以覆盖芯片120、芯片座113、第二凹口115、第一引脚116、第二引脚118、支持肋119及接合引线130。如同上述，部分的第一凹口114在凹入部分114a以连接至第二凹口115。因此，模制化合物160可自第二凹口115流至第一凹口114以包封第一引脚116的延伸部117。粘附至导线架条110的下表面112的保护膜50避免模制化合物160溢流至下表面112。
请参阅图1K，保护膜50被移除。虽然此部分并未表示于图中，模制化合物160的下表面可能从导线架110c的下表面112被轻微地挤压。请参阅图1L，其表示一作用于导线架条110的下表面112以移除部分导电基材110a与部分模制化合物160而暴露出第二凹口115以使芯片座113与第二引脚118在电性与物理上相互隔绝的程序。此程序例如可以是研磨、抛光、蚀刻或是其他合适的程序。因此第一引脚116的外部表面116a与第二引脚118的外部表面118a被暴露而提供了这些接触部。在本实施例中，由于凹穴113a的第一深度d1小于第二凹口115的第二深度d2，凹穴113a在此过程中并不会被暴露。因此，芯片座113仍存在一厚度且在此过程完成后只有芯片座113的外表面113b被暴露。外表面113b,116a,118a与模制化合物160的下表面160a共平面。由于第二凹口115与芯片座113的凹穴113a经半蚀刻程序而形成，芯片座113与第二引脚118的侧表面具有凹曲的轮廓。更特别的是，在本实施例的半导体封装件100中，第一引脚116具有开口于一第一方向的曲面或凹曲的侧表面116b，一般来说曲面或凹曲的侧面表面116b的方向朝下，且第二引脚118具有开口于相对于第一方向的一第二方向的曲面或凹曲的侧表面118b，一般来说曲面或凹曲的侧表面118b的方向朝上。此几何结构提供引脚与模制化合物160在机械力上的内连结，以抵抗这些引脚自模制化合物160分离。此几何结构也导致第一引脚116的外表面116a的表面区域小于第二引脚118的外表面118a的表面区域。
请参阅图1M，多个焊球170配置于芯片座113、第一引脚116及第二引脚118的外表面113b、116a、118a，外表面113b、116a、118a暴露于模制化合物160外。这些焊球170有助于抵抗外表面113b、116a、118a氧化。焊球170也被使用于电连接至例如电路板的外部电路（未绘示）。焊球170可经由例如是一浸焊过程（dipsolderingprocess）、一焊锡印刷过程、一无电电镀过程或其他过程而形成。
请参阅图1N，一分割程序被进行以移除支持肋119及模制化合物160的一部分以形成多个半导体封装件100。分割程序可能包含激光切割或机械切割等。
第一引脚116与第二引脚118的凹曲侧表面116b、118b以及第一引脚116的延伸部117的下表面117b被模制化合物160包封。只有芯片座113的外表面113b、第一引脚116的外表面116a及第二引脚118的外表面118a暴露。因此，可避免第一引脚116、第一引脚116的延伸部117及第二引脚118被包封的部分发生氧化。此外，芯片座113的曲内表面113c、第一引脚116与第二引脚118的凹曲侧表面116b、118b成为锁固结构以避免芯片座113、第一引脚116与第二引脚118自模制化合物160脱离。
图2绘示图1F的导线架的上表面的局部俯视示意图。为了使读者了解第一引脚116与支持肋119之间的连接关系，在图2中仅就上表面111来描述，图1D的金属层110b并未绘示。图2中的影线（hatching）指出导线架条100已从下方被半蚀刻。支持肋119连接位于两邻近导线架110c的边缘的第一引脚116。因此，支持肋119连接邻近的导线架110c去形成一导线架条110，以使多个半导体封装件100可被同时制造。
关于图2，第一引脚116的延伸部117以非零角度朝远离第一引脚116的方向延伸。在另一实施例中，延伸部117以任何角度朝远离第一引脚116的方向延伸，包括沿着与第一引脚116相同的直线。延伸部117与第二引脚118之间的距离可被减少，以助于降低连接芯片120与延伸部117的接合引线130的长度。
请参阅图3，图3是依照本发明的一实施例的另一种半导体封装件的剖面示意图。图3的半导体封装件200与图1N的半导体封装件100的差异仅在于，图3的半导体封装件200以一第二金属层210b配置于芯片座113的外表面113b、第一引脚116的外表面116a及第二引脚118的外表面118a。第二金属层210b可避免芯片座113的外表面113b、第一引脚116的外表面116a及第二引脚118的外表面118a的氧化。此外，半导体封装件200经由此第二金属层210b电连接至例如是电路板的一外部电路（未绘示）。第二金属层210b的材料可选自于由金、钯、镍或其混合物所组成的群组，但不限于上述材料。第二金属层210b的材料可与金属层110b的材料不同。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附的权利要求所界定的为准。

Claims (20)

1.一种半导体封装件，包括：
芯片座；
芯片，设置于该芯片座上；
第一引脚，设置于该芯片座旁，该第一引脚包含一接触部、实质上沿该芯片座的方向延伸的一延伸部及设置于该接触部及该延伸部之间的一凹曲侧表面；以及
第二引脚，设置于该芯片座旁，该第二引脚在面对该第一引脚的一侧仅具有一凹曲侧表面；
其中，该第一引脚的该凹曲侧表面朝向该第二引脚的该凹曲侧表面，且该第一引脚的该凹曲侧表面朝向该半导体封装件的一下表面及该第二引脚的该凹曲侧表面朝向该半导体封装件的一上表面。
2.如权利要求1所述的半导体封装件，其中该第一引脚的该凹曲侧表面位于该第一引脚的一上表面下方。
3.如权利要求2所述的半导体封装件，其中该第一引脚的该凹曲侧表面容纳位于该第一引脚底部的一模制化合物的一部分以将该第一引脚固定在该半导体封装件内。
4.如权利要求1所述的半导体封装件，其中该芯片座包含凹穴，该凹穴具有朝向该芯片的一曲内表面。
5.如权利要求1所述的半导体封装件，还包括：
金属层，配置于该些第一引脚、该些第二引脚及芯片座的下表面，其中该金属层突出于该半导体封装件的一下表面。
6.如权利要求1所述的半导体封装件，还包括一模制化合物，该模制化合物覆盖该些第一引脚、该些第二引脚的该些凹曲侧表面及该些延伸部的下表面，且暴露出该些第一引脚、该些第二引脚及该芯片座的下表面。
7.如权利要求1所述的半导体封装件，其中该延伸部斜向地延伸于该接触部与该芯片座之间。
8.如权利要求7所述的半导体封装件，还包括：
多个第一引脚，其中该些第一引脚成对地分组且每对第一引脚的该些延伸部背离该第一引脚且朝向该芯片座延伸。
9.如权利要求1所述的半导体封装件，其中该第一引脚的外表面的表面区域小于该第二引脚的外表面的表面区域。
10.如权利要求1所述的半导体封装件，还包括一模制化合物，该模制化合物包含一下表面，该下表面与该芯片座、该些第一引脚及该些第二引脚的该些下表面共平面。
11.一种半导体封装件，包括：
芯片座；
芯片，设置于该芯片座上；
第一引脚，设置于该芯片座旁，该第一引脚包含一凹曲侧表面，该第一引脚的该凹曲侧表面朝向该半导体封装件的一下表面；
第二引脚，设置于该芯片座及该第一引脚之间，该第二引脚在面对该第一引脚的一侧仅具有一凹曲侧表面，该第二引脚的该凹曲侧表面朝向该半导体封装件的一上表面；以及
模制化合物，该模制化合物覆盖该芯片与该些第一引脚、该些第二引脚的上表面及该些凹曲侧表面，且暴露出该些第一引脚、该些第二引脚及该芯片座的下表面。
12.如权利要求11所述的半导体封装件，其中该第一引脚的该凹曲侧表面位于该第一引脚的一上表面下方。
13.如权利要求12所述的半导体封装件，其中该第一引脚的该凹曲侧表面容纳位于该第一引脚底部的一模制化合物的一部分以将该第一引脚固定在该半导体封装件内。
14.如权利要求11所述的半导体封装件，其中该芯片座还包含具有一曲内表面的一凹穴，该凹穴的该曲内表面朝向该芯片及该半导体封装件的该上表面。
15.如权利要求11所述的半导体封装件，其中该第一引脚包含一接触部及斜向地延伸于该接触部与该芯片座之间的一延伸部。
16.如权利要求15所述的半导体封装件，还包括：
多个第一引脚，其中该些第一引脚成对地分组且每对第一引脚的该些延伸部背离该第一引脚且朝向该芯片座延伸。
17.如权利要求11所述的半导体封装件，其中该第一引脚的外表面的表面区域小于该第二引脚的外表面的表面区域。
18.一种多个半导体封装件的制造方法，包括：
设置多个芯片于多个导线架上，其中每一导线架包含相对的上表面与下表面、凹穴、多个第一凹口及多个第二凹口，其中(1)该些第一凹口形成于该下表面且定义出多个第一引脚、多个延伸部以及连接该些第一引脚的该些延伸部的多个支持肋，(2)该些第二凹口形成于该上表面且定义出多个第二引脚与多个芯片座，该些第二引脚在面对该些第一引脚的一侧仅具有一凹曲侧表面，且该第二引脚的该凹曲侧表面朝向该半导体封装件的上表面，(3)该些凹穴的深度小于该些第二凹口的深度，(4)该些第一凹口的至少其一连通于该些第二凹口的至少其一；
该芯片通过多个接合引线电连接于该些延伸部及该些第二引脚；
形成一封装板体以覆盖该些芯片、该些接合引线及该些导线架的该些上表面且填充该些第一凹口及该些第二凹口；
自该些下表面移除每一导线架的一部分与该封装板体的一部分以电性隔离该些芯片、该些第一引脚及该些第二引脚；以及
通过切割该封装板体且移除该些支持肋而将每一芯片分开以形成该些半导体封装件。
19.如权利要求18所述的多个半导体封装件的制造方法，其中在该芯片通过多个接合引线电连接于该些延伸部及该些第二引脚的步骤中，该导线架被一加热块支撑，且该加热块被放置在该些下表面且延伸至该些第一凹口的一部分以支撑该些延伸部。
20.如权利要求18所述的多个半导体封装件的制造方法，其中在形成该封装板体的步骤中，包含：
粘附一保护膜至该些导线架的该些下表面；
注入一模制化合物以形成该封装板体以覆盖该些芯片及该些接合引线，其中该模制化合物自该些第二凹口流至该些第一凹口以使该模制化合物填充于该第一凹口与第二凹口；以及
移除该保护膜。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5678727B2 (ja) * 2011-03-03 2015-03-04 セイコーエプソン株式会社 振動デバイス、振動デバイスの製造方法、電子機器
US8871572B2 (en) 2012-12-20 2014-10-28 Intersil Americas LLC Lead frame having a perimeter recess within periphery of component terminal
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US9368423B2 (en) * 2013-06-28 2016-06-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package
TWI582913B (zh) * 2013-08-02 2017-05-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9978667B2 (en) 2013-08-07 2018-05-22 Texas Instruments Incorporated Semiconductor package with lead frame and recessed solder terminals
JP6210818B2 (ja) * 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
DE102014104819A1 (de) * 2014-03-26 2015-10-01 Heraeus Deutschland GmbH & Co. KG Träger und/oder Clip für Halbleiterelemente, Halbleiterbauelement und Verfahren zur Herstellung
US9748165B2 (en) * 2014-05-30 2017-08-29 Delta Electronics, Inc. Packaging structure
JP6617955B2 (ja) * 2014-09-16 2019-12-11 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
US9379087B2 (en) * 2014-11-07 2016-06-28 Texas Instruments Incorporated Method of making a QFN package
US9748187B2 (en) 2014-12-19 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and method for wafer dicing
TWI606555B (zh) 2015-05-15 2017-11-21 尼克森微電子股份有限公司 晶片封裝結構及其製造方法
CN109698181B (zh) * 2015-05-15 2023-08-18 无锡超钰微电子有限公司 芯片封装结构
US9515032B1 (en) 2015-08-13 2016-12-06 Win Semiconductors Corp. High-frequency package
JP6757274B2 (ja) * 2017-02-17 2020-09-16 新光電気工業株式会社 リードフレーム及びその製造方法
US10128169B1 (en) * 2017-05-12 2018-11-13 Stmicroelectronics, Inc. Package with backside protective layer during molding to prevent mold flashing failure
US10529672B2 (en) 2017-08-31 2020-01-07 Stmicroelectronics, Inc. Package with interlocking leads and manufacturing the same
DE102018128109A1 (de) * 2018-11-09 2020-05-14 Infineon Technologies Ag Ein clip mit einem diebefestigungsabschnitt, der konfiguriert ist, um das entfernen von hohlräumen beim löten zu fördern
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
FR3089055B1 (fr) * 2018-11-23 2021-08-27 Linxens Holding Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré.
JP2021044532A (ja) 2019-03-25 2021-03-18 ローム株式会社 電子装置、電子装置の製造方法、およびリードフレーム
CN110323141B (zh) * 2019-04-15 2021-10-12 矽力杰半导体技术(杭州)有限公司 引线框架结构，芯片封装结构及其制造方法
US11133241B2 (en) * 2019-06-28 2021-09-28 Stmicroelectronics, Inc. Semiconductor package with a cavity in a die pad for reducing voids in the solder
US11862538B2 (en) * 2021-08-31 2024-01-02 Texas Instruments Incorporated Semiconductor die mounted in a recess of die pad
TWI776739B (zh) * 2021-11-23 2022-09-01 南茂科技股份有限公司 晶片封裝結構

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101533825A (zh) * 2008-03-14 2009-09-16 日月光半导体制造股份有限公司 半导体封装结构及其工艺与表面粘着型半导体封装结构
CN102280431A (zh) * 2011-08-01 2011-12-14 日月光半导体制造股份有限公司 具有保护层的半导体封装及其制作方法

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3060020B2 (ja) 1991-12-17 2000-07-04 イビデン株式会社 電子部品搭載装置の製造方法
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR100300666B1 (ko) 1997-08-04 2001-10-27 기타지마 요시토시 수지밀봉형반도체장치와거기에사용되는회로부재및회로부재의제조방법
JP3521758B2 (ja) 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
US7247526B1 (en) 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US7049177B1 (en) 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
TW423133B (en) 1999-09-14 2001-02-21 Advanced Semiconductor Eng Manufacturing method of semiconductor chip package
US6420779B1 (en) * 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6333252B1 (en) 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6342730B1 (en) 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6261864B1 (en) 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6548328B1 (en) 2000-01-31 2003-04-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6242284B1 (en) 2000-05-05 2001-06-05 Advanced Semiconductor Engineering, Inc. Method for packaging a semiconductor chip
TW506236B (en) 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
US6400004B1 (en) 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US6545347B2 (en) 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6993594B2 (en) 2001-04-19 2006-01-31 Steven Schneider Method, product, and apparatus for requesting a resource from an identifier having a character image
US20030006055A1 (en) 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
US6664615B1 (en) 2001-11-20 2003-12-16 National Semiconductor Corporation Method and apparatus for lead-frame based grid array IC packaging
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7790500B2 (en) 2002-04-29 2010-09-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
JP4159431B2 (ja) 2002-11-15 2008-10-01 株式会社ルネサステクノロジ 半導体装置の製造方法
US20050247944A1 (en) 2004-05-05 2005-11-10 Haque Ashim S Semiconductor light emitting device with flexible substrate
TWI245392B (en) * 2004-06-29 2005-12-11 Advanced Semiconductor Eng Leadless semiconductor package and method for manufacturing the same
TWI287275B (en) 2005-07-19 2007-09-21 Siliconware Precision Industries Co Ltd Semiconductor package without chip carrier and fabrication method thereof
KR101089449B1 (ko) 2005-08-10 2011-12-07 가부시키가이샤 미츠이하이테크 반도체 장치 및 그 제조 방법
TWI264091B (en) 2005-09-15 2006-10-11 Siliconware Precision Industries Co Ltd Method of manufacturing quad flat non-leaded semiconductor package
US8163604B2 (en) 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7683461B2 (en) 2006-07-21 2010-03-23 Stats Chippac Ltd. Integrated circuit leadless package system
JP4533875B2 (ja) 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
JP2008258411A (ja) 2007-04-05 2008-10-23 Rohm Co Ltd 半導体装置および半導体装置の製造方法
US7807498B2 (en) 2007-07-31 2010-10-05 Seiko Epson Corporation Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication
JP5166985B2 (ja) 2008-06-18 2013-03-21 株式会社日立エレクトリックシステムズ 導電端子装置を備えた回路遮断器
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
CN101442035B (zh) 2008-12-14 2011-03-16 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
JP5195647B2 (ja) 2009-06-01 2013-05-08 セイコーエプソン株式会社 リードフレームの製造方法及び半導体装置の製造方法
US8362598B2 (en) * 2009-08-26 2013-01-29 Amkor Technology Inc Semiconductor device with electromagnetic interference shielding
CN102044510A (zh) 2009-10-13 2011-05-04 日月光半导体制造股份有限公司 芯片封装体
CN101694837B (zh) * 2009-10-17 2012-09-26 天水华天科技股份有限公司 一种双排引脚的四面扁平无引脚封装件及其生产方法
US8115287B2 (en) * 2009-12-10 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with dual row lead-frame having top and bottom terminals and method of manufacture thereof
US8377750B2 (en) 2010-12-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with multiple row leads and method of manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101533825A (zh) * 2008-03-14 2009-09-16 日月光半导体制造股份有限公司 半导体封装结构及其工艺与表面粘着型半导体封装结构
CN102280431A (zh) * 2011-08-01 2011-12-14 日月光半导体制造股份有限公司 具有保护层的半导体封装及其制作方法

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