TWI620279B - 分離式預成形封裝導線架及其製作方法 - Google Patents
分離式預成形封裝導線架及其製作方法 Download PDFInfo
- Publication number
- TWI620279B TWI620279B TW105131719A TW105131719A TWI620279B TW I620279 B TWI620279 B TW I620279B TW 105131719 A TW105131719 A TW 105131719A TW 105131719 A TW105131719 A TW 105131719A TW I620279 B TWI620279 B TW I620279B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- portions
- wafer
- forming
- electrical connection
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000005022 packaging material Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000002313 adhesive film Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 18
- 229920000642 polymer Polymers 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 15
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 12
- 239000011265 semifinished product Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 claims 18
- 238000000465 moulding Methods 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 abstract description 18
- 238000004026 adhesive bonding Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本發明提供一種預成形封裝導線架的製作方法,利用分段式蝕刻及封裝,讓導電基片藉由封裝材料的黏接封裝,而讓形成的分離式預成形封裝導線架的每一個導線架單元可不需藉由支撐架連接各自分離並電性獨立,而可更易於後續封裝、切單的製程使用。
Description
本發明是有關於一種四方扁平無外引腳 (QFN,quad flat no-lead) 導線架及其製作方法,特別是指一種預成形封裝導線架及其製作方法。
參閱圖1,習知四方扁平無外引腳(QFN,quad flat no-lead)導線架結構,大都是先藉由體蝕刻方式,將一選自銅、鐵鎳合金,或銅系合金為材料構成的金屬片蝕刻移除不必要的部分後,而形成一導線架1。該導線架1具有多條縱向及橫向排列且彼此間隔的連接支架11,及多個由任兩相鄰且彼此相交的橫向及縱向排列的連接支架11共同界定出的導線架單元12。每一個該導線架單元12具有一晶片座13,及多條自該連接支架11朝向該晶片座13延伸的引腳14。當要利用前述該導線架1進行晶片封裝時,一般是先將一半導體晶片(圖未示)貼合於該晶片座13的頂面,然後進行打線、封裝後,再沿一預切割線(如圖1所示之假想線)將該等引腳14切割,讓該等引腳14彼此電性獨立進行,而得到單粒封裝晶粒結構。
配合參閱圖2,而另一種QFN封裝方式,則是業界稱為GQFN(grid quad flat no-lead)封裝方式。其是先藉由體蝕刻將一金屬片10蝕刻移除不必要的部分後,於該金屬片10的其中一表面形成一與圖1所示的導線架單元12的結構雷同的線路圖案121,接著先將一半導體晶片15貼合於該晶片座13的頂面,然後進行打線封裝,形成導線16與封裝該晶片15與該等導線16的封裝層17後,再將封裝有該半導體晶片15的金屬片10進行背蝕刻,於該金屬片10反向該半導體晶片15的表面蝕刻形成與該線路圖案121對應的電連接線路圖案122,之後於該電連接線路圖案122的間隙形成一絕緣層18後,再進行切單(dicing),而得到單粒封裝之封裝晶粒。前述GQFN製程因為第一次蝕刻形成的線路圖案121僅在金屬片10表面,因此,該等引腳14可各自獨立,而不需存在如圖1所示之連接支架11連接,故,當以GQFN封裝方式得到的封裝晶片進行切單時,其切割位置(如圖2箭頭所示位置)僅會切割到封裝材料不會切割到金屬材料。然而,此封裝方式因為是先將該半導體晶片15封裝後再進行第二蝕刻,因此,於蝕刻過程中對該半導體晶片15的影響無法預期。
因此,本發明之目的,即在提供一種方便使用並可用於簡化後續封裝切割製程的分離式預成形封裝導線架的製作方法。
於是,本發明分離式預成形封裝導線架製作方法,包含一第一蝕刻步驟、一第一封膠步驟,及一第二蝕刻步驟。
該第一蝕刻步驟是準備一具有彼此相對之一第一表面及一第二表面的導電基片,自該第一表面向下蝕刻移除部分的導電材料形成一第一蝕刻槽,且該蝕刻槽的深度不穿過該第二表面,得到一導線架半成品,該導線架半成品具一導電基部、多個自該導電基部向上的上晶片部,及多個與該等上晶片部成一間隙的引腳部,該等引腳部與上晶片部藉由該第一蝕刻槽彼此分隔,其中,該導電基部的底面即為該第二表面,該等上晶片部反向該導電基部的表面即為用於與一半導體晶片連接的面。
該第一封膠步驟是於該第一蝕刻槽填注一高分子封裝材料,固化後形成一第一成形膠膜,且該第一成形膠膜不覆蓋該等下晶片部及引腳部反向該導電基部的表面。
第二蝕刻步驟是將形成該第一成形膠膜的導線架半成品自該導電基部的第二表面,將該導電基部對應該第一蝕刻槽位置的導電材料蝕刻移除至該第一成形膠膜露出,而形成一第二蝕刻槽及多個分別與該等上晶片部及該等引腳部相對應連接的下晶片部及電連接部,且該等下晶片部及電連接部藉由該第二蝕刻槽彼此分隔。
此外,本發明之另一目的,即在提供一種方便使用並可用於簡化後續封裝切割製程的分離式預成形封裝導線架。
於是,本發明的分離式預成形封裝導線架包含多個導線架單元,及一預成形膠層。
該等導線架單元由導電材料構成,彼此電性隔離不相連接並成陣列間隔排列,每一個導線架單元具有一個晶片座,及多條各自電性獨立的引腳,該晶片座具有一用於與一半導體晶片連接的頂面,該每一條引腳具有一朝向該晶片座的頂面延伸並與該晶片座成一間隙的引腳部且該引腳部的頂面與該晶片座的頂面齊平,及自該每一條引腳部相對遠離該晶片座的一側向下延伸並可用於對外電連接的電連接部。
該預成形膠層位於該等導線架單元間的間隙及該每一個導線架單元的該等引腳部、該等電連接部與該晶片座的間隙,具有一與該等晶片座的頂面相鄰的第一面,及一反向該第一面的第二面,其中,每一個晶片座及每一條引腳部的頂面自該第一面露出,該每一個晶片座反向該頂面的底面及該每一個電連接部反向該引腳部的表面會自該第二面露出,且該等晶片座的頂面與該預成形膠層的第一面及該等引腳部的表面齊平,共同構成一平坦的表面。
本發明之功效在於:利用分段式蝕刻及封裝,讓導電基片於蝕刻過程可藉由封裝材料的黏接封裝,而讓形成的每一個導線架單元可不需藉由習知金屬支撐架的連接,各自分離並電性獨立,而可更易於後續封裝、切單的製程使用。
參閱圖3、4,本發明分離式預成形封裝導線架200的一實施例是可用於進行半導體晶片封裝。該預成形封裝導線架200具有多個導線架單元2,及一預成形膠層3。
該等導線架單元2是由銅、銅系合金或鐵鎳合金等至少一種導電材料構成,彼此電性隔離不相連接並成陣列間隔排列。定義多條沿X方向及Y方向間隔排列的第一、二預切割道301、302,該等第一、二預切割道301、302即分別位於任相鄰的導線架單元2間,也就是說,任兩相鄰並相交的第一、二預切割道301、302會定義出一個導線架單元2。每一個導線架單元2具有一個晶片座21,及多條各自電性獨立自鄰近該等第一、二預切割道301、302的邊緣朝向該晶片座21周緣延伸並與該晶片座21成一間隙的引腳22。
詳細的說,該晶片座21具有一用於與一半導體晶片連接的頂面211,及一反向該頂面211的底面212,每一條引腳22具有一朝向該晶片座21的頂面211延伸並與該晶片座21成一間隙的引腳部221,且該引腳部221的頂面222與該晶片座21的頂面211齊平,及自該引腳部221遠離該晶片座21的一側向下延伸並可用於對外電連接的電連接部223。要說明的是,圖3中是以該每一個導線架單元2包含一個晶片座21為例,然而,實際實施時,該等導線架單元2也可以分別具有多個晶片座21,並不以此數量為限。此外,圖3中是以該等引腳22為自彼此相對的第一預切割道301、朝向該晶片座21延伸,而形成單排引腳為例,然而實際實施時,該等引腳22可以分別自該等第一、二預切割道301、302定義出之範圍內,由任意位置朝向該晶片座21延伸,例如,該等引腳22可如圖5所示由不同位置延伸,而形成多排(圖5以2排為例)引腳。
該預成形膠層3是由環氧樹脂等高分子封裝材料構成,位於該等導線架單元2間的間隙及該每一個導線架單元2的該等引腳部221、該等電連接部223與該晶片座21的間隙。該預成形膠層3具有一與該等晶片座21的頂面211相鄰的第一面31,及一反向該第一面31的第二面32,其中,該每一個晶片座21的頂面211及該每一條引腳部221的頂面222自該第一面31露出,該每一個晶片座21反向該頂面211的底面212及該每一個電連接部223反向該引腳部221的表面會自該第二面32露出,且該等晶片座21的頂面211與該預成形膠層3的該第一面31及該等引腳部221的頂面222齊平,共同構成一平坦的表面。
配合參閱圖6~8,前述該分離式預成形封裝導線架200製作方法,是先進行一第一蝕刻步驟91,將一導電基片100不必要的部分蝕刻移除,得到一導線架半成品。
該導電基片100具有預計用於連接半導體晶片的一第一表面101及與該第一表面101相對的一第二表面102,並於該導電基片100定義多條彼此間隔並以該X方向及Y方向排列的第一、二分隔島103、104,且該等第一、二分隔島103、104即為對應如圖3所示之第一、二預切割道301、302的位置。要說明的是導電基片100可以是由一單層的導電材料,例如銅、銅系合金或鐵鎳合金等構成,也可以是由多層導電材料層疊,例如於銅片上鍍鎳層再鍍鈀層,而形成具有銅/鎳/鈀三層結構,並不需要特別加以限制。於本實施例中,該導電基片100是以單層,且厚度為1.0~1.5mm的銅片為例說明。
該第一蝕刻步驟91是自該導電基片100的該第一表面101向下蝕刻移除對應該等第一、二分隔島101、102位置及其餘不需要的導電材料,形成一不穿過該第二表面102的第一蝕刻槽105,而得到一於該第一表面101具有預定之導電線路圖案的導線架半成品200A。該導線架半成品200A具一導電基部201、多個自該導電基部201向上的上晶片部202及多個與該等上晶片部202成一間隙的引腳部221,且該等引腳部221與該等上晶片部202藉由該第一蝕刻槽105彼此分隔。其中,該導電基部201的底面即為該第二表面102,該等上晶片部202反向該導電基部201的表面即為用於與一半導體晶片連接的面。較佳地,該第一蝕刻槽105的深度,不超過該第一表面101到第二表面102之距離的一半,而為了可更精確的控制該導電線路圖案的蝕刻精度,更佳地,該第一蝕刻槽105的深度為控制在不大於0.5mm。
接著,進行一第一封膠步驟92,將該導線架半成品200A夾設於一模具(圖未示)中,用模注方式於該第一蝕刻槽105填注一選自環氧樹脂等絕緣高分子的高分子封裝材料,並控制讓該高分子封裝材料不會覆蓋該等上晶片部202及引腳部221反向該導電基部201的表面,接著將該成形封裝材料固化,形成一第一成形膠膜106。
然後,進行一第二蝕刻步驟93,將前述形成該第一成形膠膜106的導線架半成品200A自該第二表面102(即該導電基部201的底面)進行蝕刻,將該導電基部201對應該第一蝕刻槽105位置的導電材料蝕刻移除至該第一成形膠膜106露出並同時將對應該等引腳部221及上晶片部203的部分導電材料移除,而形成一第二蝕刻槽107及多個分別與相對應的該等上晶片部202及該等引腳部221連接的下晶片部203及電連接部223,且該等下晶片部203及電連接部223藉由該第二蝕刻槽107彼此分隔。配合參閱圖3,此時,對應該等第一、二預切割道301、302位置的導電材料已均被移除,而每一個對應連接的上晶片部202及下晶片部203共同構成該如圖3所示的該晶片座21;且每一個對應連接的引腳部221及電連接部223共同構成可對外電連接的該引腳22。
最後再進行一第二封膠步驟94,於該第二蝕刻槽107填注一高分子封裝材料形成一第二成形膠膜108,即可得到如圖3所示之分離式預成形封裝導線架200。
詳細地說,該第二封膠步驟94係將前述形成該第二蝕刻溝槽107的該導線架半成品200A夾設於一模具(圖未示)中,用模注方式於該第二蝕刻槽107填注一選自環氧樹脂等絕緣高分子的高分子封裝材料,並控制令該高分子封裝材料不覆蓋該等電連接部223及下晶片部203反向該等引腳部221及上晶片部202的表面,接著將該高分子封裝材料固化,形成該第二成形膠膜108,該第一、二成形膠膜106、108會彼此接合共同構成該預成型膠層3,即可完成該分離式預成形封裝導線架200的製作。要說明的是,該第一、二成形膠膜106、108所選用的高分子封裝材料可為相同或不同,僅需選擇彼此相容性佳的高分子絕緣材料即可,並不需特別加以限制。
此外,要說明的是,也可視實際製程需求而不實施該第二封膠步驟94。當未實施該第二封膠步驟94時,最終形成的該預成形膠層3則會僅具有該第一成形膠膜106。
本發明利用該第一蝕刻步驟91,先將該導電基材100進行淺蝕刻而形成導電線路圖案,因此可更精準的控制蝕刻形成的導電線路圖案(如引腳部221)的精度,而得到品質較佳的導電線路圖案。此外,因為該第一、二蝕刻步驟91、93,已將原對應位在該等第一、二預切割道301、302位置的導電材料完全蝕刻移除,因此,最終製得之該分離式預成形封裝導線架200的每一個導線架單元2彼此均為電性隔離,且於對應該等第一、二預切割道301、302的位置並無導電(金屬)材料,而僅存在高分子封裝材料。
參閱圖9,當後續利用該分離式預成形封裝導線架200進行該半導體晶片W的貼合、打線及封裝後,即可先分別針對選取的該導線架單元2的封裝晶粒進行單獨的電性測試;且最後要沿該等第一、二預切割道301、302進行切單(dicing)時(圖9箭頭為顯示沿該等第一預切割道301進行切單),因僅會切割到高分子材料而不會切割到金屬材料,而可更易於切割並避免切割刀具磨損。
參閱圖10,本發明分離式預成形封裝導線架的一第二實施例,其結構與該第一實施例大致相同,不同處在於該第二實施例在該等晶片座21及該等電連接部223自該第二面32露出之表面,及/或是於該等引腳部221及該等晶片座21自該第一面31露出的部分頂面222、211還會形成一金屬層4。該金屬層4可為單層或多膜層結構,且材料可選自鎳、鈀、銀或金等金屬,可用於提升後續與其它電路板電連接、焊錫或是打線製程的可靠度。圖10中僅顯示該等晶片座21及該等電連接部223自該第二面32露出之表面具有該金屬層4為例作說明。
參閱圖11,該第二實施例的製備方法與該第一實施例大致相同,不同處在於該第二封膠步驟94之後還需進一步進行一金屬層形成步驟95,利用化鍍方式或濺鍍等鍍膜方式,以於在該等晶片座21及該等電連接部223自該第二面32露出之表面,及/或是於該等引腳部221及該等晶片座21自該第一面31露出的部分頂面222、211形成該金屬層4。由於前述該化鍍或濺鍍等製程的相關參數及鍍膜材料的選擇為本技術領域所知悉,故不再多加贅述。
當利用該第二實施例的分離式預成形封裝導線架200進行半導體晶片的封裝時,由於該等引腳22的電連接部223於反向該等晶片座21用於對外電連接的表面已先預鍍該金屬層4,因此,可直接利用該金屬層4與其它電路板(圖未示)進行電連接或焊錫,而更增加使用便利性。
綜上所述,本發明該分離式預成形封裝導線架200利用分段蝕刻及封裝,而讓經由蝕刻形成的每一個導線架單元2可不需藉由習知金屬支撐架(如圖1所示的連接支架11)的連接,各自分離並電性獨立,而可更易於後續封裝、切單的製程。此外,藉由進一步形成金屬層4,還可直接利用該金屬層4與其它電路板進行電連接或焊錫,而更增加使用便利性,故確實可達成本發明之目的。
惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。
200 | 分離式預成形封裝導線架 | 100 | 導電基片 |
2 | 導線架單元 | 101 | 第一表面 |
21 | 晶片座 | 102 | 第二表面 |
211 | 頂面 | 103 | 第一分隔島 |
212 | 底面 | 104 | 第二分隔島 |
22 | 引腳 | 105 | 第一蝕刻槽 |
221 | 引腳部 | 106 | 第一成形膠膜 |
222 | 頂面 | 107 | 第二蝕刻槽 |
223 | 電連接部 | 108 | 第二成形膠膜 |
3 | 預成形膠層 | 200A | 導線架半成品 |
31 | 第一面 | 201 | 導電基部 |
32 | 第二面 | 202 | 上晶片部 |
4 | 金屬層 | 203 | 下晶片部 |
91 | 第一蝕刻步驟 | 301 | 第一預切割道 |
92 | 第一封膠步驟 | 302 | 第二預切割道 |
93 | 第二蝕刻步驟 | W | 半導體晶片 |
94 | 第二封膠步驟 | X、Y | 方向 |
95 | 金屬層形成步驟 |
本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是說明習知QFN導線架結構的示意圖; 圖2是說明習知GQFN的封裝製作流程示意圖; 圖3是說明本發明分離式預成形封裝導線架的一第一實施例的俯視示意圖; 圖4是圖3中4-4割線的剖視圖; 圖5說明該第一實施例的引腳為多排的示意圖; 圖6是說明該第一實施例的文字步驟流程圖; 圖7是說明該步驟91的流程示意圖; 圖8是以圖7中8-8割線之剖視結構說明該步驟92-94的流程示意圖; 圖9是說明利用該第一實施例的分離式預成形封裝導線架進行半導體晶片封裝後,切單前的剖視結構示意圖; 圖10說明該第二實施例製得的分離式預成形封裝導線架的剖視示意圖;及 圖11是說明該第二實施例的文字步驟流程圖。
Claims (6)
- 一種分離式預成形封裝導線架製作方法,包含:一第一蝕刻步驟,準備一具有彼此相對之一第一表面及一第二表面的導電基片,自該第一表面向下蝕刻移除部分的導電材料形成一第一蝕刻槽,且該蝕刻槽的深度不穿過該第二表面,得到一導線架半成品,該導線架半成品具一導電基部、多個自該導電基部向上的上晶片部,及多個與該等上晶片部成一間隙的引腳部,該等引腳部與上晶片部藉由該第一蝕刻槽彼此分隔,其中,該導電基部的底面即為該第二表面,該等上晶片部反向該導電基部的表面即為用於與一半導體晶片連接的面;一第一封膠步驟,於該第一蝕刻槽填注一高分子封裝材料,固化後形成一第一成形膠膜,且該第一成形膠膜不覆蓋該等上晶片部及引腳部反向該導電基部的表面;及一第二蝕刻步驟,將形成該第一成形膠膜的導線架半成品自該導電基部的第二表面進行蝕刻,將該導電基部對應該第一蝕刻槽位置的導電材料蝕刻移除至該第一成形膠膜露出並將對應該等引腳部及上晶片部的部分導電材料移除,而形成一第二蝕刻槽及多個分別與該等上晶片部及該等引腳部相對應連接的下晶片部及電連接部,且該等下晶片部及電連接部藉由該第二蝕刻槽彼此分隔。
- 如請求項1所述的分離式預成形封裝導線架製作方法,還包含一第二封膠步驟,於該第二蝕刻槽填注一高分子封裝材料形成一第二成形膠膜,且該第二成形膠膜不覆蓋該等 電連接部及下晶片部反向該等上晶片部的表面。
- 如請求項1所述的分離式預成形封裝導線架製作方法,還包含一金屬層形成步驟,於該等電連接部及該等下晶片部外露於該第二成形膠膜的表面形成一金屬層。
- 如請求項1所述的分離式預成形封裝導線架製作方法,其中,該導電基片為由至少一層導電材料構成,該第一封膠步驟形成的該第一成形膠膜的表面與該等上晶片部及該等引腳部反向該導電基部的表面齊平,且該第一、二成形膠膜可為相同或不同的高分子封裝材料。
- 一種分離式預成形封裝導線架,包含:多個導線架單元,由導電材料構成,彼此電性隔離不相連接並成陣列間隔排列,每一個導線架單元具有至少一個晶片座,及多條各自電性獨立的引腳,該晶片座具有一用於與一半導體晶片連接的頂面,該每一條引腳具有一朝向該晶片座的頂面延伸並與該晶片座成一間隙的引腳部且該引腳部的頂面與該晶片座的頂面齊平,及自該每一條引腳部相對遠離該晶片座的一側向下延伸並可用於對外電連接的電連接部;及一預成形膠層,位於該等導線架單元間的間隙及該每一個導線架單元的該等引腳部、該等電連接部與該晶片座的間隙,該預成形膠層具有一與該等晶片座的頂面相鄰的第一面,及一反向該第一面的第二面,一自該第一面朝向該第二面形成的第一成型膠膜,及一自該第二面朝向第一面形成的第二成型膠膜,且該第一、二成型膠膜的材料可 為相同或不同,其中,每一個晶片座及每一條引腳部的頂面自該第一面露出,該每一個晶片座反向該頂面的底面及該每一個電連接部反向該引腳部的表面會自該第二面露出,且該等晶片座的頂面與該預成形膠層的第一面及該等引腳部的表面齊平,共同構成一平坦的表面。
- 如請求項5所述的分離式預成形封裝導線架,還包含一金屬層,該金屬層形成於該等晶片座及該等電連部自該第二面外露的表面。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105131719A TWI620279B (zh) | 2016-09-30 | 2016-09-30 | 分離式預成形封裝導線架及其製作方法 |
US15/482,039 US9984980B2 (en) | 2016-09-30 | 2017-04-07 | Molded lead frame device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105131719A TWI620279B (zh) | 2016-09-30 | 2016-09-30 | 分離式預成形封裝導線架及其製作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201813011A TW201813011A (zh) | 2018-04-01 |
TWI620279B true TWI620279B (zh) | 2018-04-01 |
Family
ID=61758854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105131719A TWI620279B (zh) | 2016-09-30 | 2016-09-30 | 分離式預成形封裝導線架及其製作方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9984980B2 (zh) |
TW (1) | TWI620279B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWM624922U (zh) * | 2021-12-13 | 2022-03-21 | 長華科技股份有限公司 | 具有切割對位記號的導線架元件 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201236228A (en) * | 2011-02-18 | 2012-09-01 | Bridge Semiconductor Corp | Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts |
TWM534433U (en) * | 2016-09-30 | 2016-12-21 | Chang Wah Technology Co Ltd | Separated-type pre-formed packaging lead frame |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6050975B2 (ja) * | 2012-03-27 | 2016-12-21 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
-
2016
- 2016-09-30 TW TW105131719A patent/TWI620279B/zh active
-
2017
- 2017-04-07 US US15/482,039 patent/US9984980B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201236228A (en) * | 2011-02-18 | 2012-09-01 | Bridge Semiconductor Corp | Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts |
TWM534433U (en) * | 2016-09-30 | 2016-12-21 | Chang Wah Technology Co Ltd | Separated-type pre-formed packaging lead frame |
Also Published As
Publication number | Publication date |
---|---|
US9984980B2 (en) | 2018-05-29 |
TW201813011A (zh) | 2018-04-01 |
US20180096953A1 (en) | 2018-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7228063B2 (ja) | 半導体装置 | |
CN102931161B (zh) | 半导体封装件及其制造方法 | |
JP4215306B2 (ja) | 半導体のパッケージおよびその製造方法 | |
US8115288B2 (en) | Lead frame for semiconductor device | |
JP5232394B2 (ja) | 半導体装置の製造方法 | |
KR20110015047A (ko) | 포일계 반도체 패키지 | |
JP2014220439A (ja) | 半導体装置の製造方法および半導体装置 | |
US8643158B2 (en) | Semiconductor package and lead frame therefor | |
US9620388B2 (en) | Integrated circuit package fabrication with die attach paddle having middle channels | |
USRE43818E1 (en) | Fabrication of an integrated circuit package | |
TWM531057U (zh) | 預成形封裝導線架 | |
TWM523189U (zh) | 導線架預成形體及導線架封裝結構 | |
TWI620279B (zh) | 分離式預成形封裝導線架及其製作方法 | |
US9202778B2 (en) | Integrated circuit package with die attach paddle having at least one recessed portion | |
TWM551755U (zh) | 泛用型導線架 | |
CN108198790A (zh) | 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺 | |
CN101814461A (zh) | 封装基板结构与芯片封装结构及其制作方法 | |
CN107305851A (zh) | 半导体器件的制造方法以及半导体器件 | |
US8829685B2 (en) | Circuit device having funnel shaped lead and method for manufacturing the same | |
TWM588888U (zh) | 高密著性預成型基板 | |
TW201308548A (zh) | 小基板多晶片記憶體封裝構造 | |
CN209544331U (zh) | 预成形填锡沟槽导线架及其封装元件 | |
CN206584920U (zh) | 分离式预成形封装导线架 | |
TWM578020U (zh) | 預成形填錫溝槽導線架及其封裝元件 | |
TWM589900U (zh) | 具有外凸微型引腳的半導體封裝元件 |