TWM551755U - 泛用型導線架 - Google Patents

泛用型導線架 Download PDF

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Publication number
TWM551755U
TWM551755U TW106208888U TW106208888U TWM551755U TW M551755 U TWM551755 U TW M551755U TW 106208888 U TW106208888 U TW 106208888U TW 106208888 U TW106208888 U TW 106208888U TW M551755 U TWM551755 U TW M551755U
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Taiwan
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lead frame
molding
wafer
forming
pins
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TW106208888U
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English (en)
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Chia-Neng Huang
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Chang Wah Technology Co Ltd
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Priority to TW106208888U priority Critical patent/TWM551755U/zh
Priority to US15/805,086 priority patent/US10068837B1/en
Priority to KR2020170005773U priority patent/KR200489837Y1/ko
Publication of TWM551755U publication Critical patent/TWM551755U/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49534Multi-layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49558Insulating layers on lead frames, e.g. bridging members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry

Description

泛用型導線架
本新型是有關於一種四方扁平無外引腳(QFN,quad flat no-lead)導線架,特別是指一種預成形的泛用型導線架。
參閱圖1,圖1是一般常見的QFN導線架,包括一框座11、一晶片座12、一自該晶片座12的四個角落延伸並與該框座11連接的支撐條13,及多條自該框座11朝向該晶片座12延伸的引腳14,其中該框座11與該晶片座12成一間隙間隔,且該等引腳14也與該晶片座12不相接觸。參閱圖2,圖2是沿圖1的2-2割面線說明。當利用圖1所示的該QFN導線架進行晶片封裝時,則可將一晶片100設置於該晶片座12上,並藉由導線15與該等引腳14電連接,最後再利用一高分子封裝材料(molding compound)形成一覆蓋該等晶片100及該導線架裸露之表面的封裝層16,而得到如圖2所示的封裝結構。
然而,當使用該QFN導線架進行該晶片100封裝時,因需同時考量封裝製程的操作性及高分子封裝材料(封裝層16)與金 屬(晶片座12)之間因為性質不相容密著性不佳,所導致的封裝元件可靠度(reliability)問題,因此,一般會控制令待封裝之晶片100的面積與該晶片座12的表面積比值約在0.6~0.8。前述方式雖然可利用控制該晶片座12的面積而減少異質接面,然而,卻也造成當需要封裝不同尺寸的晶片100,就需重新製作具不同尺寸之晶片座12的QFN導線架,使其可符合前述晶片100與該晶片座12的表面積比值約控制在0.6~0.8的要求。
因此,本新型之目的,即在提供一種可以單一規格適用不同尺寸之晶片封裝的泛用型導線架。
於是,本新型泛用型導線架,包括多條彼此縱橫間隔交錯的外框條,及多個經由該等外框條所定義出,彼此間隔並成陣列排列的導線架單元,每一個導線架單元包含一晶片設置區、多條引腳,及一成形膠層。
該晶片設置區具有一底部、一由該底部的部份表面向上延伸的座部,及多數由該底部向上延伸的柱部,該等柱部彼此間隔並位於該座部的外圍,該底部、座部及該等柱部是由相同的金屬材料構成,且該座部及該等柱部分別具有一與該底部反向的頂面。
該等引腳由與該座部相同的金屬材料構成,該等引腳 自該等外框條朝向該晶片設置區延伸,彼此間隔設置且與該晶片設置區成一間隙。
該成形膠層由絕緣高分子材料構成,具有一第一成形膠部、一第二成形膠部,及一第三成形膠部,該第一成形膠部填置於該晶片設置區的該等柱部的間隙,該第二成形膠部位於該於該晶片設置區,並會環圍該等柱部及該第一成形膠部,該第三成形膠部填製於該等引腳及該等引腳與該晶設片設置區之間的間隙。
其中,該第一、二成形膠部分別具有與該底部反向的一第一表面及一第二表面,該座部的頂面及該等柱部的頂面與該第一成形膠部的該第一表面共同構成一連續平坦的表面,該第二成形膠部的該第二表面與該第一成形膠部的該第一表面不等高,且該座部、該等柱部的頂面及該第一、二表面會裸露於外界環境。
本新型之功效在於:利用由座部與柱部配合形成可用於設置晶片的晶片設置區,因此可利用該等柱部將可承載晶片的面積延伸而可用於承載不同尺寸的晶片並降低界面密著性問題,且還利用該第二成形膠部防止封裝焊錫溢流的問題。
21‧‧‧第一外框條
22‧‧‧第二外框條
3‧‧‧導線架單元
31‧‧‧晶片設置區
311‧‧‧底部
312‧‧‧座部
3121‧‧‧頂面
313‧‧‧柱部
3131‧‧‧頂面
314‧‧‧接地部
315‧‧‧支撐部
32‧‧‧引腳
321‧‧‧頂面
33‧‧‧成形膠層
331‧‧‧第一成形膠部
3311‧‧‧第一表面
332‧‧‧第二成形膠部
3321‧‧‧第二表面
333‧‧‧第三成形膠部
3331‧‧‧第三表面
本新型之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是說明習知QFN導線架結構的示意圖;圖2是說明利用圖1之導線架進行晶片封裝的封裝結構剖視示意圖;圖3是說明本新型泛用型導線架的一第一實施例的俯視示意圖;圖4是圖3中沿4-4割面線的剖視示意圖;圖5是說明該第一實施例中,第二成形膠部的另一結構態樣的剖視示意圖;及圖6說明說明本新型泛用型導線架的一第二實施例的剖視示意圖。
參閱圖3、4,本新型泛用型導線架是可用於進行半導體晶片封裝而形成一封裝結構。該泛用型導線架的一第一實施例包含多條由銅、銅系合金或鐵鎳合金的金屬材料構成,呈縱向及橫向間隔排列且彼此相交的第一外框條21、第二外框條22,及多個經由該等第一外框條21及第二外框條22所定義出,彼此間隔並成陣列排列的導線架單元3,圖3僅顯示其中一個導線架單元3。
其中,每一個導線架單元3包含一晶片設置區31、多條引腳32,及一成形膠層33。
該晶片設置區31,具有一底部311、一由該底部311的 部份表面向上延伸的座部312、多數由該底部311向上延伸的柱部313、多條自該底部311的邊緣向上延伸,並與該等柱部313成一間隙的接地部314,及自該晶片設置區31的四個角落延伸而與相應的該等第一、二外框條21、22連接的支撐部315。
其中,該等該座部312及該等柱部313分別具有一與該底部311反向的頂面3121、3131,且該第一、二外框條21、22、底部311、座部312及該等柱部313是由相同的金屬材料構成。該等接地部314概呈長條型,分別具有一對外裸露,並位於該等引腳32與該等柱部313的頂面3131之間的表面, 該等引腳32由與該座部312相同的金屬材料構成,自該等第一、二外框條21、22的其中至少一朝向該晶片設置區31延伸。其中,該等引腳32彼此間隔,與該晶片設置區31呈一間隙並分別具有一與該座部312的頂面3121同向且裸露於外界的頂面321。圖3中是以該等引腳32成雙排排列為例,然而,要說明的是,該等引腳32也可以是單排排列或是多排排列,並不以此為限。
該成形膠層33由絕緣高分子材料,如環氧樹脂等構成,具有一第一成形膠部331、一第二成形膠部332,及一第三成形膠部333,且該第一成形膠部331、第二成形膠部332及第三成形膠部333分別具有與該底部311反向的一第一表面3311、一第二表面3321,及一第三表面3331。
詳細地說,該第一成形膠部331填置於該晶片設置區31的該等柱部313及該等柱部313與座部312之間的間隙;該第二成形膠部332位於該於該晶片設置區31外圍,環圍該等柱部313及該第一成形膠部331,並介於該等接地部314與該等柱部313之間;該第三成形膠層333填置於該等引腳32及該等引腳32與該晶設片設置區31之間的間隙。其中,該座部312的頂面3121及該等柱部313的頂面3131與該第一成形膠部331的該第一表面3311共同構成一連續平坦的表面,該第二成形膠部332的該第二表面3321會高於該第一成形膠部331的該第一表面3311,且該座部312、該等柱部313、該等引腳32的頂面321,及該第一、二、三表面3311、3321、3331會裸露於外界環境,而可分別用於後續電連接。
本新型泛用型導線架的該第一實施例,利用讓該座部312及柱部313共同配成一可用於設置晶片(圖未示)的晶片設置區31。因此,可將該座部312的尺寸設計成封裝最小晶片所需的面積,再利用該等柱部313將可承載晶片的面積延伸,因此,當待封裝的晶片的面積超過該座部312時,可進一步藉由該等柱部313作為晶片的承載區域,而可用於承載不同尺寸的晶片;而因為該等柱部313之間填置的高分子材料,與後續用於封裝的封裝材料性質相同且相容性高,因此,可有效改善封裝後界面接著性問題,而提升封裝後元件的可靠度。再者,本新型還進一步利用讓該第二成形膠 部332的高度高於該第一成形膠部331,因此,當利用本新型該第一實施例進行晶片封裝時,還可防止用於連接晶片與座部312的焊錫溢流至引腳32,而造成元件失效的問題。
此外,參閱圖5,前述該第二成形膠部332,除了如圖3所示可以是高於該第一成形膠部331,而形成類似擋牆的形狀以防止焊錫溢流之外,也可以是如圖5所示,令該第二成形膠部332的表面3321低於第一成形膠部331的表面3311,而形成一類似溝槽的形狀,也可用於容納溢出之焊錫,而同樣具有防止溢流之目的。
前述該泛用型導線架的第一實施例的製作方法是先提供一由可導電的材料,例如銅、銅系合金或鐵鎳合金等材料構成的基片。於該基片定義多條彼此間隔並呈縱向及橫向排列的第一、二分隔島。
接著進行蝕刻,將該基片不必要的部分蝕刻移除,令該基片形成一半成品,該半成品包括多條如圖3所示,對應該等第一、二分隔島位置的第一、二外框條21、22,及多個由該等第一、二外框條21、22界定出之導線架半成品單元,且該每一個導線架半成品單元具有如圖3所示的該晶片設置區31及引腳32。
接著,再配合參閱圖3、4,將該半成品夾設於一具有與該成形膠層33的形狀相對應的模具中,用模注方式灌入一成形封裝材料,其中,該成形封裝材料為選自環氧樹脂等絕緣高分子材 料,將該成形封裝材料填滿該等導線架單元3的該等晶片設置區31及該等引腳32與該等晶片設置區31之間的所有間隙,且控制讓該成形封裝材料如圖4所示,不會覆蓋該等座部312及該等引腳32的頂面3121、321及與該等頂面3121、321反向的底面,接著再將該成形封裝材料固化形成該成形膠層33,即可得到該如圖3所示的泛用型導線架。
參閱圖6,本實用新型泛用型導線架的一第二實施例與該第一實施例的結構大致相同,其與第一實施例的不同處在於該等第一、二外框條21、22是高分子材料,與該成形膠層33為一體成形,且該晶片設置區31不需該等支撐部315與該等第一、二外框條21、22連接。
該第二實施例因為該等第一、二外框條21、22為高分子材料,因此,當利用該第二實施例所示的泛用型導線架進行晶片封裝後,而沿該第一、二外框條21、22位置進行切割時,因為該等第一、二外框條21、22為高分子材料,所以還可進一步減少切割刀具的損耗。
前述該第二實施例可利用二次蝕刻製程控制而形成,該二次蝕刻方法的細部製程說明已見於中華民國新型專利M523189,於此不再多加說明。
綜上所述,本新型該泛用型導線架利用讓該座部312 及柱部313共同配成一可用於設置晶片的晶片設置區31,以及該第二成形膠部332的結構設計。因此,除了可用於承載不同尺寸的晶片、改善封裝後界面接著性問題而提升封裝可靠度之外,還可防止用於連接晶片與該座部312的焊錫溢流至引腳32,而可有效提升封裝後元件的可靠度,故確實可達成本新型之目的。
惟以上所述者,僅為本新型之實施例而已,當不能以此限定本新型實施之範圍,凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本新型專利涵蓋之範圍內。
21‧‧‧第一外框條
31‧‧‧晶片設置區
311‧‧‧底部
312‧‧‧座部
3121‧‧‧頂面
313‧‧‧柱部
3131‧‧‧頂面
321‧‧‧頂面
33‧‧‧成形膠層
331‧‧‧第一成形膠部
3311‧‧‧第一表面
332‧‧‧第二成形膠部
3321‧‧‧第二表面
333‧‧‧第三成形膠部
314‧‧‧接地部
32‧‧‧引腳
3331‧‧‧第三表面

Claims (7)

  1. 一種泛用型導線架,包括多條彼此縱橫間隔交錯的外框條,及多個經由該等外框條所定義出,彼此間隔並成陣列排列的導線架單元,每一個導線架單元包含:一晶片設置區,具有一底部、一由該底部的部份表面向上延伸的座部,及多數由該底部向上延伸的柱部,該等柱部彼此間隔並位於該座部的外圍,該底部、座部及該等柱部是由相同的金屬材料構成,且該座部及該等柱部分別具有一與該底部反向的頂面;多條引腳,由與該座部相同的金屬材料構成,該等引腳自該等外框條朝向該晶片設置區延伸,彼此間隔設置且與該晶片設置區成一間隙;及一成形膠層,由絕緣高分子材料構成,具有一第一成形膠部、一第二成形膠部,及一第三成形膠部,該第一成形膠部填置於該晶片設置區的該等柱部的間隙,該第二成形膠部位於該於該晶片設置區,並會環圍該等柱部及該第一成形膠部,該第三成形膠部填置於該等引腳及該等引腳與該晶設片設置區之間的間隙,其中,該第一、二成形膠部分別具有與該底部反向的一第一表面及一第二表面,該座部的頂面及該等柱部的頂面與該第一成形膠部的該第一表面共同構成一連續平坦的表面,該第二成形膠部的該第二表面與該第一成形膠部的該第一表面不等高,且該座部、該等柱部的頂面及該第一、二表面會裸露於外界環境。
  2. 如請求項1所述的泛用型導線架,其中,該第一成形膠部的該第一表面高於該第二成形膠部的該第二表面。
  3. 如請求項1所述的泛用型導線架,其中,該第一成形膠部的該第一表面低於該第二成形膠部的該第二表面。
  4. 如請求項1所述的泛用型導線架,其中,該第三成形膠部具有一第三表面,且該第三表面與該第一表面齊平。
  5. 如請求項1所述的泛用型導線架,還包含至少一位於該晶片設置區與該等引腳之間的接地部,該至少一接地部自該底部向上延伸,具有一對外裸露,並位於該第二、三表面之間的第四表面。
  6. 如請求項1所述的泛用型導線架,其中,該等外框條是由與該等座部相同的金屬材料構成,且與該等導線架單元的底部連接。
  7. 如請求項1所述的泛用型導線架,其中,該等外框條是由高分子材料構成,且與該成形膠層一體連接。
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