TWM531057U - 預成形封裝導線架 - Google Patents

預成形封裝導線架 Download PDF

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TWM531057U
TWM531057U TW105212025U TW105212025U TWM531057U TW M531057 U TWM531057 U TW M531057U TW 105212025 U TW105212025 U TW 105212025U TW 105212025 U TW105212025 U TW 105212025U TW M531057 U TWM531057 U TW M531057U
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Taiwan
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lead frame
package
wafer holder
pins
spacers
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TW105212025U
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Chia-Neng Huang
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Chang Wah Technology Co Ltd
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Priority to TW105212025U priority Critical patent/TWM531057U/zh
Publication of TWM531057U publication Critical patent/TWM531057U/zh
Priority to US15/422,257 priority patent/US9799613B1/en
Priority to MYPI2017702291A priority patent/MY180051A/en
Priority to KR2020170003970U priority patent/KR200489288Y1/ko

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Lead Frames For Integrated Circuits (AREA)

Description

預成形封裝導線架
本新型是有關於一種四方扁平無外引腳 (QFN,quad flat no-lead) 導線架,特別是指一種預成形封裝導線架。
參閱圖1,習知四方扁平無外引腳(QFN,quad flat no-lead)導線架結構,大都是先藉由體蝕刻方式,將一選自銅、鐵鎳合金,或銅系合金為材料構成的金屬片蝕刻移除不必要的部分後,而形成一導線架1。該導線架1具有多條縱向及橫向排列且彼此間隔的連接支架11,及多個由任兩相鄰且彼此相交的橫向及縱向排列的連接支架11共同界定出的導線架單元12。每一個該導線架單元12具有一晶片座13,及多條自該連接支架11朝向該晶片座13延伸的引腳14。
當要利用前述該導線架1進行晶片封裝時,以其中一個導線架單元12說明,一般是先將一晶片15貼合於該晶片座13的頂面131,然後進行打線,得到連接該晶片15與該等引腳14的導線16。然後利用封裝材料(molding compound)形成一封裝該晶片15的封裝層17,即可得到如圖2之封裝結構。然後沿切割線(如圖1所示之虛線,或圖2所示之假想線位置)切單(dicing),即可得到單粒封裝之封裝晶粒,之後再將該單粒封裝之封裝晶粒與一封裝基板(如電路板)電連接,而得到所需之電子元件。
然而,前述晶片封裝過程,因為目前常用於打線製程的金屬為銀,而銀與銅的密著並不好,因此,為了提升打線的可靠度,於打線前會先於該等引腳14靠近晶片座13的局部區域(如圖1中該等引腳14的假想線所示區域)進行後電鍍,而電鍍一層與銀導線密著性佳的貴金屬材料(如銀或鎳鈀合金)。然而,局部電鍍需再增加微影製程而增加了製程的繁雜度。此外,於後電鍍過程中,還會於該導線架1的底面(即反向該晶片15的表面)貼上一層防鍍層,因此,在後電鍍完畢移除該防鍍層後,為了避免該防鍍層在該導線架1的底面殘膠,而影響後續封裝的可靠度,會再對該導線架1的底面進行刮膠,且為了避免因括膠過程造成的刮痕對該導線架1的電性影響,因此,之後還會於該導線架1的底面再形成一層厚錫層,以減少影響並用於後續與電路板的接合。此外,因為用於晶片封裝的該封裝層17為高分子材料,與該等引腳14(銅)的密著性並不佳,因此,切割後之封裝晶粒在該封裝層17與該等引腳14的接合處也容易有剝離的問題,而又再影響封裝晶片的可靠度。
因此,本新型之目的,即在提供一種方便使用,且可提升封裝性能的預成形封裝導線架。
於是,本新型預成形封裝導線架,包含多條由金屬材料構成,呈縱向及橫向間隔排列且彼此相交的第一、二分隔架及多個成陣列排列的導線架封裝單元。每一個導線架封裝單元是由任兩相鄰且彼此相交的該等第一、二分隔架共同定義出,且該每一個導線架單元包含至少一晶片座、多條引腳,及一成形膠層。
該至少一晶片座由與該等第一、二分隔架相同的金屬材料構成。
該等引腳由與該晶片座相同的金屬材料構成,自該等第一分隔架或第二分隔架的至少其中任一,朝向該至少一晶片座延伸並與該至少一晶片座成一間距,且該等引腳於遠離該至少一晶片座的一側,具有自該等引腳的頂面向下形成的凹槽。
該成形膠層由絕緣高分子材料構成,填置於該至少一晶片座與該等第一、二分隔架之間的間隙及該等引腳的凹槽。
本新型之功效在於:利用將導線架封裝單元的引腳於遠離晶片座位置形成填滿成形封裝材料的凹槽,因此,可讓該預成形封裝導線架的引腳與後續用於封裝的封裝材料於最外側接面為同質材料,而可提升封裝元件的性能及可靠度。
參閱圖3、4,本新型預成形封裝導線架200是可用於進行半導體晶片封裝。該預成形封裝導線架200的一實施例包含多條由銅、銅系合金或鐵鎳合金的金屬材料構成,呈縱向及橫向間隔排列且彼此相交的第一、二分隔架21、22,及多個成陣列排列的導線架封裝單元3,且每一個導線架封裝單元3是由任兩相鄰且彼此相交的該等第一、二分隔架21、22共同定義出。
該每一個導線架封裝單元3包含一晶片座31、多條引腳32,及一成形膠層33。
該晶片座31由與該等第一、二分隔架21、22相同的金屬材料構成,具有一頂面311及一與該頂面311相對的底面312。要說明的是,圖3中是以該每一個導線架封裝單元3包含一個晶片座31為例,然而,實際實施時,該等導線架封裝單元3也可以分別具有多個晶片座31,並不以此數量為限。
該等引腳32由與該晶片座31相同的金屬材料構成,自該等第一分隔架21或第二分隔架22的至少其中任一朝向該晶片座31延伸並與該晶片座31呈一間距,且於遠離該晶片座31的一側,具有自該等引腳32的頂面向下形成的凹槽321。於圖3中是以該等引腳32自彼此相對的兩個第一分隔架21朝向該晶片座31延伸並與該晶片座31呈一間距,且每一條引腳32於遠離該晶片座31的一側,具有一自該引腳32的頂面向下形成的凹槽321為例作說明。且定義一用於後續切割該每一個導線架封裝單元3的預切割道(如圖3中虛線所示),該等引腳32的凹槽321會位於該預切割道上。
該成形膠層33由絕緣高分子材料,如環氧樹脂等構成,填置於該晶片座31與該等第一、二分隔架21、22之間的間隙及該等引腳32的凹槽321。
配合參閱圖5,前述該預成形封裝導線架200的製作方法,是提供一由可導電的材料,例如銅、銅系合金或鐵鎳合金等材料構成的基片100。於該基片100定義多條彼此間隔並呈縱向及橫向排列的第一、二分隔島101、102。
接著進行蝕刻,將該基片100不必要的部分蝕刻移除,令該基片100形成一個導線架201A。其中,該導線架201A包括多條縱向及橫向排列且彼此間隔的第一、二分隔架21、22,及多個導線架單元3A。
詳細的說,該等第一、二分隔架21、22即位於該等第一、二分隔島101、102所定義之位置。任兩相鄰且彼此相交的第一、二分隔架21、22共同界定出一個導線架單元3A,每一個導線架單元3A包含該晶片座31及該等引腳32,而該等引腳32的凹槽321則是於蝕刻過程中,利用蝕刻製程的控制,進一步自該等引腳32於遠離該晶片座31的一側自該等引腳32的頂面向下進行半蝕刻而形成。
此外,要說明的是,經蝕刻後形成的該等第一、二分隔架21、22的形狀及細部結構為本技術領域者所熟知並視實際需求及設計而有所不同,且非為本新型之結構重點,因此,於圖式中僅是一簡單示意圖,實際結構並不以此為限。
接著,將該導線架201A夾設於一模具(圖未示)中,用模注方式灌入一成形封裝材料,其中,該成形封裝材料為選自環氧樹脂等絕緣高分子材料,將該成形封裝材料填滿該等第一、二分隔架21、22與該等晶片座31之間的空隙及該等引腳32的凹槽321內,且控制讓該成形封裝材料不會覆蓋該等晶片座31及該等引腳31的頂面及底面,接著將該成形封裝材料固化形成該成形膠層33,即可得到該如圖3所示的預成形封裝導線架200。
由於經預封裝後得到的該預成形封裝導線架200,於該等引腳32遠離該晶片座31的一側均具有一表面為非金屬的樹脂區域(即該等引腳32的凹槽321所在區域),因此,配合參閱圖6,當後續利用該預成形封裝導線架200進行晶片34的貼合、打線及封裝時,圖6是以圖3所示之預成形封裝導線架200進行封裝後之剖視結構示意圖。由於封裝層35與該等引腳32的接觸面(即凹槽321所在區域的表面)均為高分子,密著性佳,因此,當封裝完成,沿著該預切割線(如圖6中假想線所示位置)進行切割時,切割後之封裝晶粒於最外側的接面均為同質(高分子)材料,所以不會有習知(如圖2所示)因為封裝材料與銅(導線架/引腳)的密著性不佳,導致封裝後的該封裝層17與該等引腳14的接合處剝離的問題。
此外,本新型該預成形封裝導線架200因為己先利用成形封裝材料(絕緣高分子)將該導線架201A不需對外電連接的部分封裝覆蓋,故,當後續考量打線製程之可靠度,而欲進一步進行後電鍍,例如,要於該等引腳32鄰近該晶片座31的區域進行不同金屬材料(如鍍銀、鎳鈀合金)的後電鍍而形成一金屬層(圖未示),該成形膠層33即可作為電鍍的遮罩,因此,可不需再使用其它的遮罩或貼保護膠帶,直接利用該預成形封裝導線架200進行後電鍍,即可讓該金屬層形成於該晶片座31及該等引腳32未被該成形膠層33遮覆的表面。且因為不需貼保護膠帶,故也不會有因使用保護膠帶而需除膠及因除膠造成的導線架刮痕問題。
參閱圖7、8,圖8是圖7中8-8割線的剖視圖。本新型該預成形封裝導線架200的該導線架封裝單元3,還可包含多個分別連接該晶片座31與相鄰的該第一分隔架21或該第二分隔架22的支撐段36,且該等支撐段36於遠離該晶片座31的一側,也各具有一自該支撐段36的頂面向下形成的凹槽361。此時,該成形膠層33除了填置於該晶片座31與該等第一、二分隔架21、22之間的間隙及該等引腳32的凹槽321之外,還會進一步填置於該等支撐段36的凹槽361內。圖7是以該導線架封裝單元3具有二個位於該晶片座31得相對兩側,分別連接該晶片座31及與該晶片座31相鄰之第二分隔架22的支撐段36,且該等支撐段36的凹槽361也位於該預切割道(圖7虛線所示)上為例作說明。利用同時於該等支撐段36上形成位於該預切割道上的凹槽361,不僅可利用該等支撐段36支撐固定該晶片座31,且藉由填置於該等凹槽361內之成形膠層33也可改善與後續封裝材料之間的密著性,而不影響封裝後製得之封裝晶粒的性能。
前述該等支撐段36的凹槽361與該等引腳32的凹槽321是於同一個蝕刻製程,並藉由製程控制而進一步於該等支撐段36及該等引腳32進行半蝕刻而得。由於蝕刻及半蝕刻使用的相關材料及製程為本技術領域者習知,故不再多加贅述。
此外,再參閱圖9、10,圖10是圖9中10-10割線的剖視圖。該預成形封裝導線架200的該晶片座31也可以經由蝕刻,而具有一底部313、多個自該底部313向上延伸且彼此間隔的連接部314。其中,該底部313遠離該等連接部314的表面即為該晶片座31的底面312,而該等連接部314的頂面即為該晶片座31的頂面311,且該成形膠層33還填置於該等連接部314之間的間隙且不覆蓋該等連接部314的頂面311。利用將該晶片座31進行蝕刻,留下作為散熱的全銅接觸點(連接部314),而將蝕刻移除部分均事先用成形封裝材料充填,所以,當要利用該預成形導線架封裝單元200進行後電鍍(例如鍍銀)時,因為已預先利用成形封裝材料將該晶片座31不需電鍍的部分封裝,所以該晶片座31不會有大面積鍍銀或影響可靠度的問題。
同樣地,前述該等連接部314也是於形成該導線架201A的蝕刻製程中一併蝕刻形成。由於蝕刻及半蝕刻使用的相關材料及製程為本技術領域者習知,故不再多加贅述
綜上所述,本新型該預成形封裝導線架200利用該導線架201A的結構設計,讓該等引腳32及支撐部36在對應該預切割道的區域形成凹槽321、361,因此,該導線架201A以成形封裝材料進行預封裝時,可同時將成形封裝材料填置於該等引腳32及支撐部36的凹槽321、361內,而將該等引腳32及支撐部36的外側表面由金屬表面轉變成高分子表面,因此可避免後續晶片封裝時,封裝材料與該等引腳32及支撐部36之間因為異質材料接合,而有密著性不佳剝離的問題。此外,該晶片座31的部分也可藉由半蝕刻,移除多數的金屬,僅留下用於散熱的全銅接觸點(連接部314),並配合成形封裝材料將該導線架201A不需要電鍍的部分進行預封裝,因此,可直接將該預成形封裝導線架200進行電鍍,不需使用遮罩或貼保護膠帶,也不會有大面積鍍銀或影響可靠度的問題,故確實可達成本新型之目的。
惟以上所述者,僅為本新型之實施例而已,當不能以此限定本新型實施之範圍,凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本新型專利涵蓋之範圍內。
200‧‧‧預成形封裝導線架
33‧‧‧成形膠層
21‧‧‧第一分隔架
34‧‧‧晶片
22‧‧‧第二分隔架
35‧‧‧封裝層
3‧‧‧導線架封裝單元
36‧‧‧支撐段
31‧‧‧晶片座
361‧‧‧凹槽
311‧‧‧頂面
100‧‧‧基片
312‧‧‧底面
101‧‧‧第一分隔島
313‧‧‧底部
102‧‧‧第二分隔島
314‧‧‧連接部
201A‧‧‧導線架
32‧‧‧引腳
3A‧‧‧導線架單元
321‧‧‧凹槽
本新型之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是說明習知四方扁平無外引腳導線架結構的示意圖; 圖2是說明利用圖1所示之四方扁平無外引腳導線架封裝的封裝結構剖視示意圖; 圖3是說明本新型預成形封裝導線架的一實施例的俯視示意圖; 圖4是圖3中4-4割線的剖視圖; 圖5說明經由蝕刻製程後得到的導線架結構示意圖; 圖6是說明利用圖3所示之預成形封裝導線架進行晶片封裝後的封裝結構剖視示意圖; 圖7說明本新型該實施例,其中,該導線架封裝單元還包含支撐部的態樣; 圖8是圖7中8-8割線的剖視圖; 圖9說明本新型該實施例中,該晶片座的另一結構態樣;及 圖10是圖9中10-10割線的剖視圖。
200‧‧‧預成形封裝導線架
21‧‧‧第一分隔架
22‧‧‧第二分隔架
3‧‧‧導線架封裝單元
31‧‧‧晶片座
32‧‧‧引腳
321‧‧‧凹槽
33‧‧‧成形膠層

Claims (6)

  1. 一種預成形封裝導線架,包括多條由金屬材料構成,呈縱向及橫向間隔排列且彼此相交的第一、二分隔架,及多個成陣列排列的導線架封裝單元,其中,每一個導線架封裝單元是由任兩相鄰且彼此相交的該等第一、二分隔架共同定義出,且該每一個導線架封裝單元,包含: 至少一晶片座,由與該等第一、二分隔架相同的金屬材料構成; 多條引腳,由與該晶片座相同的金屬材料構成,自該等第一分隔架或第二分隔架的至少其中任一,朝向該至少一晶片座延伸並與該至少一晶片座成一間距,且該等引腳於遠離該至少一晶片座的一側,具有自該等引腳的頂面向下形成的凹槽;及 一成形膠層,由絕緣高分子材料構成,填置於該至少一晶片座與該等第一、二分隔架之間的間隙及該等引腳的凹槽。
  2. 如請求項1所述的預成形封裝導線架,其中,定義一用於切割該每一個導線架封裝單元的預切割道,該等引腳的凹槽位於該預切割道上。
  3. 如請求項2所述的預成形封裝導線架,其中,該每一個導線架封裝單元還包括多個分別連接該至少一晶片座與相鄰的該等第一分隔架或第二分隔架的支撐段,且該等支撐段於遠離該晶片座的一側,具有自該等支撐段的頂面向下形成的凹槽,該成形膠層還填置於該等支撐段的凹槽,且該等支撐段的凹槽也位於該預切割道上。
  4. 如請求項1所述的預成形封裝導線架,其中,該至少一晶片座具有一底部、多個自該底部向上延伸且彼此間隔的連接部,該成形膠層還填置於該等連接部之間的間隙,且不覆蓋該等連接部的頂面。
  5. 如請求項1所述的預成形封裝導線架,其中,該每一個導線架封裝單元還包含一金屬層,該金屬層形成於該晶片座及該等引腳未被該成形膠層遮覆的表面。
  6. 如請求項1所述的預成形封裝導線架,其中,第一、二分隔架的構成材料選自銅、銅系合金,或鐵鎳合金。
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