TWI466254B - 引腳延伸之半導體封裝及其製造方法 - Google Patents

引腳延伸之半導體封裝及其製造方法 Download PDF

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TWI466254B
TWI466254B TW101136942A TW101136942A TWI466254B TW I466254 B TWI466254 B TW I466254B TW 101136942 A TW101136942 A TW 101136942A TW 101136942 A TW101136942 A TW 101136942A TW I466254 B TWI466254 B TW I466254B
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semiconductor package
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wafer holder
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TW101136942A
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TW201338114A (zh
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Lin Wang Yu
ping cheng Hu
Che Chin Chang
Yu Fang Tsai
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Advanced Semiconductor Eng
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Description

引腳延伸之半導體封裝及其製造方法
本發明是有關於一種半導體單元及其製作方法，且特別是有關於一種四方扁平無引腳(Quad Flat No Lead,QFN)封裝結構及其製作方法。
半導體封裝技術包含有許多封裝形態，四方扁平無引腳封裝即為其中之一，四方扁平無引腳封裝具有較短的訊號傳遞路徑及相對較快的訊號傳遞速度，因此四方扁平無引腳封裝適用於高頻傳輸(例如射頻頻帶)之晶片封裝，且為低腳位(low pin count)封裝型態的主流之一。
在四方扁平無引腳封裝之製造方法中，多個晶片被固定於一導線架基材的多個晶片座上。這些晶片經由接合引線(bonding wires)電性連接至導線架的引腳(leads)。這些引腳、接合引線與晶片被模製化合物(molding compound)或包封材料(encapsulant)封裝與保護。這些引腳的底部暴露於封裝材料之外以電性連接至一外接裝置，此基材可被分割出個別的四方扁平無引腳封裝。
當四方扁平無引腳封裝的尺寸增加時，晶片與引腳之間的距離增加，由於電訊號需要傳輸較長距離，因而降低了封裝的表現。其中一個解決方法是增加引腳的延伸部以減少接合引線的長度。然而，當引腳的延伸部被暴露於包封材料之外且未連接於任何外接裝置時，暴露於空氣下的 引腳之延伸部便容易氧化。
本發明提出一種半導體封裝包括一晶片座、設置於晶片座上之一晶片及設置於晶片座旁之一第一引腳。第一引腳包含一接觸部、實質上沿晶片座方向延伸之一延伸部及設置於接觸部及延伸部之間的一凹曲側表面。具有一凹曲側表面之一第二引腳亦設置於晶片座旁。第一引腳之凹曲側表面之方向相反於第二引腳之凹曲側表面。
本發明更提出一種半導體封裝，包括一晶片座、設置於晶片座上之一晶片以及設置於晶片座旁之一第一引腳。第一引腳包含一凹曲側表面，第一引腳之凹曲側表面朝向半導體封裝之一下表面。一第二引腳設置於晶片座及第一引腳之間，第二引腳包含一凹曲側表面，第二引腳之凹曲側表面朝向半導體封裝之一上表面。
本發明再提出一種多個半導體封裝的製造方法，包括下列步驟，設置多個晶片於多個導線架上，其中每一導線架包含相對的一上表面與一下表面、一凹穴、多個第一凹口及多個第二凹口，其中(1)這些第一凹口形成於下表面且定義出多個第一引腳、多個延伸部以及連接這些第一引腳之這些延伸部之多個支持肋，(2)這些第二凹口形成於上表面且定義出多個第二引腳與多個晶片座，(3)這些凹穴的深度小於這些第二凹口的深度，(4)至少一第一凹口連通於至少一第二凹口。本方法更進一步包含晶片藉由多 個接合引線電性連接於這些延伸部及這些第二引腳。本方法更進一步包含形成一封裝板體以覆蓋這些晶片及這些接合引線且填充這些第一凹口及這些第二凹口。本方法更進一步包含自這些下表面移除每一引腳架的一部份與封裝板體的一部份以電性隔離這些晶片、這些第一引腳及這些第二引腳。本方法更進一步包含藉由切割封裝板體且移除這些支持肋而將每一晶片分開以形成這些半導體封裝。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
請參考圖1A，其繪示一導電基材110a具有相對之一上表面111及一下表面112。導電基材110a之材料可以是銅、鐵或是其他導電材料。一罩幕層10被形成以全面地覆蓋在導電基材110a之上表面111，且以一圖案化罩幕層20覆蓋導電基材110a之下表面112的一部分。在本實施例中，罩幕層10與圖案化罩幕層20可以是一乾膜光阻或一濕膜光阻。
請參考圖1B，以上述圖案化罩幕層20當作蝕刻罩幕，一半蝕刻程序作用於導電基材110a之下表面112以在導電基材110a上未被圖案化罩幕層20覆蓋的部分形成第一凹口114。第一凹口114定義出可用來當作外部引腳的第一引腳116。當此半蝕刻程序作用時，罩幕層10覆蓋且保護導電基材110a之上表面111。完成此半蝕刻程序後， 罩幕層10與圖案化罩幕層20被移除。
請參考圖1C，一罩幕層30被用來全面覆蓋下表面112且填入第一凹口114。一金屬層110b選擇性地電鍍於上表面111，且一圖案化罩幕層12被形成以覆蓋金屬層110b。金屬層110b為一抗氧化層，例如為一表面處理層，舉例來說可以是金、鈀、鎳、上述成分之混合物或是其他材料等。請參閱圖2，圖案化罩幕層12定義出多個晶片座113、第一引腳116、第一引腳116之延伸部117、可用來當作內部引腳118之第二引腳118及支持肋119的圖案。延伸部117係與第一引腳116一體且向內並朝向對應的晶片座113延伸。
圖1C’描述了相似於圖1C之實施例的另一實施例，除了圖1C’的實施例中金屬層110b的圖案不同於圖1C的實施例。由於圖案化罩幕層12被當作蝕刻罩幕使用，金屬層110b只形成於用來當作接點的區域。
請參考圖1D，使用圖案化罩幕層12來當作一蝕刻罩幕，一半蝕刻程序作用於導電基材110a之上表面111以在導電基材110a上未被圖案化光阻層12覆蓋的部分形成多個第二凹口115與這些晶片座113之多個凹穴113a。這些第二凹口115與這些凹穴113a之側面具有凹曲的輪廓。
請參閱圖1E，一第二圖案化罩幕層14被形成以覆蓋這些凹穴113a。使用圖案化罩幕層12與第二圖案化罩幕層14作為蝕刻罩幕，更有一半蝕刻程序作用於導電基材110a以增加第二凹口115之深度。在此半蝕刻程序完成之 後，部份第二凹口115連通於第一凹口114，以使這些第一引腳116與這些第二引腳118可在電性上及物理上相互隔絕。值得注意的是，在圖1E中，第一凹口114與第二凹口115似乎是被分開的，但在移除罩幕層30後，第一凹口114連通於第二凹口115(如圖1F所示)。
請參閱圖1F，在圖案化罩幕層12、第二圖案罩幕阻層14與罩幕層30被移除之後，即完成具有多個導線架110c之一導線架條(leadframe strip)110。每一導線架110c具有晶片座113、凹穴113a、第一凹口114、第二凹口115、第一引腳116、第一引腳116之延伸部117、第二引腳118及金屬層110b。請參閱圖2，這些第一引腳116被連接至這些支持肋119，這些支持肋119被連接至這些連結桿(tie bars)119a，且這些連結桿119a被連接至這些晶片座113以托住這些晶片座113。第一引腳116與第二引腳118具有凹曲的輪廓。晶片座113之凹穴113a之深度d1小於第二凹口115之深度d2，此在將晶片座113與第二引腳118隔絕的過程後，可保留晶片座113之部分厚度。其在圖1L中的步驟中有更詳細的敘述。凹穴113a亦具有一平坦區域，用以放置一晶片。此外，支持肋119被設置在兩鄰近的第一引腳116之間。在本實施例中，支持肋119被使用去連接多個引腳架110c，以便同時製造多個半導體封裝。在本實施例中以兩個導線架被支持肋119連接為例，以表現出導線架實際上以陣列的方式製作的狀況。
圖1G至圖1N是依照本發明之一實施例之一種半導 體封裝的製造方法之步驟的剖面示意圖。請參閱圖1G，這些晶片120被設置於晶片座113之凹穴113a內。這些晶片120可以被例如是黏著層、銀膠(colloidal silver)或是其他適合的材料固定於凹穴113a內。凹穴113a具有朝向晶片120之一曲內表面113c。
請參閱圖1H，晶片120利用多個接合引線130以電性連接至第一引腳116之延伸部117、第二引腳118及晶片座113。一加熱塊(heating block)40可被使用來支撐且加熱導線架條110之第一引腳116及第二引腳118。加熱塊40設置於下表面112且伸入第一凹口114以支撐第一引腳116之延伸部117。加熱塊40可加熱接合引線130與延伸部170之間的介面以增強共晶結合。此外，由於晶片120經由連接於晶片120及延伸部117之間的接合引線130電性連接至第一引腳116，相較於不具有延伸部117之結構，本實施例之半導體封裝100之接合引線130之長度可被縮短。
請參閱圖1I，一保護膜50被黏附於導線架條110的下表面112。保護膜50例如可以是一預模膠帶(pre-mold tape)。保護膜50不延伸入第一凹口114。
請參閱圖1J，一模製化合物160被形成以覆蓋晶片120、晶片座113、第二凹口115、第一引腳116、第二引腳118、支持肋119及接合引線130。如同上述，部份的第一凹口114在凹入部份114a以連接至第二凹口115。因此，模製化合物160可自第二凹口115流至第一凹口114 以包封第一引腳116之延伸部117。黏附至導線架條110之下表面112的保護膜50避免模製化合物160溢流至下表面112。
請參閱圖1K，保護膜50被移除。雖然此部份並未表示於圖中，模製化合物160的下表面可能從導線架110c之下表面112被輕微地擠壓。請參閱圖1L，其表示一作用於導線架條110之下表面112以移除部份導電基材110a與部份模製化合物160而暴露出第二凹口115以使晶片座113與第二引腳118在電性與物理上相互隔絕的程序。此程序例如可以是研磨、拋光、蝕刻或是其他合適的程序。因此第一引腳116之外部表面116a與第二引腳118之外部表面118a被暴露而提供了這些接觸部。在本實施例中，由於凹穴113a之第一深度d1小於第二凹口115之第二深度d2，凹穴113a在此過程中並不會被暴露。因此，晶片座113仍存在一厚度且在此過程完成後只有晶片座113之外表面113b被暴露。外表面113b,116a,118a與模製化合物160之下表面160a共平面。由於第二凹口115與晶片座113之凹穴113a經半蝕刻程序而形成，晶片座113與第二引腳118之側表面具有凹曲的輪廓。更特別的是，在本實施例之半導體封裝100中，第一引腳116具有開口於一第一方向之曲面或凹曲的側表面116b，一般來說曲面或凹曲的側面表面116b的方向朝下，且第二引腳118具有開口於相對於第一方向之一第二方向之曲面或凹曲的側表面118b，一般來說曲面或凹曲的側表面118b的方向朝上。此幾何結構 提供引腳與模製化合物160在機械力上的內連結，以抵抗這些引腳自模製化合物160分離。此幾何結構亦導致第一引腳116之外表面116a之表面區域小於第二引腳118之外表面118a之表面區域。
請參閱圖1M，多個銲球170配置於晶片座113、第一引腳116及第二引腳118之外表面113b、116a、118a，外表面113b、116a、118a暴露於模製化合物160外。這些銲球170有助於抵抗外表面113b、116a、118a氧化。銲球170亦被使用於電性連接至例如電路板之外部電路(未繪示)。銲球170可經由例如是一浸焊過程(dip soldering process)、一焊錫印刷過程、一無電電鍍過程或其他過程而形成。
請參閱圖1N，一分割程序被進行以移除支持肋119及模製化合物160的一部份以形成多個半導體封裝100。分割程序可能包含雷射切割或機械切割等。
第一引腳116與第二引腳118之凹曲側表面116b、118b以及第一引腳116之延伸部117的下表面117b被模製化合物160包封。只有晶片座113之外表面113b、第一引腳116之外表面116a及第二引腳118之外表面118a暴露。因此，可避免第一引腳116、第一引腳116之延伸部117及第二引腳118被包封的部份發生氧化。此外，晶片座113之曲內表面113c、第一引腳116與第二引腳118之凹曲側表面116b、118b成為鎖固結構以避免晶片座113、第一引腳116與第二引腳118自模製化合物160脫離。
圖2繪示圖1F之導線架的上表面之局部俯視示意圖。為了使讀者了解第一引腳116與支持肋119之間的連接關係，在圖2中僅就上表面111來描述，圖1D之金屬層110b並未繪示。圖2中的影線(hatching)指出導線架條100已從下方被半蝕刻。支持肋119連接位在兩鄰近導線架110c之邊緣的第一引腳116。因此，支持肋119連接鄰近的導線架110c去形成一導線架條110，以使多個半導體封裝100可被同時製造。
關於圖2，第一引腳116的延伸部117以非零角度朝遠離第一引腳116之方向延伸。在另一實施例中，延伸部117以任何角度朝遠離第一引腳116之方向延伸，包括沿著與第一引腳116相同的直線。延伸部117與第二引腳118之間的距離可被減少，以助於降低連接晶片120與延伸部117之接合引線130之長度。
請參閱圖3，圖3是依照本發明之一實施例之另一種半導體封裝的剖面示意圖。圖3之半導體封裝200與圖1N之半導體封裝100的差異僅在於，圖3之半導體封裝200以一第二金屬層210b配置於晶片座113之外表面113b、第一引腳116之外表面116a及第二引腳118之外表面118a。第二金屬層210b可避免晶片座113之外表面113b、第一引腳116之外表面116a及第二引腳118之外表面118a的氧化。此外，半導體封裝200經由此第二金屬層210b電性連接至例如是電路板之一外部電路(未繪示)。第二金屬層210b之材料可選自於由金、鈀、鎳或其混合物所組 成的群組，但不限於上述材料。第二金屬層210b的材料可與金屬層110b之材料不同。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、30‧‧‧罩幕層
12、14、20‧‧‧圖案化罩幕層
40‧‧‧加熱塊
50‧‧‧保護層
100、200‧‧‧半導體封裝
110‧‧‧導線架條
110a‧‧‧導電基材
110b‧‧‧金屬層
110c‧‧‧導線架
111‧‧‧上表面
112‧‧‧下表面
113‧‧‧晶片座
113a‧‧‧凹穴
113b‧‧‧外表面
113c‧‧‧曲內表面
114‧‧‧第一凹口
114a‧‧‧凹入部份
115‧‧‧第二凹口
116‧‧‧第一引腳
116a‧‧‧外表面
116b‧‧‧凹曲側表面
117‧‧‧延伸部
117b‧‧‧下表面
118‧‧‧第二引腳
118a‧‧‧外表面
118b‧‧‧凹曲側表面
119‧‧‧支持肋
119a‧‧‧連結桿
120‧‧‧晶片
130‧‧‧接合引線
160‧‧‧模製化合物
160a‧‧‧下表面
170‧‧‧銲球
210b‧‧‧第二金屬層
圖1A至圖1F是依照本發明之一實施例之一種導線架的製造方法之步驟的剖面示意圖。
圖1G至圖1N是依照本發明之一實施例之一種半導體封裝的製造方法之步驟的剖面示意圖。
圖2繪示圖1F之導線架的上表面之局部俯視示意圖。
圖3是依照本發明之一實施例之另一種半導體封裝的剖面示意圖。
100‧‧‧半導體封裝
113‧‧‧晶片座
113b‧‧‧外表面
116‧‧‧第一引腳
116a‧‧‧外表面
116b‧‧‧凹曲側表面
117b‧‧‧下表面
118‧‧‧第二引腳
118a‧‧‧外表面
118b‧‧‧凹曲側表面
120‧‧‧晶片
130‧‧‧接合引線
160‧‧‧模製化合物
170‧‧‧銲球

Claims (18)

  1. 一種半導體封裝，包括：一晶片座；一晶片，設置於該晶片座上；一第一引腳，設置於該晶片座旁，該第一引腳包含一接觸部、實質上沿該晶片座之方向延伸之一延伸部及設置於該接觸部及該延伸部之間的一凹曲側表面；以及一第二引腳，設置於該晶片座旁，該第二引腳包含一凹曲側表面；其中，該第一引腳之該凹曲側表面朝向該第二引腳之該凹曲側表面；其中該第一引腳之該凹曲側表面位在該第一引腳之一上表面下方。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該第一引腳之該凹曲側表面容納位於該第一引腳底部之一模製化合物的一部分以將該第一引腳固定在該半導體封裝內。
  3. 如申請專利範圍第1項所述之半導體封裝，其中該晶片座包含一凹穴，該凹穴具有朝向該晶片之一曲內表面。
  4. 如申請專利範圍第1項所述之半導體封裝，更包括：一金屬層，配置於該些第一引腳、該些第二引腳及晶片座之下表面，其中該金屬層突出於該半導體封裝之一下表面。
  5. 如申請專利範圍第1項所述之半導體封裝，更包括一模製化合物，該模製化合物覆蓋該些第一引腳、該些第二引腳之該些凹曲側表面及該些延伸部的下表面，且暴露出該些第一引腳、該些第二引腳及該晶片座的下表面。
  6. 如申請專利範圍第1項所述之半導體封裝，其中該延伸部斜向地延伸於該接觸單元與該晶片座之間。
  7. 如申請專利範圍第6項所述之半導體封裝，更包括：多個第一引腳，其中該些第一引腳成對地分組且每對第一引腳之該些延伸部背離該第一引腳且朝向該晶片座延伸。
  8. 如申請專利範圍第1項所述之半導體封裝，其中該第一引腳之外表面的表面區域小於該第二引腳之外表面的表面區域。
  9. 如申請專利範圍第1項所述之半導體封裝，更包括一模製化合物，該模製化合物包含一下表面，該下表面與該晶片座、該些第一引腳及該些第二引腳之該些下表面共平面。
  10. 一種半導體封裝，包括：一晶片座；一晶片，設置於該晶片座上；一第一引腳，設置於該晶片座旁，該第一引腳包含一凹曲側表面，該第一引腳之該凹曲側表面朝向該半導體封裝之一下表面；以及 一第二引腳，設置於該晶片座及該第一引腳之間，該第二引腳包含一凹曲側表面，該第二引腳之該凹曲側表面朝向該半導體封裝之一上表面；其中該第一引腳之該凹曲側表面位在該第一引腳的一上表面下方。
  11. 如申請專利範圍第10項所述之半導體封裝，其中該第一引腳之該凹曲側表面容納位於該第一引腳底部之一模製化合物的一部分以將該第一引腳固定在該半導體封裝內。
  12. 如申請專利範圍第10項所述之半導體封裝，其中該晶片座更包含具有一曲內表面的一凹穴，該凹穴之該曲內表面朝向該晶片及該半導體封裝的該上表面。
  13. 如申請專利範圍第10項所述之半導體封裝，其中該第一引腳包含一接觸部及斜向地延伸於該接觸部與該晶片座之間的一延伸部。
  14. 如申請專利範圍第13項所述之半導體封裝，更包括：多個第一引腳，其中該些第一引腳成對地分組且每對第一引腳之該些延伸部背離該第一引腳且朝向該晶片座延伸。
  15. 如申請專利範圍第10項所述之半導體封裝，其中該第一引腳之外表面的表面區域小於該第二引腳之外表面的表面區域。
  16. 一種多個半導體封裝的製造方法，包括： 設置多個晶片於多個導線架上，其中每一導線架包含相對的一上表面與一下表面、一凹穴、多個第一凹口及多個第二凹口，其中(1)該些第一凹口形成於該下表面且定義出多個第一引腳、多個延伸部以及連接該些第一引腳之該些延伸部之多個支持肋，(2)該些第二凹口形成於該上表面且定義出多個第二引腳與多個晶片座，(3)該些凹穴的深度小於該些第二凹口的深度，(4)該些第一凹口的至少其一連通於該些第二凹口的至少其一；該晶片藉由多個接合引線電性連接於該些延伸部及該些第二引腳；形成一封裝板體以覆蓋該些晶片及該些接合引線且填充該些第一凹口及該些第二凹口；自該些下表面移除每一導線架的一部份與該封裝板體的一部份以電性隔離該些晶片、該些第一引腳及該些第二引腳；以及藉由切割該封裝板體且移除該些支持肋而將每一晶片分開以形成該些半導體封裝。
  17. 如申請專利範圍第16項所述之多個半導體封裝的製造方法，其中在該晶片藉由多個接合引線電性連接於該些延伸部及該些第二引腳的步驟中，該導線架被一加熱塊支撐，且該加熱塊被放置在該些下表面且延伸至該些第一凹口的一部份以支撐該些延伸部。
  18. 如申請專利範圍第16項所述之多個半導體封裝的製造方法，其中在形成該封裝板體的步驟中，包含： 黏附一保護膜至該些導線架之該些下表面；注入一模製化合物以形成該封裝板體以覆蓋該些晶片及該些接合引線，其中該模製化合物自該些第二凹口流至該些第一凹口以使該模製化合物填充於該第一凹口與第二凹口；以及移除該保護膜。
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