TWI381506B - 先進四方扁平無引腳封裝結構及其製造方法 - Google Patents

先進四方扁平無引腳封裝結構及其製造方法 Download PDF

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TWI381506B
TWI381506B TW098122244A TW98122244A TWI381506B TW I381506 B TWI381506 B TW I381506B TW 098122244 A TW098122244 A TW 098122244A TW 98122244 A TW98122244 A TW 98122244A TW I381506 B TWI381506 B TW I381506B
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Taiwan
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wafer
pins
pin
package structure
quad flat
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TW098122244A
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English (en)
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TW201010037A (en
Inventor
Chien Pao Huei Chang
ping cheng Hu
Po Shing Chiang
Wei Lun Cheng
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Advanced Semiconductor Eng
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

先進四方扁平無引腳封裝結構及其製造方法
本發明大體上是有關於一種封裝結構及其製造方法。更明確而言，本發明是有關於一種先進四方扁平無引腳(advanced quad flat non-leaded，a-QFN)封裝結構及其製造方法。
本申請案主張2008年8月21日申請之美國臨時申請案第61/090,879號的優先權權益。上文所提及之專利申請案之全文特此以引用之方式併入本文中，且構成說明書的一部分。
依據導線架(leadframe)之引腳的形狀，四方扁平封裝(quad flat package，QFP)可分為I型(QFI)、J型(QFJ)及無引腳型(QFN)封裝。由於QFN封裝結構具有相對較短之信號傳遞路徑以及較快之信號傳輸速度，所以QFN封裝結構已成為具有較低腳位(pin count)之封裝結構的一種風行選擇，且適合具有高頻(例如，射頻頻寬)傳輸之晶片封裝(chip package)。
一般而言，在QFN封裝結構之製造過程中，多個晶片配置於導線架上，且藉由多條焊線而電性連接至導線架。接著，形成一封裝膠體以包覆導線架、晶片及焊線。最後，經由單體化(singulation)製程來形成多個QFN晶片封裝結構。
本發明針對一種先進四方扁平無引腳封裝結構及其製造方法，其有助於減少交叉線(cross wire)問題並增強產品可靠度。
本發明提供一種先進四方扁平無引腳封裝結構。先進四方扁平無引腳封裝結構包括一載體、一配置於載體上的晶片、多條焊線以及一封裝膠體。載體包括一晶片座(die pad)以及多個引腳，且引腳包括多個圍繞晶片座配置的第一引腳、多個圍繞第一引腳配置的多個第二引腳，以及至少一嵌入引腳部。每一第一引腳包括一第一內引腳以及一第一外引腳，而每一第二引腳包括一第二內引腳以及一第二外引腳。嵌入引腳部位於第一內引腳與第二內引腳之間。焊線配置於晶片、第一內引腳與嵌入引腳部之間。封裝膠體包覆晶片、晶片座、焊線、第一內引腳、第二內引腳以及嵌入引腳部。
根據本發明之一實施例，嵌入引腳部可為一配置於第一內引腳與第二內引腳之間且與第一內引腳以及第二內引腳電性絕緣的浮置端子。因此，封裝結構可更包括至少一配置於浮置端子與第二內引腳之一之間的跨接線(jumper)，以使得晶片透過焊線、浮置端子以及跨接線而電性連接至第二內引腳。跨接線的材料可與焊線的材料相同或不同。或者，根據本發明之另一實施例，嵌入引腳部為一使第一內引腳之一與第二內引腳之一直接連接的連接部，以使得晶片透過焊線以及連接部而電性連接至第二內引腳。
根據本發明之一實施例，載體更包括位於晶片座上且透過焊線電性連接至晶片的至少一接地環(ground ring)及/或電源環(power ring)。電源環與接地環電性絕緣。
本發明更提供一種先進四方扁平無引腳封裝結構之製造方法，包括以下步驟。提供一載體。載體具有至少一容納槽(accommodating cavity)、多個第一內引腳、多個第二內引腳以及由多個開口所定義的至少一引腳部。第一內引腳圍繞容納槽配置，第二內引腳圍繞第一內引腳配置，且引腳部配置於第一內引腳與第二內引腳之間。在載體之一下表面上包括覆蓋於載體之對應於第一內引腳及第二內引腳的多個第一金屬部，及覆蓋於載體之對應於容納槽的多個第二金屬部。提供一晶片於容納槽內後，提供多條焊線。焊線配置於晶片、第一內引腳與引腳部之間。接著，形成一封裝膠體以包覆晶片、焊線、第一內引腳、第二內引腳、引腳部，並填充容納槽以及開口內。之後，藉由載體之下表面上的第一金屬部以及第二金屬部作為蝕刻罩幕來進行一蝕刻製程，以蝕刻穿過載體直至填充於開口內之封裝膠體暴露為止，以便形成多個第一引腳、多個第二引腳以及一晶片座。
根據本發明之一實施例，當引腳部為一配置於第一內引腳與第二內引腳之間並與第一內引腳以及第二內引腳電性絕緣的浮置端子時，製造方法更包括在形成封裝膠體前，形成配置於浮置端子與第二內引腳之一之間的至少一跨接線，以使得晶片透過焊線、浮置端子以及跨接線而電性連接至第二內引腳。跨接線的材料可與焊線的材料相同或不同。或者，當嵌入引腳部為一使第一內引腳之一與第二內引腳之一直接連接的連接部時，晶片經由焊線以及連接部而電性連接至第二內引腳。
根據本發明之一實施例，在提供晶片之前，先進四方扁平無引腳封裝結構之製造方法更包括在容納槽之中心部上形成黏著層。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
現將詳細參考本發明之目前較佳實施例，其實例在隨附圖式中說明。在任何可能之處，圖式及描述內容中均使用相同參考編號來指代相同或相似部分。
圖1A至圖1H為本發明之一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
首先，請參考圖1A，提供具有一上表面210a以及一下表面210b的基板210。基板210的材料例如為銅、銅合金或其他適用的金屬材料。
接著，請再參考圖1A，形成一第一圖案化光阻層214a於基板210的上表面210a上，且形成一第二圖案化光阻層214b於基板210的下表面210b上。第一圖案化光阻層214a暴露出部分基板210的上表面210a，而第二圖案化光阻層214b暴露部分基板210的下表面210b。然而，第一圖案化光阻層214a與第二圖案化光阻層214b不對稱。
接著，請參考圖1B，形成一第一金屬層216a於基板210被暴露出的上表面210a上，且形成一第二金屬層216b於基板210被暴露出的下表面210b上。在本實施例中，第一金屬層216a與第二金屬層216b可藉由例如電鍍而形成。本文所描述之第一金屬層216a或第二金屬層216b可不為一連續層，此視第一圖案化光阻層214a或第二圖案化光阻層214b之圖案設計而定。
更詳細而言，第二金屬層216b包括多個第一金屬部217a以及至少一第二金屬部217b。第一金屬部217a對應於隨後將形成之第一內引腳232以及第二內引腳234(無對應隨後將形成之第三內引腳236)，且第二金屬部217b對應於隨後將形成之晶片座220(如圖1D中所示)。
接著，請參考圖1C，同時移除第一圖案化光阻層214a以及第二圖案化光阻層214b，且分別保留第一金屬層216a以及第二金屬層於基板210的上表面210a以及下表面210b上。
接著，請參考圖1D，藉由利用第一金屬層216a作為蝕刻罩幕來進行一蝕刻製程，以移除部分基板210，以便形成至少一容納槽220a以及多個第一開口S1。至此，在形成第一金屬層216a、第二金屬層216b並圖案化基板210後，粗略地形成載體200。
詳細而言，容納槽220a具有中心部222及圍繞中心部222配置的周邊部224。藉由開口S1來定義，以形成多個第一內引腳232、多個第二內引腳234以及至少一第三內引腳236。第一內引腳232環繞周邊部224配置。第二內引腳234環繞第一內引腳232配置。第三內引腳236配置於第一內引腳232與第二內引腳234之間。值得注意的是，周邊部224可視為接地環。
接著，請參考圖1E，提供至少一晶片300至每一容納槽220a的中心部222，其中一黏著層700位於晶片300與容納槽220的中心部222之間。透過配置於晶片300與容納槽220a之中心部222之間的黏著層700，可增加晶片300與中心部222之間的黏著力。
接著，請參考圖1F，提供多個焊線400以及至少一跨接線500。在本實施例中，焊線400配置於晶片300、接地環(周邊部)224、第一內引腳232以及第三內引腳236之間。詳細而言，焊線400之一端焊接於晶片300上，而焊線400之另一端焊接於接地環(周邊部)224、第一內引腳232以及第三內引腳236上。換言之，晶片300透過焊線400電性連接至接地環(周邊部)224、第一內引腳232以及第三內引腳236。
跨接線500配置於第三內引腳236與第二內引腳234之間，以使晶片300與第二內引腳234電性連接。跨接線500的材料可不同於焊線400的材料。舉例而言，跨接線500的材料可選自金、銅、鎳、鈀或其合金，而焊線400之材料可為金。晶片300透過焊線400電性連接至第三內引腳236，且晶片300透過跨接線500更進一步電性連接至第二內引腳234。第三內引腳236以及跨接線500之設計可代替直長線，且避免焊線偏移(wire sweep)或交叉線所引起之問題。
接著，請參考圖1G，形成一封裝膠體600以包覆晶片300、焊線400、跨接線500、第一內引腳232、第二內引腳234、接地環(周邊部)224以及第三內引腳236，並填充於容納槽220a以及第一開口S1內。
接著，請參考圖1H，對載體200的下表面210b進行一蝕刻製程，以移除基板210被暴露的部分，載體200被蝕穿以暴露出填充於第一開口S1內的封裝膠體600，且同時形成多個第二開口S2。第一內引腳232、第二內引腳234以及第三內引腳236透過蝕刻製程而彼此電性絕緣。此外，對載體200的下表面210b進行蝕刻製程以形成第二開口S2的期間，具有中心部222以及周邊部224的晶片座220進一步由載體200之第二開口S2所定義。晶片座220是由第一引腳232所環繞，且透過第二開口S2與第一引腳232電性絕緣。
詳細而言，在本實施例中，對載體200的下表面210b進行蝕刻製程，以便形成第二開口S2。此外，由於對應於第三內引腳236的基板210未被第二金屬層216b所覆蓋，因此對應於第三內引腳236的基板210會透過蝕刻製程而被移除。第三內引腳236可視為浮置端子。本文所描述之跨接線500具有不同於焊線400的功能。一般而言，焊線400用於連接晶片300與其他引腳，而跨接線500用於連接浮置端子(第三內引腳)236與其他引腳，但不連接至晶片300。因此，完成設計有浮置端子(第三內引腳)236以及跨接線500中之一或多者的先進四方扁平無引腳封裝結構100。
簡言之，本實施例之先進四方扁平無引腳封裝結構100使用浮置端子(第三內引腳)236以及跨接線500來代替直長線，使得晶片300可透過跨接線500以及浮置端子(第三內引腳)236電連接至較遠的引腳(例如，第二內引腳234)。因此，本實施例之先進四方扁平無引腳封裝結構100可避免焊線偏移或交叉線問題之可能性並增強產品能力。
圖2A為本發明之一實施例之一種先進四方扁平無引腳封裝結構的俯視示意圖。圖2B為沿圖2A之線I-I’的剖面示意圖。為了方便說明起見，圖2A中省略繪示部分元件。請同時參考圖2A與圖2B，在本實施例中，先進四方扁平無引腳封裝結構100包括一載體200、一晶片300、多條焊線400以及至少一跨接線500。
在本實施例中，載體200例如為導線架。詳細而言，載體200包括一晶片座220以及多個引腳230。引腳230包括多個第一引腳232、多個第二引腳234以及至少一浮置端子236。在圖2A中，僅示意性地描繪二個浮置端子236。具體而言，第一引腳232圍繞晶片座220配置，且每一第一引腳232包括一第一內引腳232a以及一第一外引腳232b。第二引腳234圍繞第一引腳232配置，且每一第二引腳234包括一第二內引腳234a以及一第二外引腳234b。內引腳及外引腳是由封裝膠體來界定，也就是說，引腳230被封裝膠體包覆的部分定義為內引腳，而引腳230暴露於封裝膠體外的部分定義為外引腳。浮置端子236配置於晶片座220的上表面上，且位於第一內引腳232a與第二內引腳234a之間。
更詳細而言，本實施例之晶片座220具有矩形形狀。舉例而言，引腳230可沿晶片座220之兩側配置，或排列成一環狀以環繞晶片座220配置。引腳230的排列可例如呈一陣列、單一列或多個列的環。在本實施例中，圖2A之第一引腳232以及第二引腳234的配置僅為舉例說明，本發明並不以此為限。此外，引腳230的材料包括金或鈀。
焊線400配置於晶片300、第一引腳232與浮置端子236之間。詳細而言，焊線400之一端焊接於晶片300上，而焊線400之另一端焊接於第一內引腳232a以及浮置端子236上。換言之，晶片300透過焊線400電性連接至載體200之較近的第一引腳232或浮置端子236。
跨接線500配置於浮置端子236與較遠的第二引腳234之間。跨接線500之一端焊接於浮置端子236上，而跨接線500之另一端焊接於第二內引腳234a上。晶片300透過浮置端子236以及跨接線500而電性連接至第二引腳234。
此外，本實施例中之先進四方扁平無引腳封裝結構100更包括一封裝膠體600。封裝膠體600包覆晶片300、焊線400、跨接線500、第一內引腳232a、第二內引腳234a、浮置端子236，且填充於引腳230之間的間隙，而暴露出第一外引腳232b、第二外引腳234b以及晶片座220之底部表面。封裝膠體600的材料例如為環氧樹脂(epoxy resin)或另一適用的聚合物材料。
另外，在本實施例中，為了滿足先進四方扁平無引腳封裝結構100之電性整合設計的要求，載體200更包括至少一接地環240以及至少一電源環250。接地環240配置於第一引腳232與晶片座220之間，且透過焊線400電性連接至晶片300。電源環250配置於第一引腳232與晶片座220之間，且透過焊線400電性連接至晶片300。由於接地環240連接至晶片座220，因此晶片座連同接地環可一起視為接地平面。電源環250與接地環240電性絕緣。
值得注意的是，圖2A與圖2B中所示之接地環240以及電源環250的位置、配置及數量僅為舉例說明，本發明並不以此為限。
簡言之，本實施例中之先進四方扁平無引腳封裝結構100具有浮置端子236與跨接線500，使得晶片300可透過浮置端子236與跨接線500電連接至較遠引腳(例如，第二引腳234)。因此，浮置端子236與跨接線500之設計可代替直長線。因此，本實施例之先進四方扁平無引腳封裝結構100可避免長線偏移或交叉線問題之可能性，並增強產品能力。
圖3A至圖3E為本發明之另一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
請先參考圖3A，在本實施例之先進四方扁平無引腳封裝結構100a之製造方法中，首先，提供載體200a。載體200a具有至少一容納槽220a’、多個第一開口S1，、一形成於載體200a之一上表面210a’上的第一金屬層216a’以及一形成於載體200a之一下表面210b’上的第二金屬層216b’。第一金屬層216a’與第二金屬層216b’不對稱。更詳細而言，第二金屬層216b’包括多個第一金屬部217a’以及一第二金屬部217b’。第一金屬部217a’對應於隨後將形成之第二內引腳234aa，且第二金屬部217b’對應於隨後將形成之晶片座220a(圖3E中所示)。此外，形成載體200a之步驟類似於圖1A至圖1C所示之步驟，於此不再贅述。
詳細而言，每一容納槽220a’具有一中心部222a以及一圍繞中心部222a配置的周邊部224a。請參考圖3A，載體200a的第一金屬層216a’藉由第一開口S1’定義成多個第一內引腳232aa、多個第二內引腳234aa以及至少一連接部236a。具體而言，第一內引腳232aa靠近或環繞周邊部224a配置。第二內引腳234aa配置於第一內引腳232aa附近或環繞第一內引腳232aa配置。第一金屬層216a’的每一連接部236a配置於每一第一內引腳232aa與每一第二內引腳234aa之間。
在此必須注意的是，每一連接部236a連接一個第一內引腳232aa與一個鄰近的第二內引腳234aa。在本實施例中，周邊部224a可視為接地環。
接著，請參考圖3B，提供至少一晶片300a至容納槽220a’的中心部222a，其中一黏著層600a配置於晶片300a與容納槽220a’的中心部222a之間。
接著，請參考圖3C，形成多條焊線400a。在本實施例中，焊線400a配置於晶片300a、接地環(周邊部)224a與第一內引腳232aa之間。晶片300a透過焊線400a電性連接至接地環224a以及第一內引腳232aa。由於每一連接部236a連接一個第一內引腳232aa與一個鄰近的第二內引腳234aa，因此晶片300a可透過連接部236a與焊線400a而電性連接至第二內引腳234aa。換言之，連接部236a的設計是用以連接兩個相鄰引腳(例如，第一內引腳232aa及第二內引腳234aa)，可減小焊線400a的長度。
接著，請參考圖3D，形成一封裝膠體500a以包覆晶片300a、焊線400a、第一內引腳232aa、第二內引腳234aa、接地環(周圍部)224a以及連接部236a，並填充於容納槽220a’以及第一開口S1’內。
接著，請參考圖3E，對載體200a的下表面210b’進行一蝕刻製程，以移除載體200a未被第二金屬層216b’所覆蓋的部分，直至暴露出封裝膠體500a且形成多個第二開口S2’為止。填充於第一開口S1’中的封裝膠體500a透過第二開口S2’而暴露。因此，第一引腳232a與第二內引腳234a彼此電性絕緣，除了連接部236a所連接的第一引腳232a與第二引腳234a之外。此外，對應於第一內引腳232aa以及連接部236a之載體200a的暴露部分在蝕刻製程期間亦同時被移除，直至第一開口S1’內之封裝膠體500a透過第二開口S2而暴露為止。簡言之，第一引腳232a以及第二引腳234a透過蝕刻製程而彼此電性絕緣，除了連接部236a所連接之第一引腳232a與第二引腳234a之外。金屬部的蝕刻速率及/或厚度，可透過精調而獲得最佳效能。
此外，在形成第二開口S2’的蝕刻製程期間，同時定義晶片座220a。晶片座220a是由第一內引腳232aa所環繞，且透過第一開口S1’或第二開口S2’與第一內引腳232aa電性隔離。最後，完成具有連接部236a之設計的先進四方扁平無引腳封裝結構100a。
如圖3E所示，移除連接至連接部236a之第一內引腳232aa的外引腳。也就是說，連接至連接部236a的第一引腳232a僅具有第一內引腳232aa。然而，如稍後在圖4A至圖4B中所示，對於大多數未連接至連接部236a的第一引腳232a而言，每一第一引腳232a包括第一內引腳232aa以及第一外引腳232ab。可視產品要求而定，有可能修改第二金屬層216b’之金屬部設計，以決定應保留亦或移除第一引腳232a或第二引腳234a的外引腳。
本實施例之先進四方扁平無引腳封裝結構100a具有連接兩個相鄰引腳(例如，第一內引腳232aa以及第二內引腳234aa)之連接部236a，可減小焊線400a的長度。因此，本實施例中先進四方扁平無引腳封裝結構100a可避免長線偏移(wire sweep)或交叉線問題之可能性，並增強產品能力。
圖4A為本發明之另一實施例之一種先進四方扁平無引腳封裝結構的俯視圖。圖4B為沿圖4A之線II-II’的剖面示意圖。為了方便說明起見，圖4A中省略繪示部份元件。請同時參考圖4A與圖4B，在本實施例中，先進四方扁平無引腳封裝結構100a包括一載體200a、一晶片300a以及多條焊線400a。
在本實施例中，載體200a例如為導線架。詳細而言，載體200a包括一晶片座220a以及多個引腳230a。引腳230a包括多個第一引腳232a、多個第二引腳234a以及至少一連接部236a。一般而言，對於大多數的第一引腳232a而言，每一第一引腳232a包括一第一內引腳232aa以及一第一外引腳232ab。對於連接至連接部236a的第一引腳232a而言，第一引腳可僅包括第一內引腳232aa，而無外引腳。對於第二引腳234a而言，每一第二引腳234a包括一第二內引腳234aa以及一第二外引腳234ab。在圖4A中，僅示意性地描繪兩個連接部236a。每一連接部236a配置於每一第一內引腳232aa與每一第二內引腳23aa之間。
由於引腳230a的材料以及晶片座220a的形狀類似於圖1A與圖1B中所描繪之前述實施例，且上文已描述，因此在此不再贅述。
晶片300a配置於晶片座220a上。焊線400a配置於晶片300a與引腳230a之間。在本實施例中，焊線400a之一端焊接於晶片300a上，而焊線400a之另一端焊接於連接部236a上。然而，由於連接部236a位於第一引腳232a與第二引腳234a之間，因此焊線400a可連接至較近的第一引腳232a或連接部236a之任何位置。一般而言，晶片300a透過焊線400a而電性連接至引腳230a。
另外，本實施例中之先進四方扁平無引腳封裝結構100a更包括一封裝膠體500a。封裝膠體500a包覆晶片300a、焊線400a，並填充引腳230a之間的間隙。換言之，封裝膠體500a包覆第一內引腳232aa、第二內引腳234aa以及連接部236a，而暴露出第一外引腳232ab以及第二外引腳234ab。
另外，本實施例之載體200a更包括用於電性整合設計之至少一接地環240a以及至少一電源環250a。由於接地環240a與電源環250a的位置、配置及數量類似於圖2A與圖2B中所描繪之前述實施例(如上文所描述)，因此在此不再贅述。此外，本實施例中之先進四方扁平無引腳封裝結構100a更包括一黏著層600a。黏著層600a配置於晶片300a與晶片座220a之間，用以增加晶片300a與晶片座220a之間的黏著力。
簡言之，本實施例之先進四方扁平無引腳封裝結構100a具有連接部236a，使得晶片300a可透過第一內引腳232aa與第二內引腳234aa之間的連接部236a而電連接至較遠的引腳(例如，第二引腳234a)。因此，連接兩個相鄰引腳之連接部236a的設計，可減小焊線400a之長度。因此，本實施例之先進四方扁平無引腳封裝結構100a可避免長線偏移(wire sweep)或交叉線問題之可能性，並增強產品能力。
綜上所述，先進四方扁平無引腳封裝結構的浮置端子或連接部可被視為嵌入引腳部，其主要嵌入先進四方扁平無引腳封裝結構的封裝膠體內，除了其底部表面暴露於封裝膠體之外。嵌入引腳部(意即浮置端子或連接部)可提供較佳電性連接以及可提高可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100a．．．先進四方扁平無引腳封裝結構
200、200a．．．載體
210．．．基板
210a、210a’．．．上表面
210b、210b’．．．下表面
214a．．．第一圖案化光阻層
214b．．．第二圖案化光阻層
216a、216a’．．．第一金屬層
216b、216b’．．．第二金屬層
217a、217a’．．．第一金屬部
217b、217b’．．．第二金屬部
220、220a．．．晶片座
220a、220a’．．．容納槽
222、222a．．．中心部
224、224a．．．周邊部/接地環
230、230a．．．引腳
232、232a、232aa．．．第一內引腳/第一引腳
232b、232ab．．．第一外引腳
234、234a、234aa．．．第二內引腳/第二引腳
234b、234ab．．．第二外引腳
236．．．第三內引腳/浮置端子
236a．．．連接部
240、240a．．．接地環
250、250a．．．電源環
300、300a．．．晶片
400、400a．．．焊線
500．．．跨接線
500a、600．．．封裝膠體
600a、700．．．黏著層
S1、S1’．．．第一開口
S2、S2’．．．第二開口
圖1A至圖1H為本發明之一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
圖2A為本發明之一實施例之一種先進四方扁平無引腳封裝結構的俯視示意圖。
圖2B為沿圖2A之線I-I’的剖面示意圖。
圖3A至圖3E為本發明之另一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
圖4A為本發明之另一實施例之一種先進四方扁平無引腳封裝結構的俯視示意圖。
圖4B為沿圖4A之線II-II’的剖面示意圖。
100．．．先進四方扁平無引腳封裝結構
200．．．載體
220．．．晶片座
230．．．引腳
232．．．第一引腳
232b．．．第一外引腳
234．．．第二引腳
234b．．．第二外引腳
236．．．浮置端子
240．．．接地環
250．．．電源環
300．．．晶片
400．．．焊線
500．．．跨接線
600．．．封裝膠體
700．．．黏著層

Claims (9)

  1. 一種先進四方扁平無引腳封裝結構，包括：一載體，具有一晶片座以及多個引腳，其中該些引腳包括多個圍繞該晶片座配置的第一引腳、多個圍繞該些第一引腳配置的第二引腳，以及一連接部，該連接部直接連接該些第一引腳之一及該些第二引腳之一；一晶片，配置於該載體的一上表面上且位於該晶片座內；一焊線，連接該晶片及至少該些第一引腳之一；以及一封裝膠體，包覆該晶片座上的該晶片、該焊線、部分該些第一引腳、部分該些第二引腳以及部分該連接部，其中該連接部具有一下表面，至少部分該下表面、該些第一引腳之一的一下表面與該封裝膠體之一下表面實質上共平面，該些第二引腳之一突出於該封裝膠體之該下表面。
  2. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該晶片透過該焊線與該連接部而電性連接至該些第二引腳之一。
  3. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該載體更包括至少一接地環，位於該晶片座上且透過該些焊線而電性連接至該晶片。
  4. 如申請專利範圍第3項所述之先進四方扁平無引腳封裝結構，其中該載體更包括至少一電源環，位於該晶片座上且透過該些焊線而電性連接至該晶片，該電源環與該接地環電性絕緣。
  5. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，更包括一配置於該晶片與該晶片座之間的黏著層。
  6. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該些引腳的材料包括金或鈀。
  7. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該些第一引腳配置較為靠近該晶片座，而該些第二引腳配置較為遠離該晶片座。
  8. 一種先進四方扁平無引腳封裝結構之製造方法，包括：提供一載體，該載體具有至少一容納槽、多個第一內引腳、多個第二內引腳以及一連接部，其中該些第一內引腳圍繞該容納槽配置，該些第二內引腳圍繞該些第一內引腳配置，且該連接部直接連接該些第一內引腳之一與該些第二內引腳之一，該載體更包括配置於該載體之一下表面上且對應於該些第二內引腳的多個第一金屬部以及對應於該容納槽的至少一第二金屬部；提供一晶片至該容納槽；形成一焊線，連接該晶片及至少該些第一內引腳之一；在該載體上形成一封裝膠體以包覆該晶片、該焊線、該些第一內引腳、該些第二內引腳及該連接部，並填充該容納槽內；以及藉由該載體之該下表面上的該些第一金屬部以及該 第二金屬部作為蝕刻罩幕來進行一蝕刻製程，以蝕穿該載體至部分該封裝膠體暴露為止，以便形成多個第一引腳、多個第二引腳以及一晶片座，其中該連接部具有一下表面，至少部分該下表面、該些第一引腳之一的一下表面與該封裝膠體之一下表面實質上共平面，該些第二引腳之一突出於該封裝膠體之該下表面。
  9. 如申請專利範圍第8項所述之先進四方扁平無引腳封裝結構之製造方法，其中在提供該晶片之前，更包括在該容納槽內形成一黏著層。
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