JP2005317998A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005317998A JP2005317998A JP2005214601A JP2005214601A JP2005317998A JP 2005317998 A JP2005317998 A JP 2005317998A JP 2005214601 A JP2005214601 A JP 2005214601A JP 2005214601 A JP2005214601 A JP 2005214601A JP 2005317998 A JP2005317998 A JP 2005317998A
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- semiconductor device
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- semiconductor element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】 中央に半導体素子11が、その周辺にエリアアレー状に、上面側がワイヤボンディング部12となって下面側が外部接続端子部13となった導体端子14が配置され、ワイヤボンディング部12と半導体素子11の各電極パッド15はボンディングワイヤ16で電気的に連結され、半導体素子11、ボンディングワイヤ16及び導体端子14の上半分は封止樹脂18で樹脂封止されている。
【選択図】 図1
Description
また、BCC型の半導体装置においては、ベースメタルをエッチングによってリムーブすると固片になってしまうので、モールド面を粘着テープで固定する必要があり、コスト高となるという問題がある。
本発明はかかる事情に鑑みてなされたもので、比較的安価に製造可能な半導体装置を提供することを目的とする。
そして、本発明に係る半導体装置において、前記半導体素子の底面側には導電性接着剤が塗布されているのが更に好ましい。
また、この半導体装置においては、外部接続端子部がエリアアレー状に配置されているので、他の基板との接合が容易となる。
ここに、図1は本発明の一実施の形態に係る半導体装置の製造方法の製造工程図、図2(A)、(B)はそれぞれ同方法で製造された半導体装置の説明図、図3は同方法で製造された半導体装置の使用状態を示す断面図である。
半導体素子11の底面側には導電性接着剤20が塗布され、これによって、半導体素子11からの熱放散を促進している。
図1(A)に示すように、板状のリードフレーム材21の表面側に、中央に搭載予定の半導体素子11を囲んで形成されるワイヤボンディング部12及びこれを囲む外枠17と、ワイヤボンディング部12に対応して裏面側に形成される外部接続端子部13とに貴金属めっき層22、23を形成する(第1工程)。
この貴金属めっき層22、23の形成は、リードフレーム材21の表面及び裏面を耐めっき性のフォトレジスト膜で覆った後、貴金属めっき層22、23が形成される部分に関する露光処理及びこれに続く現像処理を行って該リードフレーム材21の部分露出を行った後に、最初にニッケル等の下地めっき層を形成し、次に貴金属めっきを行う。このように、下地めっき層を介してAg、Au、Pdから選択された一種類の貴金属で貴金属めっき層22、23を形成することによって、リードフレーム材21に銅等を使用する場合のボンダビリティの確保と半田濡れ性の確保を維持している。
この後、図1(D)に示すように、半導体素子11、ボンディングワイヤ16、及び突出した外枠17を含むリードフレーム材21の表面側を封止樹脂18で樹脂封止する(第4工程)。
半導体装置の製造過程にあっては、半導体装置に残る外枠は周囲の外枠本体に実質的に連結されている必要があるので、外枠全体の全部の表面に貴金属めっき層を形成する必要はなく、外枠の一部(即ち、連結部分のみ)に貴金属めっき層を形成するのが好ましい。
また、前記実施の形態においては、耐エッチングレジスト膜の除去は、第5工程によって行ったが、第2工程が完了した後、裏面側のハーフエッチングを行う前であれば、何時行ってもよく、この場合も本発明は適用される。
Claims (3)
- 中央に半導体素子が、その周辺にエリアアレー状に、上面側がワイヤボンディング部となって下面側が外部接続端子部となった導体端子が配置され、前記ワイヤボンディング部と前記半導体素子の各電極パッドはボンディングワイヤで電気的に連結され、前記半導体素子、前記ボンディングワイヤ及び前記導体端子の上半分は封止樹脂で樹脂封止されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記導体端子の外側には導体からなる外枠が設けられ、該外枠の上半分が封止樹脂で樹脂封止されていることを特徴とする半導体装置。
- 請求項1及び2のいずれか1項に記載の半導体装置において、前記半導体素子の底面側には導電性接着剤が塗布されていることを特徴とする半導体装置。
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JP2005214601A JP3947750B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法及び半導体装置 |
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JP2005214601A JP3947750B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法及び半導体装置 |
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JP19322599A Division JP3780122B2 (ja) | 1999-07-07 | 1999-07-07 | 半導体装置の製造方法 |
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JP2007067330A Division JP4137981B2 (ja) | 2007-03-15 | 2007-03-15 | 半導体装置の製造方法 |
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Cited By (12)
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US7834469B2 (en) | 2008-05-12 | 2010-11-16 | Advanced Semiconductor Engineering, Inc. | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame |
US7858443B2 (en) | 2009-03-09 | 2010-12-28 | Utac Hong Kong Limited | Leadless integrated circuit package having standoff contacts and die attach pad |
US8072053B2 (en) | 2009-03-06 | 2011-12-06 | Kaixin Inc. | Leadless integrated circuit package having electrically routed contacts |
US8106492B2 (en) | 2009-04-10 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
JP2012503877A (ja) * | 2008-09-25 | 2012-02-09 | エルジー イノテック カンパニー リミテッド | 多列リードフレーム及び半導体チップパッケージ並びにその製造方法 |
US8115285B2 (en) | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
JP2012514326A (ja) * | 2008-12-24 | 2012-06-21 | エルジー イノテック カンパニー リミテッド | 多列リード型リードフレーム及びこれを用いた半導体パッケージの製造方法 |
US8237250B2 (en) | 2008-08-21 | 2012-08-07 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8785253B2 (en) | 2009-04-03 | 2014-07-22 | Kaixin, Inc. | Leadframe for IC package and method of manufacture |
US9362138B2 (en) | 2009-09-02 | 2016-06-07 | Kaixin, Inc. | IC package and method for manufacturing the same |
JP2016171101A (ja) * | 2015-03-11 | 2016-09-23 | Amテクノワークス株式会社 | 放熱基板の製造方法および放熱基板 |
US9570381B2 (en) | 2015-04-02 | 2017-02-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and related manufacturing methods |
Families Citing this family (3)
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CN101651126A (zh) * | 2008-08-12 | 2010-02-17 | 三星电子株式会社 | 芯片封装件及其制造方法 |
KR101445759B1 (ko) | 2010-03-30 | 2014-10-06 | 해성디에스 주식회사 | 리드 프레임 및 이를 사용한 집적회로 소자 |
KR101128999B1 (ko) * | 2010-07-08 | 2012-03-23 | 엘지이노텍 주식회사 | 칩 패키지 제조 방법 및 이에 의해 제조된 칩 패키지 |
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2005
- 2005-07-25 JP JP2005214601A patent/JP3947750B2/ja not_active Expired - Lifetime
Cited By (19)
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US8115285B2 (en) | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US8492883B2 (en) | 2008-03-14 | 2013-07-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a cavity structure |
US8120152B2 (en) | 2008-03-14 | 2012-02-21 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof |
US7834469B2 (en) | 2008-05-12 | 2010-11-16 | Advanced Semiconductor Engineering, Inc. | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame |
US8237250B2 (en) | 2008-08-21 | 2012-08-07 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8659131B2 (en) | 2008-09-25 | 2014-02-25 | Lg Innotek Co., Ltd. | Structure for multi-row lead frame and semiconductor package capable of minimizing an under-cut |
JP2012503877A (ja) * | 2008-09-25 | 2012-02-09 | エルジー イノテック カンパニー リミテッド | 多列リードフレーム及び半導体チップパッケージ並びにその製造方法 |
US8956919B2 (en) | 2008-12-24 | 2015-02-17 | Lg Innotek Co., Ltd. | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof |
JP2012514326A (ja) * | 2008-12-24 | 2012-06-21 | エルジー イノテック カンパニー リミテッド | 多列リード型リードフレーム及びこれを用いた半導体パッケージの製造方法 |
US8497159B2 (en) | 2009-03-06 | 2013-07-30 | Kaixin, Inc. | Method of manufacturing leadless integrated circuit packages having electrically routed contacts |
US8072053B2 (en) | 2009-03-06 | 2011-12-06 | Kaixin Inc. | Leadless integrated circuit package having electrically routed contacts |
US7858443B2 (en) | 2009-03-09 | 2010-12-28 | Utac Hong Kong Limited | Leadless integrated circuit package having standoff contacts and die attach pad |
US8736037B2 (en) | 2009-03-09 | 2014-05-27 | Utac Hong Kong Limited | Leadless integrated circuit package having standoff contacts and die attach pad |
US8785253B2 (en) | 2009-04-03 | 2014-07-22 | Kaixin, Inc. | Leadframe for IC package and method of manufacture |
US8106492B2 (en) | 2009-04-10 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US9362138B2 (en) | 2009-09-02 | 2016-06-07 | Kaixin, Inc. | IC package and method for manufacturing the same |
JP2016171101A (ja) * | 2015-03-11 | 2016-09-23 | Amテクノワークス株式会社 | 放熱基板の製造方法および放熱基板 |
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