CN109427698B - 组装qfp型半导体器件的方法 - Google Patents
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Abstract
本公开涉及一种组装QFP型半导体器件的方法。组装QFP型器件的方法包括:提供引线框,该引线框具有从阻挡杆延伸到管芯底盘的引线;并且执行用第一模塑料填充引线之间以及阻挡杆与管芯底盘之间的空间的第一模塑过程。第一模塑料还在管芯底盘周围形成环,其中环从引线框的两个横向侧面延伸。去除管芯底盘周围的第一区域以将引线与管芯底盘分离,并且去除阻挡杆的内角附近的第二区域以形成模具浇口。将管芯附接到管芯底盘并且用接合线电连接到引线,然后执行第二模塑过程以包封管芯、接合线和内引线。
Description
技术领域
本发明涉及集成电路(IC)的封装,并且更具体地涉及组装四方扁平封装(QFP)型器件的方法。
背景技术
QFP是具有从其四个侧面延伸的引线的表面安装IC封装。引线通常被成形或弯曲成“鸥翼”形。QFP是一项成熟的技术,自20世纪70年代以来一直在使用,因此与BGA封装相比,具有成熟的制造工具和材料基础设施以及较低成本的优势,引线计数范围为从48到208IO。使用引线框形成QFP,并且预期可以使用相同的引线框来封装具有不同管芯尺寸的芯片。然而,不同的管芯尺寸意味着将管芯或芯片电连接到引线框的引线的接合线的不同的环路长度。例如,当管芯尺寸小并且线节距很细时,必须延伸线环路长度,这可能导致包封期间的线蜿蜒(wire sweep),其中较长的线环路不能承受液体模塑料的转移压力。
解决较长的线长问题的一个解决方案是增加内引线长度。然而,为了节省成本,引线框已经变得较薄,例如从8密耳到5密耳,因此使用较薄金属制成的较长的引线在线接合期间容易弹起,这可能导致接合线与引线之间的结合强度差,并且将剩余应力引入到第二接合的后跟,这在现场应用期间有后跟破裂的危险。
期望具有用可以容纳各种尺寸管芯的薄引线框组装QFP型器件的可靠方法。
附图说明
当结合附图阅读时,将更好地理解本发明的优选实施例的以下详细描述。本发明以示例的方式例示出并且不受附图的限制,附图中相同的附图标记指示相似的元件。应当理解,为了便于理解本发明,附图不是按比例的并且被简化。
图1是根据本发明的实施例的引线框的放大俯视图;
图2A和图2B分别是第一模塑过程之后的图1的引线框的放大俯视图和放大侧视图;
图3是去除其中的某些部分之后的图2A和图2B的模塑后的引线框的俯视图;
图4A和图4B分别是线接合步骤之后的图3的组件的俯视图和侧视图;
图5A例示了对图4A和图4B的组件执行的第二模塑过程,并且图5B和图5C分别是在第二模塑过程之后的图4A和图4B的组件的俯视图和侧视图;
图6A是在去除组件的替代部分之后的图2A和图2B所示的组件的放大俯视图;
图6B和图6C是在附接了倒装芯片管芯之后的图6A的组件的放大俯视图和放大侧视图;
图6D是例示在第二模塑过程之后的图6B和图6C的组件的放大截面侧视图;和
图7是例示根据本发明的实施例的组装QFP器件的方法中的步骤的流程图。
具体实施方式
下面结合附图阐述的详细描述旨在作为本发明的当前优选实施例的描述,并不旨在表示可以实践本发明的唯一形式。应当理解,相同或等同的功能可以由旨在包含在本发明的精神和范围内的不同实施例来实现。在附图中,相同的附图标记始终用于指示相同的元件。
在一个实施例中,本发明提供了一种组装QFP型器件的方法,包括:提供引线框,该引线框具有阻挡杆、管芯底盘以及从阻挡杆延伸到管芯底盘的周边的多个引线。在一个实施例中,引线框还具有从阻挡杆的内角延伸到底盘的外角的连杆。执行其中第一模塑料填充引线之间以及底盘与阻挡杆之间的空间的第一模塑步骤。第一模塑料还形成与管芯焊盘间隔开并将在管芯焊盘周围的环,其中环具有使其从引线框的两个横向侧面突出的厚度。接下来,冲压模塑后的框架的角落以形成模具浇口,并且引线的内引线端与管芯底盘分离。然后将半导体管芯附接到引线框,并且管芯接合焊盘电连接到引线的靠近管芯底盘的内端。在一个实施例中,管芯是倒装芯片管芯,并且通过用焊料凸块将管芯接合焊盘附接到引线的内引线端而形成电连接部。在另一个实施例中,管芯附接到底盘,并且管芯接合焊盘通过接合线连接到引线的内引线端。执行第二模塑步骤以用第二模塑料覆盖管芯和电连接部,使得形成壳体。从壳体延伸出的阻挡杆和引线的外端可以被裁切,并且引线弯曲成任何期望的形状。
现在参考图1,示出了根据本发明的实施例的引线框10的俯视图。引线框10的形状通常为矩形,并且包括阻挡杆12、管芯底盘(die flag)14以及多个引线指或引线16。阻挡杆12包围管芯底盘14和引线16。引线16在阻挡杆12与管芯底盘14之间延伸。引线框10优选地由具有约5密耳厚度的铜片例如通过冲压、切割或蚀刻而形成。引线框10的尺寸可以从约7mm×7mm到约20mm×20mm变化,并且引线16的数量可以从约32到144变化。引线框10还可以用金属或金属合金镀敷以防止氧化,或者可以只对引线框10的某些区域(诸如管芯底盘14和/或引线16)镀敷。如镍、金和钯的镀敷材料是本领域技术人员已知的。引线16具有靠近阻挡杆12的外引线部分18和靠近管芯底盘14的内引线部分20。引线16可以在内引线部分20处比在外引线部分18处更宽或更窄。在一些实施例中,引线框10还包括从阻挡杆12的内角延伸到管芯底盘14的外角的连杆22,如图所示。通常,QFP引线框具有未连接到管芯底盘的引线。然而,在本发明中,优选地,引线16附接到管芯底盘14,因此引线16在处理和组装过程期间将会变形的可能性较小。
图2A和图2B分别是在第一模塑过程之后的图1的引线框10的俯视图和侧视图,在第一模塑过程中,形成第一模塑料24以填充引线16之间以及阻挡杆12与底盘14之间的空间。第一模塑料24还形成与管芯底盘14间隔开并且包围管芯底盘14的环26。也就是说,模塑工具被设计为使得存在顶和底引线框表面上的包围中央底盘以及引线16的内引线端20的两个模塑的环(称为环26)。环26具有使得环26从引线框10的两个横向侧面突出的厚度。在一个实施例中,模塑环26具有约0.2至0.3mm的厚度。模塑环26在第一模塑步骤期间平衡热机械应力。第一模塑料24包括通常用于半导体封装中并且本领域技术人员已知的环氧树脂。
图3是去除其中的某些部分之后的图2A和图2B的模塑后的引线框的俯视图。更具体地,内引线端20例如通过冲压、切割或蚀刻而物理和电气都与管芯底盘14分离,如由管芯底盘14周围示出的间隙28所指示的。在一个实施例中,引线框10包括连杆22,并且连杆22保持连接到管芯底盘14以提供对其的稳定性。在其它实施例中,连杆22可以用于提供电力(或接地),在这种情况下,与引线16类似,连杆22与管芯底盘14分离。在当前优选的实施例中,模塑后的引线框组件的靠近阻挡杆12的内角中的一个例如通过冲压或蚀刻也被去除,以形成模具浇口插入区域30,如下面将更详细描述的。
图4A和图4B分别是在管芯附接和线接合之后的图3的组件的俯视图和侧视图。半导体管芯32的底表面例如用环氧树脂粘合剂或粘合带附接到管芯底盘14。在所示的实施例中,管芯32在其顶表面上具有允许到管芯电路系统的电连接部的管芯接合焊盘。管芯32使用接合线34电连接到引线16的内引线端20。由于引线16从阻挡杆12延伸到管芯底盘14,因此线34不需要过长地从管芯32延伸到内引线端20。此外,环26提供机械支撑,从而可以进行可靠的针脚接合。管芯32可以是任何种类的管芯,例如微处理器、DSP、专用电路等,并且本发明不受管芯的类型的限制。管芯32也不限于诸如CMOS或任何特定的晶片技术得到的特定技术。此外,管芯32的尺寸可以变化,只要其适合于管芯底盘14即可。
图5A例示了对图4A和图4B的组件执行的第二模塑过程。包括引线框10、管芯32和接合线34的组件被插入到模具36中,使得在组件周围存在顶部和底部腔38、40以及与形成在组件的角落中的模具浇口插入件30配合的模具浇口42。然后通过模具浇口42将第二模塑料44(图5B和5C所示)注入顶部和底部腔38、40中。
图5B和图5C分别是第二模塑过程之后的图4A和图4B的组件的俯视图和侧视图。第二模塑料44覆盖管芯32、接合线34、包括环26的第一模塑料24,使得在它们周围形成壳体。阻挡杆12和引线16的外端部分18延伸超出壳体并从壳体突出。模塑环26通过增加第一和第二模塑料24、44之间的接触区域并减小第二模塑料44与引线框10的暴露部分之间的接触区域来在第二模塑过程期间形成锁定部件。在当前优选的实施例中,第一和第二模塑料24和44包含相同的材料;也就是说,它们包含相同的环氧树脂,因此不存在材料失配。
在从模具36中去除现在包封的组件之后,切除阻挡杆12,并且可以使从壳体延伸或突出的外引线端弯曲或成形,例如成为鸥翼形。应当理解,为了确保外引线端18被充分暴露,一些模塑料44也可被裁切或切除。
本发明还提供了一种组装使用倒装芯片管芯而不是线接合管芯32的QFP器件的方法。图6A是在去除组件的替代部分之后的图2A和图2B所示的组件的俯视图。更具体地,引线框10被第一模塑料24覆盖,然后将引线框底盘14切掉或去除以形成间隙50。内角之一也被切掉以形成如上所述的模具浇口插入区域30。
图6B和图6C是附接了倒装芯片管芯52之后的图6A的组件的俯视图和侧视图。更具体地,管芯52安装在引线16的内引线端20上,其中诸如用导电球54将管芯接合焊盘与内引线端20电连接。导电球54允许与管芯52的电互连。在一个实施例中,导电球54包括C4焊球。然后,该组件被第二模塑料44覆盖,使得形成壳体,其中外引线端18从壳体突出。图6D是例示在执行第二模塑过程之后使用倒装芯片管芯52组装并具有成形为鸥翼形的外引线端18的QFP型器件56的截面侧视图。
图7是总结根据本发明的实施例的组装QFP器件的方法中的步骤的流程图60。第一步骤62包括提供如图1所示的引线框10的引线框。引线框被设计成使得引线框的所有IO(引线)机械地连接到中央金属底盘。以这种方式,引线或引线指不太可能在引线框制造期间以及在封装组装过程期间变形。接下来,执行第一道模塑步骤64,其中引线之间的空间被第一模塑料24填充,该空间被阻挡杆12和管芯底盘14限定。还用第一模塑料24形成环26。在步骤66中,通过将内引线20与管芯底盘14的邻接部分分离,引线16与管芯底盘14的机械和电连接被切断。还形成模具浇口插入件。虽然图3和图6A所示的模具浇口插入区域30位于引线框的角落中,但这并不要求,因为模具浇口插入件可以位于其它区域中,只要它不损害任何引线16即可。可以通过冲压、切割或蚀刻使引线16与管芯底盘14分离并形成模具浇口插入区域30。在步骤68中,执行常规的管芯附接和常规的线接合。
在步骤70中,执行第二道模塑步骤。在该步骤中,管芯、接合线和引线框被第二模塑料覆盖。优选地,第二模塑料包括与第一模塑料相同的材料,其优选地是常规的半导体包封剂。在第一模塑道64中在管芯底盘14周围形成的模塑环26用于在第一模塑过程期间填充各种引线框部件(例如阻挡杆12、底盘14和引线16)之间的空隙/间隙。在引线框的两个横向侧面向外延伸的模塑环26有助于在第一模塑过程64期间平衡热机械应力,这允许在管芯接合和线接合过程68期间更好的可制造性。模塑环26还通过增加模塑料到模塑料接触区域并减小第二道模塑料到金属引线框接触区域来在第二模塑过程70期间形成锁定部件,从而允许更好的封装抗分层能力。在从模具中去除组件之后,壳体和外引线端可以被裁切和成形为例如鸥翼形。
从前面的讨论可以看出,本发明提供了组装QFP型器件的方法,并提供了根据该方法组装的QFP型器件。
为了例示和描述的目的,已经呈现了本发明的优选实施例的描述,但并不意图是穷尽的或将本发明限制于所公开的形式。本领域技术人员将理解,在不脱离本发明广泛的发明构思的情况下,可以对上述实施例进行改变。因此,应当理解,本发明不限于所公开的特定实施例,而是覆盖在由所附权利要求限定的本发明的精神和范围内的修改。
Claims (18)
1.一种组装QFP型器件的方法,包括:
提供引线框,所述引线框具有阻挡杆、管芯底盘和从阻挡杆延伸到管芯底盘的周边的多个引线;
执行其中第一模塑料填充引线之间以及底盘与阻挡杆之间的空间的第一模塑步骤,并且其中第一模塑料还形成与管芯底盘间隔开并在管芯底盘周围的环,其中所述环具有使得环从引线框的两个横向侧面突出的厚度;
将引线的内引线端与管芯底盘分离;
去除模塑后的框架的内角以形成模具浇口;
将半导体管芯附接到管芯底盘;
将管芯的接合焊盘与引线的靠近管芯底盘的内引线端电连接;
执行第二模塑步骤以用第二模塑料覆盖管芯和电连接部,使得形成壳体,其中阻挡杆和引线的外端延伸超出所述壳体。
2.根据权利要求1所述的组装QFP型器件的方法,其中在第二模塑步骤之后,从引线框切割阻挡杆。
3.根据权利要求2所述的组装QFP型器件的方法,还包括将引线的延伸超出所述壳体的外端形成为鸥翼形。
4.根据权利要求1所述的组装QFP型器件的方法,其中模塑环的厚度在0.2mm至0.3mm的范围内。
5.根据权利要求4所述的组装QFP型器件的方法,其中模塑环在第一模塑步骤期间平衡热机械应力。
6.根据权利要求4所述的组装QFP型器件的方法,其中模塑环通过增加第一模塑料与第二模塑料之间的接触区域并减小第二模塑料与引线框的暴露部分之间的接触区域来在第二模塑过程期间形成锁定部件。
7.根据权利要求1所述的组装QFP型器件的方法,其中第一模塑料和第二模塑料包含相同的材料。
8.根据权利要求1所述的组装QFP型器件的方法,其中用接合线将引线的内引线端与管芯接合焊盘电连接。
9.根据权利要求1所述的组装QFP型器件的方法,其中半导体管芯是倒装芯片型管芯,并且用导电凸块将管芯接合焊盘安装并附接到引线的内引线端。
10.根据权利要求1所述的组装QFP型器件的方法,其中内引线端通过冲压与管芯底盘分离。
11.根据权利要求1所述的组装QFP型器件的方法,其中通过冲压去除模塑后的框架的内角。
12.根据权利要求1所述的组装QFP型器件的方法,其中引线框还包括从阻挡杆的内角延伸到底盘的外角的连杆。
13.根据权利要求1所述的组装QFP型器件的方法,其中引线框由铜形成。
14.根据权利要求1所述的组装QFP型器件的方法,其中,用环氧树脂和粘合带之一将管芯附接到底盘。
15.一种根据权利要求1的方法形成的QFP型半导体器件。
16.一种QFP器件,包括:
半导体管芯,电连接到引线框的多个引线的内引线端;
环,由包围半导体管芯和管芯与内引线端的电连接部的第一模塑料形成,其中环形成在引线的中央部分之上并且从引线的横向表面向外延伸;以及
第二模塑料,在引线、半导体管芯、管芯与内引线端之间的电连接部以及环周围覆盖并形成壳体,其中引线的外引线端从壳体向外突出,以及其中所述第二模塑料在所述环的内侧表面和外侧表面上形成,以使包括所述第二模塑料的所述壳体的外横向侧暴露并使所述外引线端自所述外横向侧突出。
17.根据权利要求16所述的QFP器件,其中半导体管芯安装到引线框的管芯底盘,并且半导体管芯与内引线端之间的电连接部包括接合线。
18.根据权利要求16所述的QFP器件,其中半导体管芯包括倒装芯片管芯,并且管芯安装在内引线端上,使得管芯接合焊盘电耦接到内引线端。
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Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69131784T2 (de) * | 1990-07-21 | 2000-05-18 | Mitsui Chemicals, Inc. | Halbleiteranordnung mit einer Packung |
US5213748A (en) | 1991-06-27 | 1993-05-25 | At&T Bell Laboratories | Method of molding a thermoplastic ring onto a leadframe |
US5869883A (en) * | 1997-09-26 | 1999-02-09 | Stanley Wang, President Pantronix Corp. | Packaging of semiconductor circuit in pre-molded plastic package |
US6146924A (en) * | 1999-08-06 | 2000-11-14 | Vanguard International Semiconductor Corporation | Magnetic insert into mold cavity to prevent resin bleeding from bond area of pre-mold (open cavity) plastic chip carrier during molding process |
US6384472B1 (en) * | 2000-03-24 | 2002-05-07 | Siliconware Precision Industries Co., Ltd | Leadless image sensor package structure and method for making the same |
WO2004006325A1 (ja) | 2002-07-03 | 2004-01-15 | Mitsui Mining & Smelting Co.,Ltd. | フレキシブル配線基材及びその製造方法 |
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US7456499B2 (en) * | 2004-06-04 | 2008-11-25 | Cree, Inc. | Power light emitting die package with reflecting lens and the method of making the same |
US7074653B2 (en) * | 2004-08-23 | 2006-07-11 | Texas Instruments Incorporated | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
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US20080174981A1 (en) | 2007-01-24 | 2008-07-24 | Chan Say Teow | Pre-molded lead frame and process for manufacturing the same |
US9029999B2 (en) * | 2011-11-23 | 2015-05-12 | Freescale Semiconductor, Inc. | Semiconductor sensor device with footed lid |
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-
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CN101950726A (zh) * | 2010-09-04 | 2011-01-19 | 江苏长电科技股份有限公司 | 双面图形芯片正装先镀后刻单颗封装方法 |
CN103907185A (zh) * | 2011-08-11 | 2014-07-02 | 联达科技控股有限公司 | 具有多材料印刷形成的包装部件的引线载体 |
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