JP2005203390A - 樹脂封止型半導体装置の製造方法 - Google Patents
樹脂封止型半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 229920005989 resin Polymers 0.000 title claims abstract description 28
- 239000011347 resin Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 238000007789 sealing Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 5
- 239000010949 copper Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 238000000227 grinding Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 238000004382 potting Methods 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000001721 transfer moulding Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- 238000003754 machining Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 17
- 239000004593 Epoxy Substances 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
【解決手段】 本発明は樹脂封止型のリードレスタイプの半導体装置の構造、製造方法に関するものである。本発明の半導体装置においては、銅などの薄板の片面側をハーフエッチングして、複数のダイパッド部3、ボンディングエリア2を形成し、各ダイパッド部3に半導体素子4を搭載する。次いで、素子上の電極5とボンディングエリア2を電気接続し、半導体素子4搭載側をモールド樹脂7で封止し、次いで導電性基板側を段階的に均等に除去して、最終的にダイパッド部3とボンディングエリア2(外部接続用電極)だけが露出するようにする。最後にダイシング法で各々の半導体装置に個片化して、最終形態になる。
【選択図】 図1
Description
次いで、図1(c)に示すとおりに導電性金属基板1のダイパッド部3に半導体素子4をAgエポキシペーストなどの接着層で搭載後、半導体素子4上の電極5とボンディングエリア2を金線などの金属ワイヤ6を用いて超音波ワイヤボンディング装置などで電気接続する。
2・・・・・・ボンディングエリア
3・・・・・・ダイパッド部
4・・・・・・半導体素子
5・・・・・・電極
6・・・・・・金属ワイヤ
7・・・・・・モールド樹脂
8・・・・・・フォトレジスト
Claims (7)
- 導電性基板1の片面側をハーフエッチングしてダイパッド部3およびボンディングエリア2を形成する工程と、
前記ダイパッド部3に半導体素子4を銀ペーストを介して搭載後、半導体素子4上の電極5と上記ボンディングエリア2を金属ワイヤ6で電気接続する工程と、
半導体素子4の搭載部分をモールド樹脂 7で封止する工程と、
上記基板1のフレーム側を段階的に除去してダイパッド部3とボンディングエリア2が外部接続用電極になるように露出させて樹脂封止体を得る工程と、
前記封止体を個片化する工程とを有する半導体装置の製造方法。 - 前記ダイパッド部3およびボンディングエリア2が導電性基板1上に複数組並列して形成し、各ダイパッド部3に搭載された各半導体素子4と各半導体素子4上の電極5に対応するボンディングエリア2とを金属ワイヤ6で電気接続する工程と、
各半導体素子4搭載部分を連続したモールド樹脂7で封止し、導電性基板1のフレーム側を段階的に除去する工程とダイパッド部3とボンディングエリア2が外部接続用電極となるように露出させた各樹脂封止体を得る工程と個々の樹脂封止体に個片化する工程とを有する請求項1に記載の半導体装置の製造方法。 - 前記導電性基板1が銅、42アロイなどの金属であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体素子4上の電極5と上記ボンディングエリア2を電気的に接続する工程において金、銅もしくはアルミワイヤを用いたワイヤボンディング法によって行われることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記モールド樹脂7で封止する工程において前記樹脂封止が、ポッティング法もしくはトランスファモールド法によって行われることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記導電性基板1のフレーム側を除去し、ダイパッド部3および外部接続用電極を露出させる工程において、その方法が、バックグラインド装置などを使用した研削、研磨、もしくはエッチングによって行なわれることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記樹脂封止体を個片化する工程においてダイシング法を用いることを特徴とする請求項1に記載の半導体装置の製造方法。
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US11/031,267 US7271035B2 (en) | 2004-01-13 | 2005-01-07 | Manufacturing method for resin sealed semiconductor device |
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DE102006044690B4 (de) * | 2006-09-22 | 2010-07-29 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zum Herstellen |
US8053280B2 (en) * | 2007-11-02 | 2011-11-08 | Infineon Technologies Ag | Method of producing multiple semiconductor devices |
KR101454321B1 (ko) * | 2008-01-22 | 2014-10-23 | 페어차일드코리아반도체 주식회사 | 절연 금속 기판을 구비하는 반도체 패키지 및 그 제조방법 |
JP5224845B2 (ja) * | 2008-02-18 | 2013-07-03 | 新光電気工業株式会社 | 半導体装置の製造方法及び半導体装置 |
US8115285B2 (en) | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8124447B2 (en) * | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
EP2282360A1 (en) | 2009-08-06 | 2011-02-09 | Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO | Opto-electric device and method for manufacturing the same |
US20110163430A1 (en) * | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
JP5642473B2 (ja) * | 2010-09-22 | 2014-12-17 | セイコーインスツル株式会社 | Bga半導体パッケージおよびその製造方法 |
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