JP4911727B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4911727B2 JP4911727B2 JP2008268083A JP2008268083A JP4911727B2 JP 4911727 B2 JP4911727 B2 JP 4911727B2 JP 2008268083 A JP2008268083 A JP 2008268083A JP 2008268083 A JP2008268083 A JP 2008268083A JP 4911727 B2 JP4911727 B2 JP 4911727B2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Description
2a アイランド部
2b 電極部
4 樹脂層
6 レジストパターン層
11 実装用金属薄膜
12 リード層
13 ボンディング用金属膜
S 半導体素子
Claims (3)
- ステンレス基板(1)の一面側に、半導体素子(S)搭載用のアイランド部(2a)および上記半導体素子(S)の電極(L)と接続される電極部(2b)を形成するための所定パターンから成るレジストパターン層(6)を形成する工程と、
上記ステンレス基板(1)の露出面に対し、不活性膜を除去する工程と、
上記ステンレス基板(1)の不活性膜を除去した露出面に実装用金属薄膜(11)として金をメッキ成長させ、上記実装用金属薄膜(11)上に電鋳工程によりリード層(12)を積層して成長させ一体化して、上記実装用金属薄膜(11)とこの上面に一体に積層される上記リード層(12)の少なくとも二層構造から成る上記アイランド部(2a)および上記電極部(2b)を独立して形成する工程と、
上記ステンレス基板(1)より上記レジストパターン層(6)を除去する工程と、
上記アイランド部(2a)に上記半導体素子(S)を搭載した後、上記半導体素子(S)の上記電極(L)と上記電極部(2b)とを電気的に接続する工程と、
上記ステンレス基板(1)上の上記半導体素子(S)搭載部分を樹脂でモールドして樹脂層(4)を形成する工程と、
上記ステンレス基板(1)を引き剥がし除去して、上記アイランド部(2a)および上記電極部(2b)の上記実装用金属薄膜(11)の各裏面が、上記樹脂層(4)の底面と略同一平面で露出した状態で形成される工程
とを順に行うことを特徴とする半導体装置の製造方法。 - 上記アイランド部(2a)および上記電極部(2b)を形成後、少なくとも上記電極部(2b)の上記リード層(12)上に、メッキ工程によってボンディング用金属膜(13)を一体に成長形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 上記ボンディング用金属膜(13)は、金、銀、スズで形成したことを特徴とする請求項2に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2002379270A JP2004214265A (ja) | 2002-12-27 | 2002-12-27 | 半導体装置および半導体装置の製造方法 |
JP2008268083A JP4911727B2 (ja) | 2002-12-27 | 2008-10-17 | 半導体装置の製造方法 |
JP2011171781A JP2011216921A (ja) | 2002-12-27 | 2011-08-05 | 半導体装置および半導体装置の製造方法 |
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JP2002379270A JP2004214265A (ja) | 2002-12-27 | 2002-12-27 | 半導体装置および半導体装置の製造方法 |
JP2008268083A JP4911727B2 (ja) | 2002-12-27 | 2008-10-17 | 半導体装置の製造方法 |
JP2011171781A JP2011216921A (ja) | 2002-12-27 | 2011-08-05 | 半導体装置および半導体装置の製造方法 |
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JP2002379270A Division JP2004214265A (ja) | 2002-12-27 | 2002-12-27 | 半導体装置および半導体装置の製造方法 |
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JP2011171781A Division JP2011216921A (ja) | 2002-12-27 | 2011-08-05 | 半導体装置および半導体装置の製造方法 |
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JP2009055055A JP2009055055A (ja) | 2009-03-12 |
JP2009055055A5 JP2009055055A5 (ja) | 2009-04-23 |
JP4911727B2 true JP4911727B2 (ja) | 2012-04-04 |
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JP2002379270A Pending JP2004214265A (ja) | 2002-12-27 | 2002-12-27 | 半導体装置および半導体装置の製造方法 |
JP2008268083A Expired - Lifetime JP4911727B2 (ja) | 2002-12-27 | 2008-10-17 | 半導体装置の製造方法 |
JP2011171781A Pending JP2011216921A (ja) | 2002-12-27 | 2011-08-05 | 半導体装置および半導体装置の製造方法 |
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Cited By (1)
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JP3626075B2 (ja) * | 2000-06-20 | 2005-03-02 | 九州日立マクセル株式会社 | 半導体装置の製造方法 |
JP3498732B2 (ja) * | 2000-06-30 | 2004-02-16 | 日本電気株式会社 | 半導体パッケージ基板及び半導体装置 |
JP2002305378A (ja) * | 2000-07-06 | 2002-10-18 | Sumitomo Bakelite Co Ltd | 多層配線板およびその製造方法ならびに半導体装置 |
JP3546961B2 (ja) * | 2000-10-18 | 2004-07-28 | 日本電気株式会社 | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
JP2002289739A (ja) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
JP2004214265A (ja) * | 2002-12-27 | 2004-07-29 | Kyushu Hitachi Maxell Ltd | 半導体装置および半導体装置の製造方法 |
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2002
- 2002-12-27 JP JP2002379270A patent/JP2004214265A/ja active Pending
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2008
- 2008-10-17 JP JP2008268083A patent/JP4911727B2/ja not_active Expired - Lifetime
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JP2009055055A (ja) * | 2002-12-27 | 2009-03-12 | Kyushu Hitachi Maxell Ltd | 半導体装置の製造方法 |
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