TWI474455B - 先進四方扁平無引腳封裝結構 - Google Patents

先進四方扁平無引腳封裝結構 Download PDF

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Publication number
TWI474455B
TWI474455B TW98119241A TW98119241A TWI474455B TW I474455 B TWI474455 B TW I474455B TW 98119241 A TW98119241 A TW 98119241A TW 98119241 A TW98119241 A TW 98119241A TW I474455 B TWI474455 B TW I474455B
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Taiwan
Prior art keywords
central portion
wafer
package structure
peripheral portion
quad flat
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TW98119241A
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English (en)
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TW201010036A (en
Inventor
Chun Hung Lin
Chien Pao Huei Chang
ping cheng Hu
Wei Lun Cheng
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Advanced Semiconductor Eng
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Publication of TW201010036A publication Critical patent/TW201010036A/zh
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Publication of TWI474455B publication Critical patent/TWI474455B/zh

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Description

先進四方扁平無引腳封裝結構
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種先進四方扁平無引腳(advanced quad flat non-leaded，a-QFN)封裝結構及其製造方法
根據導線架(leadframe)的引腳(lead)的形狀，四方扁平封裝(quad flat package，QFP)可以分為I型(QFI)、J型(QFJ)與無引腳型(QFN)封裝。由於QFN封裝結構具有相對較短的訊號線(signal trace)以及較快的訊號傳輸速率，因此成為一種普遍的具有低腳數(pin count)封裝結構，且適用於具有高頻率(例如，射頻頻寬(radio frequency bandwidth))傳輸的晶片封裝。
一般來說，在QFN封裝結構的製程中，將多個晶片配置於導線架上，且藉由多個焊線(bonding wire)而電性連接至導線架。然後，形成封裝膠體(molding compound)，以包覆導線架、晶片與焊線。最後，藉由切割製程(singulation process)來形成多個QFN封裝結構。
本發明提供一種先進四方扁平無引腳封裝結構及其製造方法，其減少了晶片座(die pad)暴露面積，以降低剝離(delamination)的風險。
為了達成上述目的，本發明提出一種先進四方扁平無引腳封裝結構。此先進四方扁平無引腳封裝結構包括承載器(carrier)、晶片與封裝膠體。承載器具有上表面與相對於上表面的下表面。承載器包括晶片座與多個引腳。晶片座具有中央部分、周邊部分與多個連接部分。周邊部分配置於中央部分周圍。連接部分連接中央部分與周邊部分。連接部分彼此分離。周邊部分、連接部分與中央部分定義出至少二個中空區域(hollow region)。引腳配置於晶片座周圍，其中每一個引腳包括配置於上表面上的內引腳與配置於下表面上的外引腳。晶片配置於承載器的上表面上，且位於晶片座的中央部分中，其中晶片經由多個導線(wire)而電性連接至內引腳。封裝膠體包覆晶片、導線、內引腳與部分承載器。
根據本發明的一實施例，晶片座的周邊部分作為接地環(ground ring)之用，其中晶片座的周邊部分經由導線而電性連接至晶片。
根據本發明的一實施例，承載器更包括至少一個電源環(power ring)，其中電源環配置於引腳與晶片座的周邊部分之間，並經由導線而電性連接至晶片，且電源環與接地環電性絕緣。
根據本發明的一實施例，先進四方扁平無引腳封裝結構更包括黏著層，其配置於晶片與晶片座的中央部分之間。
根據本發明的一實施例，晶片座的中央部分具有多邊形(polygonal)的形狀。
根據本發明的一實施例，周邊部分經由連接部分而與中央部分的至少一側連接。
根據本發明的一實施例，周邊部分經由連接部分而與中央部分的至少一個角落連接。
根據本發明的一實施例，引腳的材料包括金(gold)或鈀(palladium)。
根據本發明的一實施例，任何二個相鄰的引腳之間的距離大於或等於400微米。
根據本發明的一實施例，中央部分的底部表面與周邊部分的底部表面共平面(coplanar)，而中央部分的上表面與周邊部分的上表面不共平面。
根據本發明的一實施例，晶片的邊緣與中央部分的邊緣之間的距離大於或等於300微米。
本發明另提出一種先進四方扁平無引腳封裝結構的製造方法，其包括以下步驟。首先，提供承載器，其中第一圖案化金屬層形成於承載器的上表面上，且第二圖案化金屬層形成於承載器的下表面上。承載器包括至少一個容置凹穴(accommodating cavity)與多個第一開口。然後，提供晶片。晶片配置於容置凹穴的中央部分上，且經由多個導線而電性連接至承載器的第一圖案化金屬層。接著，形成封裝膠體，以包覆晶片、導線、承載器的第一圖案化金屬層，並填滿容置凹穴與第一開口。而後，以第二圖案化金屬層為罩幕，對承載器的下表面進行蝕刻製程，以蝕刻穿過承載器而暴露出填入第一開口中的封裝膠體，且同時 形成多個第二開口與多個第三開口。
根據本發明的一實施例，在蝕刻製程之後，承載器藉由第二開口而定義出多個引腳與晶片座。
根據本發明的一實施例，晶片座藉由第三開口同時定義出中央部分、周邊部分與多個連接部分。
根據本發明的一實施例，在提供晶片之前，更包括於容置凹穴的中央部分上形成黏著層。
綜上所述，根據本發明，承載器的晶片座中具有多個中空區域，且中空區域暴露出封裝膠體。因此，封裝膠體與晶片座的接觸面積可以減少，且由於不同材料之間的不均勻應力所導致的封裝膠體與晶片座之間的剝離問題可以減輕。另一方面，位於晶片座的中央部分上的晶片可以被封裝膠體包覆且保護。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A為根據本發明的一實施例所繪示的先進四方扁平無引腳封裝結構的底部示意圖。圖1B為沿圖1A中的I-I’剖面所繪示的剖面示意圖。圖1C為沿圖1A中的II-II’剖面所繪示的剖面示意圖。請同時參照圖1A、圖1B與圖1C，在本實施例中，先進四方扁平無引腳(a-QFN)封裝結構100包括承載器200、晶片300與封裝膠體500。
在本實施例中，承載器200例如為導線架。詳細地說， 承載器200具有上表面210a與相對於上表面210a的下表面210b。承載器200包括晶片座220與多個引腳230，其中晶片座220具有中央部分222、周邊部分224與多個連接部分226。在圖1A中，繪示出四個連接部分226。然而，晶片座220可以包括一個或多個連接部分226，且連接部分226的數目在此並不限定。周邊部分224圍繞中央部分222。連接部分226連接中央部分222與周邊部分224。由於連接部分226彼此分離，因此周邊部分224、連接部分226與中央部分222定義出了四個中空區域S。中空區域S的數目在此並不限定，但藉由承載器200中連接部分226的數目來決定。
詳細地說，在本實施例中，晶片座220的中央部分222具有矩形的形狀。中央部分222的底部表面222b與周邊部分224的底部表面224b共平面，而中央部分222的上表面222a與周邊部分224的上表面224a不共平面。如圖1C所示，周邊部分224的上表面224a高於中央部分222的上表面222a。然而，晶片座220的中央部分222可以是多邊形的形狀。連接部分226配置於中央部分222的一側或角落。特別是，在本實施例中，連接部分226連接中央部分222的四側與周邊部分224。值得注意的事，連接部分226的位置、排列或數量可以依據封膠製程(molding process)的需求而調整。在本發明的另一實施例中，晶片座220僅具有二個連接部分226，且周邊部分224經由連接部分226而連接至中央部分222的二個角落，如圖2所示。
請參照圖1A與圖1B，引腳230配置於晶片座220周圍， 其中每一個引腳230包括內引腳232與外引腳234。舉例來說，引腳230可以沿著晶片座220的二側來配置，或配置於晶片座220的周圍。引腳230的配置方式例如是陣列(array)、多行或多列，或配置成環狀。引腳230的配置方式可以依據客戶需求或產品需求而客製化(customized)。引腳230的材料例如為金或鈀。
此外，任何二個相鄰的引腳230之間的距離大於或等於400微米。
晶片300配置於晶片座220的中央部分222，且位於承載器200的上表面210a上。晶片300經由多個導線400而電性連接至內引腳232與周邊部分224。此外，晶片300的邊緣與中央部分222的邊緣之間的距離d大於或等於300微米。
封裝膠體500包覆晶片300、導線400、內引腳232、一部分的晶片座220。換句話說，外引腳234與晶片座220的底部表面未被封裝膠體500覆蓋。此外，晶片座220的中空區域S與引腳230之間的間隙暴露出封裝膠體500。由於晶片座220的中空區域S，因此封裝膠體500與晶片座220之間的剝離現象可以減少。封裝膠體500的材料例如為環氧樹脂(epoxy resin)或其他可應用的聚合物材料(polymer material)。
此外，在本實施例中，在a-QFN封裝結構100中，晶片座220的周邊部分224例如可以作為接地環之用。另外，承載器200還可以包括至少一個電源環240。電源環240配置於引腳230與晶片座220的周邊部分224之間，且經由導線400 而電性連接至晶片300。電源環240與接地環224電性絕緣。
再者，在本實施例中，a-QFN封裝結構100更包括黏著層600。黏著層600配置於晶片300與晶片座220的中央部分222之間，以將晶片300固定於中央部分222。
簡言之，在本發明的實施例中，a-QFN封裝結構100/100a具有至少二個位於晶片座220的周邊部分224與中央部分222之間的中空區域S，且中空區域S暴露出封裝膠體500。因此，可以減少由於金屬氧化或不均勻應力所導致的封裝膠體500與晶片座220之間的剝離問題。
以下將以圖3A至圖3I來說明本發明的a-QFN封裝結構100的製作流程。
圖3A至圖3I為根據本發明的一實施例所繪示的先進四方扁平無引腳封裝結構的製造流程剖面圖，其中圖3H的次圖(a)為沿圖1A中的I-I’剖面所繪示的剖面示意圖，而圖3H的次圖(b)為沿圖1A中的II-II’剖面所繪示的剖面示意圖。為了方便說明，在本實施例中將省略電源環。
首先，請參照圖3A，提供具有上表面210a與下表面210b的基底210。基底210的材料例如為銅、銅合金或其他可應用的金屬材料。然後，於基底210的上表面210a上形成第一圖案化光阻層214a，且於基底210的下表面212b上形成第二圖案化光阻層214b。
然後，請參照圖3B，於暴露出來的基底210的上表面210a上形成第一金屬層216a，且於暴露出來的基底210的下表面210b上形成第二金屬層216b。在本實施例中，形成第 一金屬層216a與第二金屬層216b的方法例如為電鍍(plating)。
接著，請參照圖3C，移除第一圖案化光阻層214a，以於基底210的上表面210a上形成第一圖案化金屬層218a。
而後，請參照圖3D，以第一圖案化金屬層218a作為蝕刻罩幕，進行蝕刻製程來移除一部分的基底210，以形成至少一個容置凹穴220a與多個第一開口S1。然後，移除第二圖案化光阻層214b，以於基底210的下表面210b上形成第二圖案化金屬層218b。藉由第一開口S1而彼此分離的第一圖案化金屬層218a將在後續步驟中形成內引腳232。第一圖案化金屬層218a的圖案與第二圖案化金屬層218b的圖案不相同或不對稱。在此階段，約略形成了承載器200。
繼之，請參照圖3E，將晶片300提供至每一個容置凹穴220a的中央部分222，且於晶片300與容置凹穴220a的中央部分222之間形成黏著層600。配置於晶片300與容置凹穴220a的中央部分222之間的黏著層600有助於將晶片300固定於中央部分222。
隨後，請參照圖3F，經由導線400將晶片300電性連接至即將形成的內引腳232。
然後，請參照3G，形成封裝膠體500，以包覆晶片300、導線400、即將形成的內引腳232，且填入容置凹穴220a與第一開口S1。
之後，請參照圖3H(a)與圖3H(b)，以第二圖案化金屬層218b作為罩幕，對暴露出來的承載器200的下表面 210b(如圖3G所示)進行蝕刻製程，以蝕刻穿過暴露的基底210(例如，導線架)。因此，第一開口S1中的封裝膠體500被暴露出來，且同時形成了多個第二開口S2與多個第三開口S3。
特別地，由於第二開口S2的形成，基底210被蝕刻穿，且定義出了內引腳232與外引腳234。內引腳232藉由第一開口S1而彼此物理分離與電性分離。外引腳234藉由第二開口S2而彼此物理分離與電性分離。第三開口S3定義容置凹穴220a中的基底210，以形成具有中央部分222、圍繞中央部分222的周邊部分224與多個連接部分226的晶片座220。連接部分226藉由第三開口S3而彼此分離。
詳細地說，晶片座220的中央部分222被周邊部分224圍繞，且連接部分226連接中央部分222與周邊部分224。如圖1C所示，中央部分222的底部表面222b與周邊部分224的底部表面224b以及連接部分226的底部表面226b共平面，且中央部分222的上表面222a與連接部分226的上表面226a共平面，但是不與周邊部分224的上表面224a共平面。晶片300的邊緣與中央部分222的邊緣之間的距離大於或等於300微米。
之後，請參照圖3I，藉由鋸開製程(sawing process)來進行切割製程。切割製程還可以包括衝壓製程(punch process)。切割的目的在於完全切斷承載器200與封裝膠體500，以得到多個a-QFN封裝結構100。在圖3I中，僅繪示出二個a-QFN封裝結構100。
簡言之，藉由對基底的下表面進行蝕刻製程來同時形成第二開口與第三開口，而封裝膠體經由第二開口與第三開口而被暴露出來。此外，由於開口的形成，導線架(晶片座)與封裝膠體之間的接觸面積可以減小，因此可以避免剝離的問題，以及增進製程品質與產品良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100a‧‧‧先進四方扁平無引腳封裝結構
200‧‧‧承載器
210a、222a、224a、226a‧‧‧上表面
210b、212b‧‧‧下表面
214a‧‧‧第一圖案化光阻層
214b‧‧‧第二圖案化光阻層
216a‧‧‧第一金屬層
216b‧‧‧第二金屬層
218a‧‧‧第一圖案化金屬層
218b‧‧‧第二圖案化金屬層
220‧‧‧晶片座
220a‧‧‧容置凹穴
222‧‧‧中央部分
224‧‧‧周邊部分
224b、222b、226b‧‧‧底部表面
226‧‧‧連接部分
230‧‧‧引腳
232‧‧‧內引腳
234‧‧‧外引腳
240‧‧‧電源環
300‧‧‧晶片
400‧‧‧導線
500‧‧‧封裝膠體
600‧‧‧黏著層
d‧‧‧距離
S‧‧‧中空區域
S1‧‧‧第一開口
S2‧‧‧第二開口
S3‧‧‧第三開口
圖1A為根據本發明的一實施例所繪示的先進四方扁平無引腳封裝結構的底部示意圖。
圖1B為沿圖1A中的I-I’剖面所繪示的剖面示意圖。
圖1C為沿圖1A中的II-II’剖面所繪示的剖面示意圖。
圖2為根據本發明的另一實施例所繪示的先進四方扁平無引腳封裝結構的底部示意圖。
圖3A至圖3I為根據本發明的一實施例所繪示的先進四方扁平無引腳封裝結構的製造流程剖面圖，其中圖3H的次圖(a)為沿圖1A中的I-I’剖面所繪示的剖面示意圖，而圖3H的次圖(b)為沿圖1A中的II-II’剖面所繪示的剖面示意圖。
100‧‧‧先進四方扁平無引腳封裝結構
200‧‧‧承載器
210a、222a、224a、226a‧‧‧上表面
210b、222b‧‧‧下表面
220‧‧‧晶片座
220a‧‧‧容置凹穴
222‧‧‧中央部分
224‧‧‧周邊部分
224b、226b‧‧‧底部表面
226‧‧‧連接部分
230‧‧‧引腳
232‧‧‧內引腳
234‧‧‧外引腳
240‧‧‧電源環
300‧‧‧晶片
400‧‧‧導線
500‧‧‧封裝膠體
600‧‧‧黏著層
d‧‧‧距離

Claims (11)

  1. 一種先進四方扁平無引腳封裝結構，包括：一承載器，具有一上表面與一下表面，其中該承載器包括：一晶片座，具有一中央部分、一周邊部分與多個連接部分，其中該周邊部分環繞該中央部分，而該些連接部分連接該中央部分與該周邊部分，該些連接部分彼此分離，且該中央部分、該周邊部分與該些連接部分定義出至少二中空區域；以及多個引腳，配置於該晶片座周圍，其中每一引腳包括配置於該上表面上的一內引腳與配置於該下表面上的一外引腳；一晶片，配置於該承載器的該上表面上，且位於該晶片座的該中央部分，其中該晶片經由多個導線而電性連接至該些內引腳；以及一封裝膠體，包覆該晶片、該些導線、該些內引腳與部份該承載器，其中該至少二中空區域暴露出該封裝膠體的一底表面，且部分該周邊部分突出於該封裝膠體的該底表面。
  2. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該晶片座的該周邊部分作為一接地環，其中該晶片座的該周邊部分經由該些導線而電性連接至該晶片。
  3. 如申請專利範圍第2項所述之先進四方扁平無引腳 封裝結構，其中該承載器更包括至少一電源環，其中電源環配置於該些引腳與該晶片座的該周邊部分之間，且經由該些導線而電性連接至該晶片，且該至少一電源環與該接地環電性絕緣。
  4. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，更包括一黏著層，配置於該晶片與該晶片座的該中央部分之間。
  5. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該晶片座的該中央部分具有多邊形的形狀。
  6. 如申請專利範圍第5項所述之先進四方扁平無引腳封裝結構，其中該周邊部分經由該些連接部分而連接至該中央部分的至少一側。
  7. 如申請專利範圍第5項所述之先進四方扁平無引腳封裝結構，其中該周邊部分經由該些連接部分而連接至該中央部分的至少一角落。
  8. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該些引腳的材料包括金或鈀。
  9. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中任何二個相鄰的該些引腳之間的距離大於或等於400微米。
  10. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該中央部分的底部表面與該周邊部分的底部表面共平面，而該中央部分的上表面與該周邊部分的 上表面不共平面。
  11. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構，其中該晶片的邊緣與該中央部分的邊緣之間的距離大於或等於300微米。
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