TWI485828B - 先進四方扁平無引腳封裝結構及其製造方法 - Google Patents

先進四方扁平無引腳封裝結構及其製造方法 Download PDF

Info

Publication number
TWI485828B
TWI485828B TW099143376A TW99143376A TWI485828B TW I485828 B TWI485828 B TW I485828B TW 099143376 A TW099143376 A TW 099143376A TW 99143376 A TW99143376 A TW 99143376A TW I485828 B TWI485828 B TW I485828B
Authority
TW
Taiwan
Prior art keywords
metal layer
substrate
protective layer
package structure
wafer
Prior art date
Application number
TW099143376A
Other languages
English (en)
Other versions
TW201220452A (en
Inventor
Chien Pao Huei Chang
ping cheng Hu
Po Shing Chiang
Wei Lun Cheng
Hsueh Te Wang
Hsiao Chuan Chang
Tsung Yueh Tsai
Yi Shao Lai
Ping Feng Yang
Original Assignee
Advanced Semiconductor Eng
Mediatek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng, Mediatek Inc filed Critical Advanced Semiconductor Eng
Publication of TW201220452A publication Critical patent/TW201220452A/zh
Application granted granted Critical
Publication of TWI485828B publication Critical patent/TWI485828B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

先進四方扁平無引腳封裝結構及其製造方法
本發明大體而言是有關於一種封裝結構及其製造方法,且特別是有關於一種先進四方扁平無引腳(advanced quad flat non-leaded,a-QFN)封裝結構及其製造方法。
四方扁平封裝(quad flat package,QFP)家族包括I型(QFI)、J型(QFJ)及無引腳型(QFN)封裝,其特徵在於導線架(leadframe)之引線的形狀。其中,QFN封裝結構可提供多種優點,包括引線電感減小、佔用面積(footprint)尺寸小、更薄且信號傳輸速度更快。因此,QFN封裝已成為一種流行之封裝結構選項,並且適用於具有高頻(例如,射頻頻寬)傳輸之晶片封裝。
對於QFN封裝結構,晶粒座(die pad)及其周圍之接觸端(引腳焊墊)是由平面狀導線架基板製成。QFN封裝結構一般藉由表面黏著技術(surface mounting technology,SMT)而焊接至印刷電路板(printed circuit board,PCB)。因此,QFN封裝結構之接觸端/焊墊需要被設計成很好地適合於封裝製程能力並能促進良好之長期接合可靠性。
本發明是有關於一種先進四方扁平無引腳封裝及其製造方法,其可幫助減輕引腳脫落問題並增強產品可靠性。
本發明提供一種先進四方扁平無引腳封裝結構,該先進四方扁平無引腳封裝結構具有一載體、一設置於該載體上的晶片、多個導線及一封裝膠體。該載體包括一晶粒座及多個引腳,且該些引腳包括多個內引腳及由該封裝膠體暴露出之多個外引腳。至少一個內引腳包括一金屬層及一保護層,該保護層覆蓋其下該金屬層之邊緣及側壁之至少一部分。此外,至少一個內引腳具有內彎側壁,該些內彎側壁能夠增強內引腳與周圍封裝膠體間之黏附性。該些導線設置於該晶片與該些內引腳之間。該封裝膠體用於封裝該晶片、該些導線及該些內引腳。
根據本發明之實施例,內引腳之側壁可被設計成內彎的或彎曲的,以提昇內引腳與周圍封裝膠體之鎖定(locking)或楔合(wedging)能力。
本發明更提供一種製造一先進四方扁平無引腳封裝結構之方法。在提供具有一上表面及一下表面之一基板後,於該基板之上表面及下表面上分別形成一第一金屬層及一第二金屬層,並對基板之上表面執行一第一蝕刻製程。隨後,於第一金屬層上形成一保護層,以覆蓋該第一金屬層之至少邊緣及側壁。使用該保護層及該第一金屬層作為一遮罩,對該基板之上表面執行一第二蝕刻製程,以形成一容置空腔及多個開口並定義出多個內引腳。該些內引腳具有內彎側壁。在提供一晶片至該基板之容置空腔並於晶片與內引腳之間形成多個導線後,於基板上形成一封裝膠體,以封裝該晶片、該些導線、該些內引腳並填充該容置空腔以及該些內引腳間之開口。之後,可使用第二金屬層作為一蝕刻遮罩來執行一第三蝕刻製程,以對基板進行穿透蝕刻,直至暴露出填充於該些開口內之封裝膠體,藉此形成多個引腳及一晶粒座。
根據本發明之實施例,可藉由以下方式製成內引腳:形成保護層部分地或完全地覆蓋其下第一金屬層,並使用保護層及第一金屬層二者作為遮罩將基板圖案化。因此,利用在蝕刻期間出現之底切,所獲得之內引腳具有內彎側壁,此會增大內引腳與封裝膠體間之接觸面積。
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。
現在,將詳細參照本發明之較佳實施例,此等較佳實施例之範例繪示於附圖中。在附圖及說明中,將盡可能使用相同之參考編號來表示相同或相似之部件。
圖1A至圖1J是依照本發明之一實施例所繪示的一種製造先進四方扁平無引腳封裝結構之方法的示意性剖視圖。
如圖1A所示,提供基板110,基板110具有上表面110a及下表面110b。舉例而言,基板110之材料可為銅、銅合金或其他適用之金屬材料。接下來,仍參見圖1A,於基板110之上表面110a上形成第一圖案化光阻層(photoresist layer)114a,並於基板110之下表面110b上形成第二圖案化光阻層114b。
接下來,參見圖1B,使用第一光阻層114a/第二光阻層114b作為遮罩(mask),於基板110之上表面110a之暴露部分上形成第一金屬層116a,並於基板110之下表面110b之暴露部分上形成第二金屬層116b。在本實施例中,第一金屬層116a及第二金屬層116b可藉由例如鍍覆(plating)而形成。端視第一圖案化光阻層114a或第二圖案化光阻層114b之圖案設計而定,本文所述之第一金屬層116a或第二金屬層116b可由各種不相連圖案之群組或由一連續層構成。舉例而言,第一金屬層116a可為一鎳金疊層(Ni/Au layer)。
如圖1B所示,第一金屬層116a包括多個第一金屬部115a及至少一第二金屬部115b。第一金屬部115a隨後將被形成為內引腳130(如圖1F所示),而第二金屬部115b隨後將被形成為晶粒座120之接地環124(如圖1I所示)。類似地,第二金屬層116b包括多個第三金屬部117a及至少一第四金屬部117b。第三金屬部117a對應於隨後所將形成之外引腳136(如圖1I所示),而第四金屬部117b則對應於隨後所將形成之晶粒座120。
接下來,參見圖1C,移除第一光阻層114a。然後,藉由使用第一金屬層116a作為蝕刻遮罩,對基板110之上表面110a執行一第一蝕刻製程(例如等向性蝕刻製程),以移除基板110之部分並形成至少一第一空腔120a及多個第一開口S1。舉例而言,該第一蝕刻製程為濕蝕刻製程(wet etching process)。因第一蝕刻製程為等向性蝕刻製程,故可輕易地在第一金屬層116a之下形成底切(undercut)。因而,如圖1D所示,執行水刀(water-jet)製程,以切除或移除位於底切正上方的第一金屬層116a之部分。
接著,參見圖1E或圖1E' ,形成保護層118,以至少覆蓋第一金屬部115a及第二金屬部115b之邊緣及側壁。圖1E' 顯示圖1E所示a-QFN封裝結構之一範例部分的放大剖視圖。舉例而言,保護層118可藉由以下方式形成:塗覆一填充材料(圖未示出)至第一空腔120a及第一開口S1,然後於第一金屬層116a上鍍覆一金屬層(圖未示出)。另一選擇為,圖1E' 中之保護層118不僅覆蓋(即保護)第一金屬部115a及第二金屬部115b之邊緣115e及側壁115d,且亦覆蓋第一金屬部115a及第二金屬部115b之頂面115c。舉例而言,保護層118之材料可為金或任何適宜之耐蝕刻性金屬材料。
接著,參見圖1F或圖1F' ,藉由使用保護層118以及第一金屬層116a作為蝕刻遮罩,對基板110之上表面110a執行第二等向性蝕刻製程,以移除基板110之部分。因存在保護層118,故在第二蝕刻製程中,第一金屬層116a之側壁受到保護。在此種情形中,第一金屬層116a之圖案(或開口)不會被改變,但下面之開口會變寬和變深。圖1F' 顯示圖1F所示a-QFN封裝結構之一範例部分之放大剖視圖。第一空腔120a更被蝕刻成容置空腔120a' ,而第一開口S1更被蝕刻成更深之第一開口S1' 。藉由該些開口S1' 之定義,形成多個單個之內引腳130。舉例而言,第一開口S1與第一開口S1' 之深度比可介於1:3至1:4範圍內。因第二蝕刻製程是等向性蝕刻製程,故第一開口S1’之側面輪廓變寬,且可輕易地在保護層118與第一金屬層116a之下形成底切。在此種情形中,第一開口S1' 之側壁Ss是外彎的(與第一蝕刻製程後之開口側壁相比,向外彎曲),且外彎距離「d」可例如為約0.5微米大。相反,內引腳130之側壁S是內彎的(與第一蝕刻製程後之內引腳側壁相比,向內彎曲),且內彎距離「d」(自第一金屬層之側壁至內引腳之最內側壁之水平距離)可例如為約0.5微米大。換言之,內引腳130在中間具有狹窄部(即頸部)。
如在實施例中所述,內引腳130利用形成底切來增強或最佳化內引腳對後續形成之封裝膠體的鎖定能力。因此,可精細地調節第二蝕刻製程之蝕刻率(etching rate)及選擇性,以獲得最佳之效能,藉此控制開口之尺寸或輪廓並最佳化引腳圖案之形狀。
至此,在形成第一金屬層116a及第二金屬層116b並將基板110圖案化之後,已大致形成載體100。容置空腔120a' 具有中央部122及圍繞中央部122設置之周邊部124。內引腳130是圍繞周邊部124設置但與周邊部124間隔開。內引腳130可排列成列、行或陣列。周邊部124可用作接地環。
接下來,參見圖1G,在至少一晶片150與容置空腔120a' 之中央部122之間使用一黏合層140將該至少一晶片150附著至容置空腔120a' 之中央部122。隨後,在晶片150、接地環124及內引腳130之間提供多個導線160。換言之,經由導線160將晶片150電性連接至接地環124及內引腳130。
接下來,參見圖1H,形成封裝膠體180,以封裝晶片150、導線160、內引腳130、接地環124及填充容置空腔120a' 及第一開口S1'
然後,參見圖1I,使用第二金屬層116b作為蝕刻遮罩,對載體100之下表面110b執行第三蝕刻製程,以移除基板110之一部分,俾對載體100進行穿透蝕刻(etched through)而暴露出填充於第一開口S1' 內之封裝膠體180並同時形成多個第二開口S2。由於第二開口S2之形成,定義出多個外引腳136且各內引腳130被相互電性隔離。亦即,在第三蝕刻製程後,形成多個引腳或接觸端138,各該些引腳或接觸端138分別由一個內引腳130與對應之外引腳136組成。此外,第三蝕刻製程更定義出載體100之至少一晶粒座120。晶粒座120被引腳138環繞並藉由第二開口S2而與引腳138隔離。總之,引腳138藉由此蝕刻製程而相互電性隔離。
接著,參見圖1J,執行切單製程(singulation process),俾獲得單個之a-QFN封裝結構10。
詳言之,在本實施例中,在第二蝕刻製程中,保護層118保護第一圖案化金屬層116a之至少邊緣及側壁(圖1F或圖1F' ),在第一金屬層116a之下形成變寬之開口S1' 且開口S1' 之側壁外彎(因底切所致)。因此,由於內引腳130(具有內彎之側壁)與周圍封裝膠體180間之接觸面積增大,故內引腳130與周圍封裝膠體180間之結合可得到增強,俾使接觸端180在表面黏著製程或其他後續製程中不會脫落,並可大幅提高產品可靠性。對於本實施例中之a-QFN封裝結構10,可減輕接觸端138之脫落問題且接觸端(或引腳)之合型能力(mold locking capability)可得到增強。
圖2是依照本發明之一實施例所繪示的一種先進四方扁平無引腳(a-QFN)封裝結構的示意性剖視圖,同時在右側以放大之3D視圖顯示a-QFN封裝結構的其中之一內引腳。參見圖2,在本實施例中,先進四方扁平無引腳(a-QFN)封裝結構20包括載體200、晶片250、多個導線260及封裝膠體280。
本實施例中之載體200為例如導線架。詳言之,載體200包括晶粒座220及多個引腳(接觸端)238。引腳238包括多個內引腳230及多個外引腳236。在圖2中,示意性地繪示三行/列接觸端238。具體而言,引腳238圍繞晶粒座220設置,且引腳238之材料可例如包括鎳、金、鈀或其一組合。內引腳與外引腳是由封裝膠體限定;亦即,引腳被封裝膠體封裝的部分定義為內引腳,而外引腳則為引腳暴露於封裝膠體外的部分。
此外,載體200之晶粒座220更包括至少一接地環224。接地環224經由導線260而電性連接至晶片250。由於接地環224連接至晶粒座220,故晶粒座與接地環一起可用作接地層(ground plane)。應注意者,圖2中所示引線238相對於接地環224及晶粒座220之位置、佈置方式及數量僅為範例性的,而不應被視為用於限制本發明。
更詳言之,如右側之三維放大視圖所示,本實施例中之內引腳230具有保護層218,保護層218覆蓋金屬層216a之至少邊緣及側壁。然而,保護層218可例如為環形的(僅覆蓋邊緣及側壁)或帽子形的(覆蓋金屬層216a之頂面及側壁)。在本實施例中,內引腳230及/或保護層218之佈置方式或形狀僅為範例性的。
在圖2中,為強調第一開口S1' 與第二開口S2之輪廓或外形之間的區別,外引腳236被範例性地繪示為具有垂直側壁,而內引腳230被範例性地繪示為具有彎曲之側壁。然而,應理解,外引腳236不必一定具有垂直側壁。因存在保護層,發生於金屬層下面之底切會使內引腳具有更為內彎之側壁,此會顯著增強引腳與封裝膠體間之結合。
另外,本實施例中a-QFN封裝結構20之封裝膠體280用於封裝晶片250、導線260及內引腳230並填充內引腳230之間的間隙,而外引腳236及晶粒座220之底面則暴露。舉例而言,封裝膠體280之材料為環氧樹脂(epoxy resin)或其他適用之聚合物材料。
圖3A至圖3J是依照本發明之另一實施例所繪示的一種製造先進四方扁平無引腳封裝結構之方法的示意性剖視圖。
如圖3A所示,提供基板310,基板310具有上表面310a及下表面310b。舉例而言,基板310之材料可為銅、銅合金或其他適用之金屬材料。接下來,仍參見圖3A,於基板310之上表面310a上形成第一圖案化光阻層314a,並於基板310之下表面310b上形成第二圖案化光阻層314b。
接下來,參見圖3B,使用第一光阻層314a/第二光阻層314b作為遮罩,於基板310之上表面310a之暴露部分上形成第一金屬層316a,並於基板310之下表面310b之暴露部分上形成第二金屬層316b。在本實施例中,第一金屬層316a及第二金屬層316b可藉由例如鍍覆而形成。端視第一圖案化光阻層314a或第二圖案化光阻層314b之圖案設計而定,本文所述之第一金屬層316a或第二金屬層316b可由各種不相連圖案之群組或由一連續層構成。舉例而言,第一金屬層316a可為一鎳金疊層(Ni/Au layer)。
如圖3B所示,第一金屬層316a包括多個第一金屬部315a及至少一第二金屬部315b。第一金屬部315a隨後將被形成為內引腳330(如圖3F所示),而第二金屬部315b隨後將被形成為晶粒座320之接地環324(如圖3I所示)。類似地,第二金屬層316b包括多個第三金屬部317a及至少一第四金屬部317b。第三金屬部317a對應於隨後所將形成之外引腳336(如圖3I所示),而第四金屬部317b則對應於隨後所將形成之晶粒座320。
接下來,參見圖3C,移除第一光阻層314a及第二光阻層314b。然後,藉由使用第一金屬層316a作為蝕刻遮罩,對基板310之上表面310a執行一第一蝕刻製程(例如等向性蝕刻製程),以移除基板310之部分並形成至少一第一空腔320a及多個第一開口S3。舉例而言,該第一蝕刻製程為濕蝕刻製程。因第一蝕刻製程為等向性蝕刻製程,故可輕易地在第一金屬層316a之下形成底切。因而,如圖3D所示,執行水刀製程,以切除或移除位於底切正上方的第一金屬層316a之部分。
接著,參見圖3E或圖3E' ,形成保護層318,以覆蓋第一金屬部315a及第二金屬部315b並局部地覆蓋第一開口S3之上部側壁。圖3E' 顯示圖3E所示a-QFN封裝結構之一範例部分的放大剖視圖。舉例而言,保護層318可藉由以下方式形成:塗覆一填充材料(圖未示出)至第一空腔320a及第一開口S3,然後於第一金屬層316a上鍍覆一金屬材料層(圖未示出)。圖3E' 中之保護層318不僅覆蓋(即保護)第一金屬部315a及第二金屬部315b之頂面315c及側壁315d,且亦局部地覆蓋第一開口S3之側壁表面S3a(及空腔320a之側壁)。在本文中,當出現底切時,開口S3之側壁S3a為彎曲的。舉例而言,保護層318之材料可為金或任何適宜之耐蝕刻性金屬材料。
接著,參見圖3F或圖3F' ,藉由使用保護層318以及第一金屬層316a作為蝕刻遮罩,對基板310之上表面310a執行第二蝕刻製程,以移除基板310之部分。因存在保護層318,故在第二蝕刻製程中,第一金屬層316a之側壁及開口側壁S3a之一部分受到保護。在此種情形中,第一金屬層316a之圖案不會被改變,但下面之開口會變深。圖3F' 顯示圖3F所示a-QFN封裝結構之一範例部分之放大剖視圖。第一空腔320a更被向下蝕刻而形成容置空腔320a' 。類似地,第一開口S3更被向下蝕刻而形成更深之第一開口S3' 。藉由該些開口S3' 之定義,形成多個單個之內引腳330。舉例而言,第一蝕刻製程與第二蝕刻製程之深度比可介於1:1至1:2範圍內。舉例而言,第二蝕刻製程是等向性蝕刻製程。因第一開口S3及第一空腔320a之側壁至少部分地受到保護,故主要對第一開口S3及第一空腔320a之底部執行蝕刻。在此種情形中,由於兩個蝕刻製程,內引腳330具有上部內彎(向內彎曲)側壁S3a及下部內彎側壁S3b。換言之,內引腳330看起來像兩個堆疊於一起之梯形棱柱,其中在中間具有突出之帶狀部(圖4)。
如在實施例中所述,內引腳330利用由兩個蝕刻製程形成底切來增強或最佳化內引腳對後續形成之封裝膠體的鎖定能力。因此,可精細地調節第一蝕刻製程/第二蝕刻製程之蝕刻率及選擇性,以獲得最佳之效能,藉此控制開口之尺寸或輪廓並最佳化引腳圖案之形狀。
至此,在形成第一金屬層316a及第二金屬層316b並將基板310圖案化之後,已大致形成載體300。容置空腔320a’具有中央部322及圍繞中央部322設置之周邊部324。內引腳330是圍繞周邊部324設置但與周邊部324間隔開。內引腳330可排列成列、行或陣列。周邊部324可用作接地環。
接下來,參見圖3G,在至少一晶片350與容置空腔320a' 之中央部322之間使用一黏合層340將該至少一晶片350附著至容置空腔320a' 之中央部322。隨後,在晶片350、接地環324及內引腳330之間提供多個導線360。換言之,經由導線360將晶片350電性連接至接地環324及內引腳330。
接下來,參見圖3H,形成封裝膠體380,以封裝晶片350、導線360、內引腳330、接地環324及填充容置空腔320a' 及第一開口S3'
然後,參見圖3I,使用第二金屬層316b作為蝕刻遮罩,對載體300之下表面310b執行第三蝕刻製程,以移除基板310之一部分,俾對載體300進行穿透蝕刻而暴露出填充於第一開口S3' 內之封裝膠體380並同時形成多個第二開口S4。由於第二開口S4之形成,定義出多個獨立外引腳336且各內引腳330相互電性隔離。亦即,在第三蝕刻製程後,形成多個引腳或接觸端318,各該些引腳或接觸端318分別由一個內引腳330與對應之外引腳336組成。此外,第三蝕刻製程更定義出載體300之至少一晶粒座320。晶粒座320被引腳318環繞並藉由第二開口S4而與引腳318隔離。總之,引腳318藉由此蝕刻製程而相互電性隔離。
接著,參見圖3J,執行切單製程,俾獲得單個之a-QFN封裝結構30。
圖4是依照本發明之另一實施例所繪示的一種先進四方扁平無引腳(a-QFN)封裝結構的示意性剖視圖,同時在右側以放大之3D視圖顯示a-QFN封裝結構的其中之一內引腳。參見圖4,在本實施例中,先進四方扁平無引腳(a-QFN)封裝結構40包括載體400、晶片450、多個導線460及封裝膠體480。
本實施例中之載體400為例如導線架。詳言之,載體400包括晶粒座420及多個引腳(接觸端)438。引腳438包括多個內引腳430及多個外引腳436,而該些內引腳及該些外引腳是由封裝膠體定義。
此外,載體400之晶粒座420更包括至少一接地環424。由於接地環424電性連接至晶粒座420,故晶粒座與接地環一起可用作接地層。應注意者,圖4中所示引線438相對於接地環424及晶粒座420之位置、佈置方式及數量僅為範例性的,而不應被視為用於限制本發明。
更詳言之,如右側之三維放大視圖所示,本實施例中之內引腳430具有帽子形的保護層418,保護層418覆蓋金屬層416a之至少頂面及側壁以及上部側壁S3a之一部分。在本實施例中,內引腳430及/或保護層418之佈置方式或形狀僅為範例性的。
在圖4中,為強調具有底切之開口之輪廓或外形,內引腳430及外引腳436被範例性地繪示為具有彎曲之側壁。因存在保護層,發生於金屬層下面之底切會使內引腳具有更為內彎之側壁,此會顯著增強引腳與封裝膠體間之結合。
另外,本實施例中a-QFN封裝結構40之封裝膠體480用於封裝晶片450、導線460及內引腳430並填充內引腳430之間的間隙,而外引腳436及晶粒座420之底面則暴露。舉例而言,封裝膠體480之材料為環氧樹脂或其他適用之聚合物材料。
對於根據上述實施例之a-QFN封裝結構,內引腳是藉由至少兩個蝕刻製程而製成,且後一蝕刻製程可於模製製程之前精調內引腳側壁之輪廓。此外,由於在蝕刻製程期間,內引腳部分上之金屬層至少部分地被保護層覆蓋,故對金屬層之損傷減小。所述實施例中之a-QFN封裝結構被設計成具有更佳之鎖定能力(即內引腳與封裝膠體間之黏附性更強),進而解決脫落問題並提高產品可靠性。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...a-QFN封裝結構
20...a-QFN封裝結構
30...a-QFN封裝結構
40...a-QFN封裝結構
100...載體
110...基板
110a...上表面
110b...下表面
114a...第一圖案化光阻層
114b...第二圖案化光阻層
115a...第一金屬部
115b...第二金屬部
115c...頂面
115d...側壁
115e...邊緣
116a...第一金屬層
116b...第二金屬層
117a...第三金屬部
117b...第四金屬部
118...保護層
120...晶粒座
120a...第一空腔
120a' ...容置空腔
122...中央部
124...接地環
130...內引腳
136...外引腳
138...引腳或接觸端
140...黏合層
150...晶片
160...導線
180...封裝膠體
200...載體
216a...金屬層
218...保護層
220...晶粒座
224...接地環
230...內引腳
236...外引腳
238...引腳(接觸端)
250...晶片
260...導線
280...封裝膠體
300...載體
310...基板
310a...上表面
310b...下表面
314a...第一圖案化光阻層
314b...第二圖案化光阻層
315a...第一金屬部
315b...第二金屬部
315c...頂面
315d...側壁
316a...第一金屬層
316b...第二金屬層
317a...第三金屬部
317b...第四金屬部
318...保護層
320...晶粒座
320a...第一空腔
320a' ...容置空腔
322...中央部
324...接地環
330...內引腳
336...外引腳
340...黏合層
350...晶片
360...導線
380...封裝膠體
400...載體
416a...金屬層
418...保護層
420...晶粒座
424...接地環
430...內引腳
436...外引腳
438...引腳(接觸端)
450...晶片
460...導線
480...封裝膠體
d...距離
Ss...第一開口S1' 之側壁
S1...第一開口
S1' ...更深之第一開口
S2...第二開口
S3...第一開口
S3' ...更深之第一開口
S3a...側壁表面/上部內彎側壁
S3b...下部內彎側壁
S4...第二開口
為達成對本發明之進一步理解,本說明包含附圖,該些附圖包含於本說明書中並構成本說明書之一部分。該些附圖繪示本發明之實施例並與本說明一起用於解釋本發明之原理。
圖1A至圖1J是依照本發明之一實施例所繪示的一種製造先進四方扁平無引腳(a-QFN)封裝結構之方法的示意性剖視圖。
圖1E' 至圖1F' 顯示圖1E至圖1F所示a-QFN封裝結構之一範例部分之示意性剖視圖。
圖2是依照本發明之一實施例所繪示的一種先進四方扁平無引腳(a-QFN)封裝結構的示意性剖視圖。
圖3A至圖3J是依照本發明之另一實施例所繪示的一種製造先進四方扁平無引腳(a-QFN)封裝結構之方法的示意性剖視圖。
圖3E' 至圖3F' 顯示圖3E至圖3F所示a-QFN封裝結構之一範例部分的放大剖視圖。
圖4是依照本發明另一實施例所繪示的一種先進四方扁平無引腳(a-QFN)封裝結構之示意性剖視圖。
10...a-QFN封裝結構
100...載體
110...基板
116a...第一金屬層
116b...第二金屬層
118...保護層
120...晶粒座
120a' ...容置空腔
122...中央部
124...接地環
130...內引腳
136...外引腳
138...引腳或接觸端
140...黏合層
150...晶片
160...導線
180...封裝膠體

Claims (16)

  1. 一種先進四方扁平無引腳封裝結構,包括:一載體,具有一晶粒座、及圍繞該晶粒座設置之多個引腳,其中各該些引腳包括一內引腳及一外引腳,且各該內引腳包括一金屬層及一保護層,該保護層覆蓋其下該金屬層之邊緣及側壁之至少一部分,且至少一個內引腳包括內彎側壁,而該保護層暴露出該金屬層的一部分;一晶片,位於該晶粒座上;多個導線,設置於該晶片與該些內引腳的該些金屬層之間,其中該些導線直接接觸該晶片與被該保護層所暴露出的該金屬層的該部分;以及一封裝膠體,用於封裝該晶粒座上之該晶片、該些導線及該些內引腳。
  2. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該保護層完全覆蓋其下該金屬層之一頂面及該些側壁。
  3. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該保護層更覆蓋該內引腳之該些內彎側壁之一部分。
  4. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該內引腳具有上部內彎側壁及下部內彎側壁,且該保護層完全覆蓋其下該金屬層之一頂面及該些側壁以及該內引腳之該些上部內彎側壁。
  5. 如申請專利範圍第1項所述之先進四方扁平無引 腳封裝結構,其中該保護層之材料包括一耐蝕刻性金屬材料。
  6. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該載體更包括至少一接地環,該至少一接地環位於該晶粒座上並藉由該導線而電性連接至該晶片。
  7. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該些引腳之材料包括鎳、金、鈀或其組合。
  8. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構,其中該內引腳具有該些內彎側壁,該些內彎側壁具有小於或等於0.5微米之一內彎距離。
  9. 一種製造一先進四方扁平無引腳封裝結構之方法,包括:提供一基板,該基板具有一上表面及一下表面;形成一第一金屬層於該基板之該上表面;使用該第一金屬層作為一蝕刻遮罩,對該基板之該上表面執行一第一蝕刻製程,以形成至少一空腔及多個第一開口;形成一保護層於該第一金屬層上,以覆蓋至少該第一金屬層之邊緣及側壁,其中該保護層暴露出該第一金屬層的一部分;使用該保護層及該第一金屬層作為一遮罩,對該基板之該上表面執行一第二蝕刻製程,以將該空腔變成一容置 空腔並擴大該些第一開口,其中該些擴大之第一開口定義出多個內引腳,且該些內引腳圍繞該容置空腔設置;提供一晶片至該基板之該容置空腔;於該晶片與該些內引腳上的該第一金屬層之間形成多個導線,其中該些導線直接接觸該晶片與被該保護層所暴露出的該第一金屬層的該部分;以及形成一封裝膠體於該基板上,以封裝該晶片、該些導線及該些內引腳。
  10. 如申請專利範圍第9項所述之製造方法,其中該保護層是藉由鍍覆而形成,且該保護層之材料包括一耐蝕刻性金屬材料。
  11. 如申請專利範圍第9項所述之製造方法,其中該第二蝕刻製程是一等向性蝕刻製程,且該些內引腳具有內彎側壁。
  12. 如申請專利範圍第9項所述之製造方法,其中該第一蝕刻製程及該第二蝕刻製程是等向性蝕刻製程,且該第一金屬層上之該保護層更覆蓋該些第一開口之側壁之一部分,使得該些內引腳具有上部內彎側壁及下部內彎側壁。
  13. 如申請專利範圍第9項所述之製造方法,更包括在形成該保護層之前執行一水刀製程。
  14. 如申請專利範圍第9項所述之製造方法,更包括形成一第二金屬層於該基板之該下表面上,其中該第一金屬層及該第二金屬層是藉由鍍覆而形成。
  15. 如申請專利範圍第9項所述之製造方法,更包括在提供該晶片之前,在該容置空腔內形成一黏合層。
  16. 如申請專利範圍第9項所述之製造方法,更包括使用該基板之該下表面上的該第二金屬層作為一蝕刻遮罩,對該基板之該下表面執行一第三蝕刻製程,以蝕刻穿透該基板,直至暴露出填充於該些擴大之第一開口內的該封裝膠體為止,藉此形成多個引腳及一晶粒座。
TW099143376A 2010-11-11 2010-12-10 先進四方扁平無引腳封裝結構及其製造方法 TWI485828B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/944,695 US20120119342A1 (en) 2010-11-11 2010-11-11 Advanced quad flat non-leaded package structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201220452A TW201220452A (en) 2012-05-16
TWI485828B true TWI485828B (zh) 2015-05-21

Family

ID=44268088

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099143376A TWI485828B (zh) 2010-11-11 2010-12-10 先進四方扁平無引腳封裝結構及其製造方法

Country Status (3)

Country Link
US (1) US20120119342A1 (zh)
CN (1) CN102130073B (zh)
TW (1) TWI485828B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629599B (zh) * 2012-04-06 2014-09-03 天水华天科技股份有限公司 四边扁平无引脚封装件及其生产方法
TWI496243B (zh) * 2012-05-29 2015-08-11 Tripod Technology Corp 元件內埋式半導體封裝件的製作方法
US9013028B2 (en) * 2013-01-04 2015-04-21 Texas Instruments Incorporated Integrated circuit package and method of making
KR102046534B1 (ko) 2013-01-25 2019-11-19 삼성전자주식회사 기판 가공 방법
US8916422B2 (en) * 2013-03-15 2014-12-23 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP6617955B2 (ja) * 2014-09-16 2019-12-11 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
US20160172292A1 (en) * 2014-12-16 2016-06-16 Mediatek Inc. Semiconductor package assembly
US9748187B2 (en) 2014-12-19 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and method for wafer dicing
ITUB20152895A1 (it) * 2015-08-05 2017-02-05 St Microelectronics Srl Procedimento per realizzare circuiti integrati e circuito corrispondente
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP2017103365A (ja) * 2015-12-02 2017-06-08 新光電気工業株式会社 リードフレーム及び電子部品装置とそれらの製造方法
CN105789072B (zh) * 2016-05-04 2018-06-08 天水华天科技股份有限公司 一种面阵列无引脚csp封装件及其制造方法
JP6777365B2 (ja) * 2016-12-09 2020-10-28 大口マテリアル株式会社 リードフレーム
US9865527B1 (en) 2016-12-22 2018-01-09 Texas Instruments Incorporated Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation
US9941194B1 (en) 2017-02-21 2018-04-10 Texas Instruments Incorporated Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer
CN108627994A (zh) * 2017-03-24 2018-10-09 敦捷光电股份有限公司 光准直器及其制造方法
IT201700089965A1 (it) * 2017-08-03 2019-02-03 St Microelectronics Srl Procedimento di produzione di componenti elettronici e corrispondente componente elettronico
US10529672B2 (en) * 2017-08-31 2020-01-07 Stmicroelectronics, Inc. Package with interlocking leads and manufacturing the same
CN112786435A (zh) * 2019-11-07 2021-05-11 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432643B (en) * 2000-01-12 2001-05-01 Advanced Semiconductor Eng Low pin-count chip package structure and its manufacturing method
US20100258934A1 (en) * 2009-04-10 2010-10-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342730B1 (en) * 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
DE10137956A1 (de) * 2001-08-07 2002-10-31 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchip und Systemträger für mehrere elektronische Bauteile, sowie Verfahren zur Herstellung derselben
SG140574A1 (en) * 2006-08-30 2008-03-28 United Test & Assembly Ct Ltd Method of producing a semiconductor package
WO2009036604A1 (en) * 2007-09-20 2009-03-26 Asat Limited Etching isolation of lpcc/qfn strip
CN101527293A (zh) * 2008-03-03 2009-09-09 南茂科技股份有限公司 四方扁平无引脚型态封装结构以及导线架
US8115285B2 (en) * 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US8502357B2 (en) * 2009-10-01 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with shaped lead and method of manufacture thereof
KR101113891B1 (ko) * 2009-10-01 2012-02-29 삼성테크윈 주식회사 리드 프레임 및 리드 프레임 제조 방법
US20110108966A1 (en) * 2009-11-11 2011-05-12 Henry Descalzo Bathan Integrated circuit packaging system with concave trenches and method of manufacture thereof
US8669649B2 (en) * 2010-09-24 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432643B (en) * 2000-01-12 2001-05-01 Advanced Semiconductor Eng Low pin-count chip package structure and its manufacturing method
US20100258934A1 (en) * 2009-04-10 2010-10-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US20100258920A1 (en) * 2009-04-10 2010-10-14 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package

Also Published As

Publication number Publication date
CN102130073A (zh) 2011-07-20
TW201220452A (en) 2012-05-16
US20120119342A1 (en) 2012-05-17
CN102130073B (zh) 2013-05-08

Similar Documents

Publication Publication Date Title
TWI485828B (zh) 先進四方扁平無引腳封裝結構及其製造方法
US8106492B2 (en) Semiconductor package and manufacturing method thereof
TWI474455B (zh) 先進四方扁平無引腳封裝結構
US8674487B2 (en) Semiconductor packages with lead extensions and related methods
US7728414B2 (en) Lead frame and resin-encapsulated semiconductor device
KR100927319B1 (ko) 스탬핑된 리드프레임 및 그 제조 방법
US20050218499A1 (en) Method for manufacturing leadless semiconductor packages
US7808084B1 (en) Semiconductor package with half-etched locking features
US8803300B2 (en) Integrated circuit packaging system with protective coating and method of manufacture thereof
TWI455213B (zh) 無外引腳封裝結構及其製作方法
US20070059863A1 (en) Method of manufacturing quad flat non-leaded semiconductor package
US8772089B2 (en) Chip package structure and manufacturing method thereof
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
US9659842B2 (en) Methods of fabricating QFN semiconductor package and metal plate
US20150084171A1 (en) No-lead semiconductor package and method of manufacturing the same
JP5971531B2 (ja) 樹脂封止型半導体装置及びその製造方法
KR100940760B1 (ko) 반도체 패키지
KR101684150B1 (ko) 반도체 패키지 및 그 제조 방법
KR101209472B1 (ko) 반도체 패키지 제조용 리드프레임 및 이를 이용한 반도체 패키지 제조 방법
KR101333001B1 (ko) 반도체 패키지용 리드프레임 및 이를 이용한 반도체 패키지 제조 방법
US20170194235A1 (en) Lead frame and semiconductor package structure
KR20030079170A (ko) 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법
JP2009152328A (ja) リードフレームおよびその製造方法
KR20120121250A (ko) 반도체 패키지 및 이의 제조 방법