CN102130073A - 先进四方扁平无引脚封装结构及其制造方法 - Google Patents
先进四方扁平无引脚封装结构及其制造方法 Download PDFInfo
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- CN102130073A CN102130073A CN2010106030619A CN201010603061A CN102130073A CN 102130073 A CN102130073 A CN 102130073A CN 2010106030619 A CN2010106030619 A CN 2010106030619A CN 201010603061 A CN201010603061 A CN 201010603061A CN 102130073 A CN102130073 A CN 102130073A
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Abstract
本发明公开一种先进四方扁平无引脚封装结构及其制造方法。该先进四方扁平无引脚封装结构包括一载体、一芯片、多个导线、及一封装胶体。载体包括一管芯座及多个引脚。引脚的内引脚被设计成具有内弯的侧壁,以增强内引脚与周围封装胶体间的粘附性。
Description
技术领域
本发明大体而言是涉及一种封装结构及其制造方法,且特别是涉及一种先进四方扁平无引脚(advanced quad flat non-leaded,a-QFN)封装结构及其制造方法。
背景技术
四方扁平封装(quad flat package,QFP)家族包括I型(QFI)、J型(QFJ)及无引脚型(QFN)封装,其特征在于导线架(leadframe)的引线的形状。其中,QFN封装结构可提供多种优点,包括引线电感减小、占用面积(footprint)尺寸小、更薄且信号传输速度更快。因此,QFN封装已成为一种流行的封装结构选项,并且适用于具有高频(例如,射频频宽)传输的芯片封装。
对于QFN封装结构,管芯座(die pad)及其周围的接触端(引脚焊垫)是由平面状导线架基板制成。QFN封装结构一般通过表面粘着技术(surfacemounting technology,SMT)而焊接至印刷电路板(printed circuit board,PCB)。因此,QFN封装结构的接触端/焊垫需要被设计成很好地适合于封装制作工艺能力并能促进良好的长期接合可靠性。
发明内容
本发明的目的在于提供一种先进四方扁平无引脚封装及其制造方法,其可帮助减轻引脚脱落问题并增强产品可靠性。
为达上述目的,本发明提供一种先进四方扁平无引脚封装结构,该先进四方扁平无引脚封装结构具有一载体、一设置于该载体上的芯片、多个导线及一封装胶体。该载体包括一管芯座及多个引脚,且该些引脚包括多个内引脚及由该封装胶体暴露出的多个外引脚。至少一个内引脚包括一金属层及一保护层,该保护层覆盖其下该金属层的边缘及侧壁的至少一部分。此外,至少一个内引脚具有内弯侧壁,该些内弯侧壁能够增强内引脚与周围封装胶体间的粘附性。该些导线设置于该芯片与该些内引脚之间。该封装胶体用于封装该芯片、该些导线及该些内引脚。
根据本发明的实施例,内引脚的侧壁可被设计成内弯的或弯曲的,以提升内引脚与周围封装胶体的锁定(locking)或楔合(wedging)能力。
本发明更提供一种制造一先进四方扁平无引脚封装结构的方法。在提供具有一上表面及一下表面的一基板后,在该基板的上表面及下表面上分别形成一第一金属层及一第二金属层,并对基板的上表面执行一第一蚀刻制作工艺。随后,在第一金属层上形成一保护层,以覆盖该第一金属层的至少边缘及侧壁。使用该保护层及该第一金属层作为一掩模,对该基板的上表面执行一第二蚀刻制作工艺,以形成一容置空腔及多个开口并定义出多个内引脚。该些内引脚具有内弯侧壁。在提供一芯片至该基板的容置空腔并于芯片与内引脚之间形成多个导线后,在基板上形成一封装胶体,以封装该芯片、该些导线、该些内引脚并填充该容置空腔以及该些内引脚间的开口。之后,可使用第二金属层作为一蚀刻掩模来执行一第三蚀刻制作工艺,以对基板进行穿透蚀刻,直至暴露出填充于该些开口内的封装胶体,由此形成多个引脚及一管芯座。
根据本发明的实施例,可通过以下方式制成内引脚:形成保护层部分地或完全地覆盖其下第一金属层,并使用保护层及第一金属层二者作为掩模将基板图案化。因此,利用在蚀刻期间出现的底切,所获得的内引脚具有内弯侧壁,此会增大内引脚与封装胶体间的接触面积。
为让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附附图,作详细说明如下。
附图说明
为达成对本发明的进一步理解,本说明包含附图,该些附图包含于本说明书中并构成本说明书的一部分。该些附图绘示本发明的实施例并与本说明一起用于解释本发明的原理。
图1A至图1J是依照本发明的一实施例所绘示的一种制造先进四方扁平无引脚(a-QFN)封装结构的方法的示意性剖视图;
图1E′至图1F′显示图1E至图1F所示a-QFN封装结构的一范例部分的示意性剖视图;
图2是依照本发明的一实施例所绘示的一种先进四方扁平无引脚(a-QFN)封装结构的示意性剖视图;
图3A至图3J是依照本发明的另一实施例所绘示的一种制造先进四方扁平无引脚(a-QFN)封装结构的方法的示意性剖视图;
图3E′至图3F′显示图3E至图3F所示a-QFN封装结构的一范例部分的放大剖视图;
图4是依照本发明另一实施例所绘示的一种先进四方扁平无引脚(a-QFN)封装结构的示意性剖视图。
主要元件符号说明
10:a-QFN封装结构
20:a-QFN封装结构
30:a-QFN封装结构
40:a-QFN封装结构
100:载体
110:基板
110a:上表面
110b:下表面
114a:第一图案化光致抗蚀剂层
114b:第二图案化光致抗蚀剂层
115a:第一金属部
115b:第二金属部
115c:顶面
115d:侧壁
115e:边缘
116a:第一金属层
116b:第二金属层
117a:第三金属部
117b:第四金属部
118:保护层
120:管芯座
120a:第一空腔
120a′:容置空腔
122:中央部
124:接地环
130:内引脚
136:外引脚
138:引脚或接触端
140:粘合层
150:芯片
160:导线
180:封装胶体
200:载体
216a:金属层
218:保护层
220:管芯座
224:接地环
230:内引脚
236:外引脚
238:引脚(接触端)
250:芯片
260:导线
280:封装胶体
300:载体
310:基板
310a:上表面
310b:下表面
314a:第一图案化光致抗蚀剂层
314b:第二图案化光致抗蚀剂层
315a:第一金属部
315b:第二金属部
315c:顶面
315d:侧壁
316a:第一金属层
316b:第二金属层
317a:第三金属部
317b:第四金属部
318:保护层
320:管芯座
320a:第一空腔
320a′:容置空腔
322:中央部
324:接地环
330:内引脚
336:外引脚
340:粘合层
350:芯片
360:导线
380:封装胶体
400:载体
416a:金属层
418:保护层
420:管芯座
424:接地环
430:内引脚
436:外引脚
438:引脚(接触端)
450:芯片
460:导线
480:封装胶体
d:距离
Ss:第一开口S1′的侧壁
S1:第一开口
S1′:更深的第一开口
S2:第二开口
S3:第一开口
S3′:更深的第一开口
S3a:侧壁表面/上部内弯侧壁
S3b:下部内弯侧壁
S4:第二开口
具体实施方式
现在,将详细参照本发明的较佳实施例,此等较佳实施例的范例绘示于附图中。在附图及说明中,将尽可能使用相同的参考编号来表示相同或相似的部件。
图1A至图1J是依照本发明的一实施例所绘示的一种制造先进四方扁平无引脚封装结构的方法的示意性剖视图。
如图1A所示,提供基板110,基板110具有上表面110a及下表面110b。举例而言,基板110的材料可为铜、铜合金或其他适用的金属材料。接下来,仍参见图1A,在基板110的上表面110a上形成第一图案化光致抗蚀剂层(photoresist layer)114a,并于基板110的下表面110b上形成第二图案化光致抗蚀剂层114b。
接下来,参见图1B,使用第一光致抗蚀剂层114a/第二光致抗蚀剂层114b作为掩模(mask),在基板110的上表面110a的暴露部分上形成第一金属层116a,并于基板110的下表面110b的暴露部分上形成第二金属层116b。在本实施例中,第一金属层116a及第二金属层116b可通过例如镀覆(plating)而形成。端视第一图案化光致抗蚀剂层114a或第二图案化光致抗蚀剂层114b的图案设计而定,本文所述的第一金属层116a或第二金属层116b可由各种不相连图案的群组或由一连续层构成。举例而言,第一金属层116a可为一镍金叠层(Ni/Au layer)。
如图1B所示,第一金属层116a包括多个第一金属部115a及至少一第二金属部115b。第一金属部115a随后将被形成为内引脚130(如图1F所示),而第二金属部115b随后将被形成为管芯座120的接地环124(如图1I所示)。类似地,第二金属层116b包括多个第三金属部117a及至少一第四金属部117b。第三金属部117a对应于随后所将形成的外引脚136(如图1I所示),而第四金属部117b则对应于随后所将形成的管芯座120。
接下来,参见图1C,移除第一光致抗蚀剂层114a。然后,通过使用第一金属层116a作为蚀刻掩模,对基板110的上表面110a执行一第一蚀刻制作工艺(例如各向同性蚀刻制作工艺),以移除基板110的部分并形成至少一第一空腔120a及多个第一开口S1。举例而言,该第一蚀刻制作工艺为湿蚀刻制作工艺(wet etching process)。因第一蚀刻制作工艺为各向同性蚀刻制作工艺,故可轻易地在第一金属层116a之下形成底切(undercut)。因而,如图1D所示,执行水刀(water-jet)制作工艺,以切除或移除位于底切正上方的第一金属层116a的部分。
接着,参见图1E或图1E′,形成保护层118,以至少覆盖第一金属部115a及第二金属部115b的边缘及侧壁。图1E′显示图1E所示a-QFN封装结构的一范例部分的放大剖视图。举例而言,保护层118可通过以下方式形成:涂覆一填充材料(图未示出)至第一空腔120a及第一开口S1,然后于第一金属层116a上镀覆一金属层(图未示出)。另一选择为,图1E′中的保护层118不仅覆盖(即保护)第一金属部115a及第二金属部115b的边缘115e及侧壁115d,且也覆盖第一金属部115a及第二金属部115b的顶面115c。举例而言,保护层118的材料可为金或任何适宜的耐蚀刻性金属材料。
接着,参见图1F或图1F′,通过使用保护层118以及第一金属层116a作为蚀刻掩模,对基板110的上表面110a执行第二各向同性蚀刻制作工艺,以移除基板110的部分。因存在保护层118,故在第二蚀刻制作工艺中,第一金属层116a的侧壁受到保护。在此种情形中,第一金属层116a的图案(或开口)不会被改变,但下面的开口会变宽和变深。图1F′显示图1F所示a-QFN封装结构的一范例部分的放大剖视图。第一空腔120a更被蚀刻成容置空腔120a′,而第一开口S1更被蚀刻成更深的第一开口S1′。通过该些开口S1′的定义,形成多个单个的内引脚130。举例而言,第一开口S1与第一开口S1′的深度比可介于1∶3至1∶4范围内。因第二蚀刻制作工艺是各向同性蚀刻制作工艺,故第一开口S1’的侧面轮廓变宽,且可轻易地在保护层118与第一金属层116a之下形成底切。在此种情形中,第一开口S1′的侧壁Ss是外弯的(与第一蚀刻制作工艺后的开口侧壁相比,向外弯曲),且外弯距离「d」可例如为约0.5微米大。相反,内引脚130的侧壁S是内弯的(与第一蚀刻制作工艺后的内引脚侧壁相比,向内弯曲),且内弯距离「d」(自第一金属层的侧壁至内引脚的最内侧壁的水平距离)可例如为约0.5微米大。换言之,内引脚130在中间具有狭窄部(即颈部)。
如在实施例中所述,内引脚130利用形成底切来增强或最佳化内引脚对后续形成的封装胶体的锁定能力。因此,可精细地调节第二蚀刻制作工艺的蚀刻率(etching rate)及选择性,以获得最佳的效能,由此控制开口的尺寸或轮廓并最佳化引脚图案的形状。
至此,在形成第一金属层116a及第二金属层116b并将基板110图案化之后,已大致形成载体100。容置空腔120a′具有中央部122及围绕中央部122设置的周边部124。内引脚130是围绕周边部124设置但与周边部124间隔开。内引脚130可排列成列、行或阵列。周边部124可用作接地环。
接下来,参见图1G,在至少一芯片150与容置空腔120a′的中央部122之间使用一粘合层140将该至少一芯片150附着至容置空腔120a′的中央部122。随后,在芯片150、接地环124及内引脚130之间提供多个导线160。换言之,经由导线160将芯片150电连接至接地环124及内引脚130。
接下来,参见图1H,形成封装胶体180,以封装芯片150、导线160、内引脚130、接地环124及填充容置空腔120a′及第一开口S1′。
然后,参见图1I,使用第二金属层116b作为蚀刻掩模,对载体100的下表面110b执行第三蚀刻制作工艺,以移除基板110的一部分,以对载体100进行穿透蚀刻(etched through)而暴露出填充于第一开口S1′内的封装胶体180并同时形成多个第二开口S2。由于第二开口S2的形成,定义出多个外引脚136且各内引脚130被相互电性隔离。亦即,在第三蚀刻制作工艺后,形成多个引脚或接触端138,各该些引脚或接触端138分别由一个内引脚130与对应的外引脚136组成。此外,第三蚀刻制作工艺更定义出载体100的至少一管芯座120。管芯座120被引脚138环绕并通过第二开口S2而与引脚138隔离。总之,引脚138通过此蚀刻制作工艺而相互电性隔离。
接着,参见图1J,执行切单制作工艺(singulation process),以获得单个的a-QFN封装结构10。
详言之,在本实施例中,在第二蚀刻制作工艺中,保护层118保护第一图案化金属层116a的至少边缘及侧壁(图1F或图1F′),在第一金属层116a之下形成变宽的开口S1′且开口S1′的侧壁外弯(因底切所致)。因此,由于内引脚130(具有内弯的侧壁)与周围封装胶体180间的接触面积增大,故内引脚130与周围封装胶体180间的结合可得到增强,以使接触端180在表面粘着制作工艺或其他后续制作工艺中不会脱落,并可大幅提高产品可靠性。对于本实施例中的a-QFN封装结构10,可减轻接触端138的脱落问题且接触端(或引脚)的合型能力(mold locking capability)可得到增强。
图2是依照本发明的一实施例所绘示的一种先进四方扁平无引脚(a-QFN)封装结构的示意性剖视图,同时在右侧以放大的3D视图显示a-QFN封装结构的其中的一内引脚。参见图2,在本实施例中,先进四方扁平无引脚(a-QFN)封装结构20包括载体200、芯片250、多个导线260及封装胶体280。
本实施例中的载体200为例如导线架。详言之,载体200包括管芯座220及多个引脚(接触端)238。引脚238包括多个内引脚230及多个外引脚236。在图2中,示意性地绘示三行/列接触端238。具体而言,引脚238围绕管芯座220设置,且引脚238的材料可例如包括镍、金、钯或其一组合。内引脚与外引脚是由封装胶体限定;亦即,引脚被封装胶体封装的部分定义为内引脚,而外引脚则为引脚暴露于封装胶体外的部分。
此外,载体200的管芯座220还包括至少一接地环224。接地环224经由导线260而电连接至芯片250。由于接地环224连接至管芯座220,故管芯座与接地环一起可用作接地层(ground plane)。应注意者,图2中所示引线238相对于接地环224及管芯座220的位置、布置方式及数量仅为范例性的,而不应被视为用于限制本发明。
更详言之,如右侧的三维放大视图所示,本实施例中的内引脚230具有保护层218,保护层218覆盖金属层216a的至少边缘及侧壁。然而,保护层218可例如为环形的(仅覆盖边缘及侧壁)或帽子形的(覆盖金属层216a的顶面及侧壁)。在本实施例中,内引脚230及/或保护层218的布置方式或形状仅为范例性的。
在图2中,为强调第一开口S1′与第二开口S2的轮廓或外形之间的区别,外引脚236被范例性地绘示为具有垂直侧壁,而内引脚230被范例性地绘示为具有弯曲的侧壁。然而,应理解,外引脚236不必一定具有垂直侧壁。因存在保护层,发生于金属层下面的底切会使内引脚具有更为内弯的侧壁,此会显著增强引脚与封装胶体间的结合。
另外,本实施例中a-QFN封装结构20的封装胶体280用于封装芯片250、导线260及内引脚230并填充内引脚230之间的间隙,而外引脚236及管芯座220的底面则暴露。举例而言,封装胶体280的材料为环氧树脂(epoxyresin)或其他适用的聚合物材料。
图3A至图3J是依照本发明的另一实施例所绘示的一种制造先进四方扁平无引脚封装结构的方法的示意性剖视图。
如图3A所示,提供基板310,基板310具有上表面310a及下表面310b。举例而言,基板310的材料可为铜、铜合金或其他适用的金属材料。接下来,仍参见图3A,在基板310的上表面310a上形成第一图案化光致抗蚀剂层314a,并于基板310的下表面310b上形成第二图案化光致抗蚀剂层314b。
接下来,参见图3B,使用第一光致抗蚀剂层314a/第二光致抗蚀剂层314b作为掩模,在基板310的上表面310a的暴露部分上形成第一金属层316a,并于基板310的下表面310b的暴露部分上形成第二金属层316b。在本实施例中,第一金属层316a及第二金属层316b可通过例如镀覆而形成。端视第一图案化光致抗蚀剂层314a或第二图案化光致抗蚀剂层314b的图案设计而定,本文所述的第一金属层316a或第二金属层316b可由各种不相连图案的群组或由一连续层构成。举例而言,第一金属层316a可为一镍金叠层(Ni/Aulayer)。
如图3B所示,第一金属层316a包括多个第一金属部315a及至少一第二金属部315b。第一金属部315a随后将被形成为内引脚330(如图3F所示),而第二金属部315b随后将被形成为管芯座320的接地环324(如图3I所示)。类似地,第二金属层316b包括多个第三金属部317a及至少一第四金属部317b。第三金属部317a对应于随后所将形成的外引脚336(如图3I所示),而第四金属部317b则对应于随后所将形成的管芯座320。
接下来,参见图3C,移除第一光致抗蚀剂层314a及第二光致抗蚀剂层314b。然后,通过使用第一金属层316a作为蚀刻掩模,对基板310的上表面310a执行一第一蚀刻制作工艺(例如各向同性蚀刻制作工艺),以移除基板310的部分并形成至少一第一空腔320a及多个第一开口S3。举例而言,该第一蚀刻制作工艺为湿蚀刻制作工艺。因第一蚀刻制作工艺为各向同性蚀刻制作工艺,故可轻易地在第一金属层316a之下形成底切。因而,如图3D所示,执行水刀制作工艺,以切除或移除位于底切正上方的第一金属层316a的部分。
接着,参见图3E或图3E′,形成保护层318,以覆盖第一金属部315a及第二金属部315b并局部地覆盖第一开口S3的上部侧壁。图3E′显示图3E所示a-QFN封装结构的一范例部分的放大剖视图。举例而言,保护层318可通过以下方式形成:涂覆一填充材料(图未示出)至第一空腔320a及第一开口S3,然后于第一金属层316a上镀覆一金属材料层(图未示出)。图3E′中的保护层318不仅覆盖(即保护)第一金属部315a及第二金属部315b的顶面315c及侧壁315d,且也局部地覆盖第一开口S3的侧壁表面S3a(及空腔320a的侧壁)。在本文中,当出现底切时,开口S3的侧壁S3a为弯曲的。举例而言,保护层318的材料可为金或任何适宜的耐蚀刻性金属材料。
接着,参见图3F或图3F′,通过使用保护层318以及第一金属层316a作为蚀刻掩模,对基板310的上表面310a执行第二蚀刻制作工艺,以移除基板310的部分。因存在保护层318,故在第二蚀刻制作工艺中,第一金属层316a的侧壁及开口侧壁S3a的一部分受到保护。在此种情形中,第一金属层316a的图案不会被改变,但下面的开口会变深。图3F′显示图3F所示a-QFN封装结构的一范例部分的放大剖视图。第一空腔320a还被向下蚀刻而形成容置空腔320a′。类似地,第一开口S3更被向下蚀刻而形成更深的第一开口S3′。通过该些开口S3′的定义,形成多个单个的内引脚330。举例而言,第一蚀刻制作工艺与第二蚀刻制作工艺的深度比可介于1∶1至1∶2范围内。举例而言,第二蚀刻制作工艺是各向同性蚀刻制作工艺。因第一开口S3及第一空腔320a的侧壁至少部分地受到保护,故主要对第一开口S3及第一空腔320a的底部执行蚀刻。在此种情形中,由于两个蚀刻制作工艺,内引脚330具有上部内弯(向内弯曲)侧壁S3a及下部内弯侧壁S3b。换言之,内引脚330看起来像两个堆叠于一起的梯形棱柱,其中在中间具有突出的带状部(图4)。
如在实施例中所述,内引脚330利用由两个蚀刻制作工艺形成底切来增强或最佳化内引脚对后续形成的封装胶体的锁定能力。因此,可精细地调节第一蚀刻制作工艺/第二蚀刻制作工艺的蚀刻率及选择性,以获得最佳的效能,由此控制开口的尺寸或轮廓并最佳化引脚图案的形状。
至此,在形成第一金属层316a及第二金属层316b并将基板310图案化之后,已大致形成载体300。容置空腔320a’具有中央部322及围绕中央部322设置的周边部324。内引脚330是围绕周边部324设置但与周边部324间隔开。内引脚330可排列成列、行或阵列。周边部324可用作接地环。
接下来,参见图3G,在至少一芯片350与容置空腔320a′的中央部322之间使用一粘合层340将该至少一芯片350附着至容置空腔320a′的中央部322。随后,在芯片350、接地环324及内引脚330之间提供多个导线360。换言之,经由导线360将芯片350电连接至接地环324及内引脚330。
接下来,参见图3H,形成封装胶体380,以封装芯片350、导线360、内引脚330、接地环324及填充容置空腔320a′及第一开口S3′。
然后,参见图3I,使用第二金属层316b作为蚀刻掩模,对载体300的下表面310b执行第三蚀刻制作工艺,以移除基板310的一部分,以对载体300进行穿透蚀刻而暴露出填充于第一开口S3′内的封装胶体380并同时形成多个第二开口S4。由于第二开口S4的形成,定义出多个独立外引脚336且各内引脚330相互电性隔离。亦即,在第三蚀刻制作工艺后,形成多个引脚或接触端318,各该些引脚或接触端318分别由一个内引脚330与对应的外引脚336组成。此外,第三蚀刻制作工艺还定义出载体300的至少一管芯座320。管芯座320被引脚318环绕并通过第二开口S4而与引脚318隔离。总之,引脚318通过此蚀刻制作工艺而相互电性隔离。
接着,参见图3J,执行切单制作工艺,以获得单个的a-QFN封装结构30。
图4是依照本发明的另一实施例所绘示的一种先进四方扁平无引脚(a-QFN)封装结构的示意性剖视图,同时在右侧以放大的3D视图显示a-QFN封装结构的其中的一内引脚。参见图4,在本实施例中,先进四方扁平无引脚(a-QFN)封装结构40包括载体400、芯片450、多个导线460及封装胶体480。
本实施例中的载体400为例如导线架。详言之,载体400包括管芯座420及多个引脚(接触端)438。引脚438包括多个内引脚430及多个外引脚436,而该些内引脚及该些外引脚是由封装胶体定义。
此外,载体400的管芯座420还包括至少一接地环424。由于接地环424电连接至管芯座420,故管芯座与接地环一起可用作接地层。应注意者,图4中所示引线438相对于接地环424及管芯座420的位置、布置方式及数量仅为范例性的,而不应被视为用于限制本发明。
更详言之,如右侧的三维放大视图所示,本实施例中的内引脚430具有帽子形的保护层418,保护层418覆盖金属层416a的至少顶面及侧壁以及上部侧壁S3a的一部分。在本实施例中,内引脚430及/或保护层418的布置方式或形状仅为范例性的。
在图4中,为强调具有底切的开口的轮廓或外形,内引脚430及外引脚436被范例性地绘示为具有弯曲的侧壁。因存在保护层,发生于金属层下面的底切会使内引脚具有更为内弯的侧壁,此会显著增强引脚与封装胶体间的结合。
另外,本实施例中a-QFN封装结构40的封装胶体480用于封装芯片450、导线460及内引脚430并填充内引脚430之间的间隙,而外引脚436及管芯座420的底面则暴露。举例而言,封装胶体480的材料为环氧树脂或其他适用的聚合物材料。
对于根据上述实施例的a-QFN封装结构,内引脚是通过至少两个蚀刻制作工艺而制成,且后一蚀刻制作工艺可于模制制作工艺之前精调内引脚侧壁的轮廓。此外,由于在蚀刻制作工艺期间,内引脚部分上的金属层至少部分地被保护层覆盖,故对金属层的损伤减小。所述实施例中的a-QFN封装结构被设计成具有更佳的锁定能力(即内引脚与封装胶体间的粘附性更强),进而解决脱落问题并提高产品可靠性。
虽然已以较佳实施例揭露如上本发明,然而其并非用以限定本发明,任何熟悉此技术者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围应以附上的权利要求所界定的为准。
Claims (16)
1.一种先进四方扁平无引脚封装结构,包括:
载体,具有管芯座、及围绕该管芯座设置的多个引脚,其中各该些引脚包括内引脚及外引脚,且至少一个内引脚包括金属层及保护层,该保护层覆盖其下该金属层的边缘及侧壁的至少一部分,且至少一个内引脚包括内弯侧壁;
芯片,位于该管芯座上;
多个导线,设置于该芯片与该些内引脚之间;以及
封装胶体,用于封装该管芯座上的该芯片、该些导线及该些内引脚。
2.如权利要求1所述的先进四方扁平无引脚封装结构,其中该保护层完全覆盖其下该金属层的一顶面及该些侧壁。
3.如权利要求1所述的先进四方扁平无引脚封装结构,其中该保护层还覆盖该内引脚的该些内弯侧壁的一部分。
4.如权利要求1所述的先进四方扁平无引脚封装结构,其中该内引脚具有上部内弯侧壁及下部内弯侧壁,且该保护层完全覆盖其下该金属层的一顶面及该些侧壁以及该内引脚的该些上部内弯侧壁。
5.如权利要求1所述的先进四方扁平无引脚封装结构,其中该保护层的材料包括一耐蚀刻性金属材料。
6.如权利要求1所述的先进四方扁平无引脚封装结构,其中该载体还包括至少一接地环,该至少一接地环位于该管芯座上并通过该导线而电连接至该芯片。
7.如权利要求1所述的先进四方扁平无引脚封装结构,其中该些引脚的材料包括镍、金、钯或其组合。
8.如权利要求1所述的先进四方扁平无引脚封装结构,其中该内引脚具有该些内弯侧壁,该些内弯侧壁具有小于或等于0.5微米的一内弯距离。
9.一种制造一先进四方扁平无引脚封装结构的方法,包括:
提供一基板,该基板具有上表面及下表面;
形成一第一金属层于该基板的该上表面;
使用该第一金属层作为一蚀刻掩模,对该基板的该上表面执行一第一蚀刻制作工艺,以形成至少一空腔及多个第一开口;
形成一保护层于该第一金属层上,以覆盖至少该第一金属层的边缘及侧壁;
使用该保护层及该第一金属层作为一掩模,对该基板的该上表面执行一第二蚀刻制作工艺,以将该空腔变成一容置空腔并扩大该些第一开口,其中该些扩大的第一开口定义出多个内引脚,且该些内引脚围绕该容置空腔设置;
提供一芯片至该基板的该容置空腔;
在该芯片与该些内引脚之间形成多个导线;以及
形成一封装胶体于该基板上,以封装该芯片、该些导线及该些内引脚。
10.如权利要求9所述的方法,其中该保护层是通过镀覆而形成,且该保护层的材料包括一耐蚀刻性金属材料。
11.如权利要求9所述的方法,其中该第二蚀刻制作工艺是一各向同性蚀刻制作工艺,且该些内引脚具有内弯侧壁。
12.如权利要求9所述的方法,其中该第一蚀刻制作工艺及该第二蚀刻制作工艺是各向同性蚀刻制作工艺,且该第一金属层上的该保护层还覆盖该些第一开口的侧壁的一部分,使得该些内引脚具有上部内弯侧壁及下部内弯侧壁。
13.如权利要求9所述的方法,还包括在形成该保护层之前执行一水刀制作工艺。
14.如权利要求9所述的方法,还包括形成一第二金属层于该基板的该下表面上,其中该第一金属层及该第二金属层是通过镀覆而形成。
15.如权利要求9所述的方法,还包括在提供该芯片之前,在该容置空腔内形成一粘合层。
16.如权利要求9所述的方法,还包括使用该基板的该下表面上的该第二金属层作为一蚀刻掩模,对该基板的该下表面执行一第三蚀刻制作工艺,以蚀刻穿透该基板,直至暴露出填充于该些扩大的第一开口内的该封装胶体为止,由此形成多个引脚及一管芯座。
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CN109427723A (zh) * | 2017-08-31 | 2019-03-05 | 意法半导体公司 | 具有互锁引线的封装件及其制造 |
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Also Published As
Publication number | Publication date |
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TW201220452A (en) | 2012-05-16 |
CN102130073B (zh) | 2013-05-08 |
US20120119342A1 (en) | 2012-05-17 |
TWI485828B (zh) | 2015-05-21 |
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