CN101656238A - 先进四方扁平无引脚封装结构及制造方法 - Google Patents

先进四方扁平无引脚封装结构及制造方法 Download PDF

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CN101656238A
CN101656238A CN200910160959A CN200910160959A CN101656238A CN 101656238 A CN101656238 A CN 101656238A CN 200910160959 A CN200910160959 A CN 200910160959A CN 200910160959 A CN200910160959 A CN 200910160959A CN 101656238 A CN101656238 A CN 101656238A
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pin
wafer
quad flat
flat non
leaded package
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CN101656238B (zh
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张简宝徽
胡平正
江柏兴
郑维伦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明涉及一种先进四方扁平无引脚封装结构及制造方法，先进四方扁平无引脚封装结构包括一载体、一晶片、多条焊线以及一封装胶体。载体包括一晶片座以及多个引脚。引脚包括多个围绕晶片座配置的第一引脚、多个围绕第一引脚配置的第二引脚以及位于第一引脚与第二引脚之间的至少一嵌入引脚部。焊线配置于晶片、第一引脚与嵌入引脚部之间。设计有嵌入引脚部的先进四方扁平无引脚封装结构可提供较佳的电性连接。

Description

先进四方扁平无引脚封装结构及制造方法
技术领域
本发明涉及一种封装结构及制造方法，尤其涉及一种先进四方扁平无引脚(advanced quad flat non-leaded；简称为：a-QFN)封装结构及制造方法。
本申请案要求2008年8月21日申请的美国临时申请案第61/090，879号的优先权。上文所提及的专利申请案的全文在此以引用的方式并入本文中，且构成说明书的一部分。
背景技术
依据导线架(leadframe)引脚的形状，四方扁平封装(quad flat package；简称为：QFP)可分为I型(quad flat package with”I”l ead；简称为：QFI)、J型(quad flat package with”J”lead；简称为：QFJ)及无引脚型(Quad Flat Non-leaded；简称为：QFN)封装。由于QFN封装结构具有相对较短的信号传递路径以及较快的信号传输速度，所以QFN封装结构已成为具有较低脚位(pin count)的封装结构的一种流行选择，且适合具有高频(例如，射频频宽)传输的晶片封装(chip package)。
一般而言，在QFN封装结构的制造过程中，多个晶片配置于导线架上，且通过多条焊线而电性连接至导线架。接着，形成一封装胶体以包覆导线架、晶片及焊线。最后，通过单体化(singulation)制程来形成多个QFN晶片封装结构。
发明内容
本发明的目的是提供一种先进四方扁平无引脚封装结构及制造方法，有助于减少交叉线(cross wire)问题并增强产品可靠度。
本发明提供一种先进四方扁平无引脚封装结构。先进四方扁平无引脚封装结构包括一载体、一配置于载体上的晶片、多条焊线以及一封装胶体。载体包括一晶片座(die pad)以及多个引脚，且引脚包括多个围绕晶片座配置的第一引脚、多个围绕第一引脚配置的多个第二引脚，以及至少一嵌入引脚部。每一第一引脚包括一第一内引脚以及一第一外引脚，而每一第二引脚包括一第二内引脚以及一第二外引脚。嵌入引脚部位于第一内引脚与第二内引脚之间。焊线配置于晶片、第一内引脚与嵌入引脚部之间。封装胶体包覆晶片、晶片座、焊线、第一内引脚、第二内引脚以及嵌入引脚部。
根据本发明的一实施例，嵌入引脚部可为一配置于第一内引脚与第二内引脚之间且与第一内引脚以及第二内引脚电性绝缘的浮置端子。因此，封装结构可还包括至少一配置于浮置端子与第二内引脚之一之间的跨接线(jumper)，以使得晶片通过焊线、浮置端子以及跨接线而电性连接至第二内引脚。跨接线的材料可与焊线的材料相同或不同。或者，根据本发明的另一实施例，嵌入引脚部为一使第一内引脚之一与第二内引脚之一直接连接的连接部，以使得晶片通过焊线以及连接部而电性连接至第二内引脚。
根据本发明的一实施例，载体还包括位于晶片座上且通过焊线电性连接至晶片的至少一接地环(ground ring)和/或电源环(power ring)。电源环与接地环电性绝缘。
本发明还提供一种先进四方扁平无引脚封装结构的制造方法，包括以下步骤。提供一载体。载体具有至少一容纳槽(accommodating cavity)、多个第一内引脚、多个第二内引脚以及由多个开口所定义的至少一引脚部。第一内引脚围绕容纳槽配置，第二内引脚围绕第一内引脚配置，且引脚部配置于第一内引脚与第二内引脚之间。在载体的一下表面上包括覆盖于载体的对应于第一内引脚及第二内引脚的多个第一金属部，及覆盖于载体的对应于容纳槽的多个第二金属部。提供一晶片于容纳槽内后，形成多条焊线。焊线配置于晶片、第一内引脚与引脚部之间。接着，形成一封装胶体以包覆晶片、焊线、第一内引脚、第二内引脚、引脚部，并填充容纳槽以及开口内。之后，通过载体的下表面上的第一金属部以及第二金属部作为蚀刻罩幕来进行一蚀刻制程，以蚀刻穿过载体直至填充于开口内的封装胶体暴露为止，以便形成多个第一引脚、多个第二引脚以及一晶片座。
根据本发明的一实施例，当引脚部为一配置于第一内引脚与第二内引脚之间并与第一内引脚以及第二内引脚电性绝缘的浮置端子时，制造方法还包括在形成封装胶体前，形成配置于浮置端子与第二内引脚之一之间的至少一跨接线，以使得晶片通过焊线、浮置端子以及跨接线而电性连接至第二内引脚。跨接线的材料可与焊线的材料相同或不同。或者，当引脚部为一使第一内引脚之一与第二内引脚之一直接连接的连接部时，晶片通过焊线以及连接部而电性连接至第二内引脚。
根据本发明的一实施例，在提供晶片之前，先进四方扁平无引脚封装结构的制造方法还包括在容纳槽的中心部上形成黏着层。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并结合附图作详细说明如下。
附图说明
图1A至图1H为本发明的一实施例的一种先进四方扁平无引脚封装结构的制造方法的剖面示意图。
图2A为本发明的一实施例的一种先进四方扁平无引脚封装结构的俯视示意图。
图2B为沿图2A的线I-I’的剖面示意图。
图2C为图2A的仰视示意图。
图3A至图3E为本发明的另一实施例的一种先进四方扁平无引脚封装结构的制造方法的剖面示意图。
图4A为本发明的另一实施例的一种先进四方扁平无引脚封装结构的俯视示意图。
图4B为沿图4A的线II-II’的剖面示意图。
图4C为图4A的仰视示意图。
主要元件符号说明：
232b、232ab：第一外引脚；     200、200a：载体；
210：基板；                   210a、210a’：上表面；
210b、210b’：下表面；        214a：第一图案化光阻层；
214b：第二图案化光阻层；      216a、216a’：第一金属层；
216b、216b’：第二金属层；    217a、217a’：第一金属部；
217b、217b’：第二金属部；    220、220a”：晶片座；
220a、220a’：容纳槽；        222、222a：中心部；
2 24、224a：周边部/接地环；   230、230a：引脚；
234b、234ab：第二外引脚；     236：第三内引脚/浮置端子；
236a：连接部；                240、240a：接地环；
250、250a：电源环；           300、300a：晶片；
400、400a：焊线；             500：跨接线；
500a、600：封装胶体；         600a、700：黏着层；
S1、S1’：第一开口；          S2、S2’：第二开口；
100、100a：先进四方扁平无引脚封装结；
232、232a、232aa：第一内引脚/第一引脚；
234、234a、234aa：第二内引脚/第二引脚。
具体实施方式
现将详细描述本发明目前较佳实施例，其实例在附图中说明。在任何可能之处，附图及描述内容中均使用相同附图标记来指代相同或相似部分。
图1A至图1H为本发明的一实施例的一种先进四方扁平无引脚封装结构的制造方法的剖面示意图。
首先，如图1A所示，提供具有一上表面210a以及一下表面210b的基板210。基板210的材料可以是铜、铜合金或其他适用的金属材料。
接着，如图1A所示，形成一第一图案化光阻层214a于基板210的上表面210a上，且形成一第二图案化光阻层214b于基板210的下表面210b上。第一图案化光阻层214a暴露出部分于基板210的上表面210a，而第二图案化光阻层214b暴露部分于基板210的下表面210b。第一图案化光阻层214a与第二图案化光阻层214b不对称。
接着，如图1B所示，形成一第一金属层216a于基板210被暴露出的上表面210a上，且形成一第二金属层216b于基板210被暴露出的下表面210b上。在本实施例中，第一金属层216a与第二金属层216b可通过电镀而形成。本文所描述的第一金属层216a或第二金属层216b可以不是一连续层，具体根据第一图案化光阻层214a或第二图案化光阻层214b的图案设计而定。
具体地，结合图1D，第二金属层216b包括多个第一金属部217a以及至少一第二金属部217b。第一金属部217a对应于随后将形成的第一内引脚232以及第二内引脚234(不对应随后将形成的第三内引脚236)，且第二金属部217b对应于随后将形成的晶片座220(如图1H所示)。
接着，如图1C所示，同时移除第一图案化光阻层214a以及第二图案化光阻层214b，且分别保留第一金属层216a和第二金属层216b于基板210的上表面210a和下表面210b上。
接着，如图1D所示，通过利用第一金属层216a作为蚀刻罩幕来进行一蚀刻制程，以移除部分基板210，以便形成至少一容纳槽220a以及多个第一开口S1。至此，在形成第一金属层216a、第二金属层216b及图案化基板210后，粗略地形成载体200。
具体地，容纳槽220a具有中心部222及围绕中心部222配置的周边部224。通过开口S1来定义，以形成多个第一内引脚232、多个第二内引脚234以及至少一第三内引脚236。第一内引脚232环绕周边部224配置。第二内引脚234环绕第一内引脚232配置。第三内引脚236配置于第一内引脚232与第二内引脚234之间。值得注意的是，周边部224可视为接地环。
接着，如图1E所示，提供至少一晶片300至每一容纳槽220a的中心部222，其中一黏着层700位于晶片300与容纳槽220a的中心部222之间。通过配置于晶片300与容纳槽220a的中心部222之间的黏着层700，可增加晶片300与中心部222之间的粘着力。
接着，如图1F所示，提供多条焊线400以及至少一跨接线500。在本实施例中，焊线400配置于晶片300、接地环(周边部)224、第一内引脚232以及第三内引脚236之间。具体地，焊线400的一端焊接于晶片300上，而焊线400的另一端焊接于接地环(周边部)224、第一内引脚232以及第三内引脚236上。即，晶片300通过焊线400电性连接至接地环(周边部)224、第一内引脚232以及第三内引脚236。
跨接线500配置于第三内引脚236与第二内引脚234之间，以使晶片300与第二内引脚234电性连接。跨接线500的材料可不同于焊线400的材料。例如，跨接线500的材料可选自金、铜、镍、钯或其合金，而焊线400的材料可为金。晶片300通过焊线400电性连接至第三内引脚236，且晶片300通过跨接线500更进一步电性连接至第二内引脚234。第三内引脚236以及跨接线500的设计可不为直长线，且避免焊线偏移(wire sweep)或交叉线所引起的问题。
接着，如图1G所示，形成一封装胶体600以包覆晶片300、焊线400、跨接线500、第一内引脚232、第二内引脚234、接地环(周边部)224以及第三内引脚236，并填充于容纳槽220a以及第一开口S1内。
接着，如图1H所示，对载体200的下表面210b进行一蚀刻制程，以移除基板210被暴露的部分，载体200被蚀穿以暴露出填充于第一开口S1内的封装胶体600，且同时形成多个第二开口S2。第一内引脚232、第二内引脚234以及第三内引脚236通过蚀刻制程而彼此电性绝缘。此外，对载体200的下表面210b进行蚀刻制程以形成第二开口S2的期间，具有中心部222以及周边部224的晶片座220进一步由载体200的第二开口S2所定义。晶片座220是由第一引脚232所环绕，且通过第二开口S2与第一引脚232电性绝缘。
具体地，在本实施例中，对载体200的下表面210b进行蚀刻制程，以便形成第二开口S2。此外，由于对应于第三内引脚236的基板210未被第二金属层216b所覆盖，因此对应于第三内引脚236的基板210会通过蚀刻制程而被移除。第三内引脚236可视为浮置端子。本文所描述的跨接线500具有不同于焊线400的功能。一般而言，焊线400用于连接晶片300与其他引脚，而跨接线500用于连接浮置端子(第三内引脚)236与其他引脚，但不连接至晶片300。因此，完成设计有浮置端子(第三内引脚)236以及跨接线500中之一或多者的先进四方扁平无引脚封装结构。
简言之，本实施例的先进四方扁平无引脚封装结构使用浮置端子(第三内引脚)236以及跨接线500来代替直长线，使得晶片300可通过跨接线500以及浮置端子(第三内引脚)236电连接至较远的引脚(例如，第二内引脚234)。因此，本实施例的先进四方扁平无引脚封装结构可避免焊线偏移或交叉线的问题并增强产品能力。
图2A为本发明的一实施例的一种先进四方扁平无引脚封装结构的俯视示意图。图2B为沿图2A的线I-I’的剖面示意图。图2C为图2A的仰视示意图。为了方便说明，图2A中省略示出的部分元件。结合图2A、图2B与图2C，在本实施例中，先进四方扁平无引脚封装结构100包括一载体200、一晶片300、多条焊线400以及至少一跨接线500。
在本实施例中，载体200可以是导线架。具体地，载体200包括一晶片座220以及多个引脚230。引脚230包括多个第一引脚232、多个第二引脚234以及至少一浮置端子236。在图2A中，仅示意性地描绘二个浮置端子236。具体而言，第一引脚232围绕晶片座220配置，且每一第一引脚232包括一第一内引脚232a以及一第一外引脚232b。第二引脚234围绕第一引脚232配置，且每一第二引脚234包括一第二内引脚234a以及一第二外引脚234b。内引脚及外引脚是由封装胶体来界定，也就是说，引脚230被封装胶体包覆的部分定义为内引脚，而引脚230暴露于封装胶体外的部分定义为外引脚。浮置端子236配置于晶片座220的上表面上，且位于第一内引脚232a与第二内引脚234a之间。
更详细而言，本实施例的晶片座220具有矩形形状。例如，引脚230可沿晶片座220的两侧配置，或排列成一环状以环绕晶片座220配置。引脚230的排列可以是呈一阵列、单一列或多个列的环。在本实施例中，图2A的第一引脚232以及第二引脚234的配置仅为举例说明，本发明并不以此为限。此外，引脚230的材料包括金或钯。
焊线400配置于晶片300、第一引脚232与浮置端子236之间。具体地，焊线400的一端焊接于晶片300上，而焊线400的另一端焊接于第一内引脚232a以及浮置端子236上。即，晶片300通过焊线400电性连接至载体200的较近的第一引脚232或浮置端子236。
跨接线500配置于浮置端子236与较远的第二引脚234之间。跨接线500的一端焊接于浮置端子236上，而跨接线500的另一端焊接于第二内引脚234a上。晶片300通过浮置端子236以及跨接线500而电性连接至第二引脚234。
此外，本实施例中的先进四方扁平无引脚封装结构100还包括一封装胶体600。封装胶体600包覆晶片300、焊线400、跨接线500、第一内引脚232a、第二内引脚234a、浮置端子236，且填充于引脚230之间的间隙，而暴露出第一外引脚232b、第二外引脚234b以及晶片座220的底部表面。封装胶体600的材料可以是环氧树脂(epoxy resin)或另一适用的聚合物材料。
另外，在本实施例中，为了满足先进四方扁平无引脚封装结构100的电性整合设计的要求，载体200还包括至少一接地环240以及至少一电源环250。接地环240配置于第一引脚232与晶片座220之间，且通过焊线400电性连接至晶片300。电源环250配置于第一引脚232与晶片座220之间，且通过焊线400电性连接至晶片300。由于接地环240连接至晶片座220，因此晶片座连同接地环可一起视为接地平面。电源环250与接地环240电性绝缘。
值得注意的是，图2A与图2B中所示的接地环240以及与图2C中所示的电源环250的位置、配置及数量仅为举例说明，本发明并不以此为限。
简言之，本实施例中的先进四方扁平无引脚封装结构100具有浮置端子236与跨接线500，使得晶片300可通过浮置端子236与跨接线500电连接至较远引脚(例如，第二引脚234)。因此，浮置端子236与跨接线500的设计可代替直长线。因此，本实施例的先进四方扁平无引脚封装结构100可避免长线偏移或交叉线的问题，并增强产品能力。
图3A至图3E为本发明的另一实施例的一种先进四方扁平无引脚封装结构的制造方法的剖面示意图。
如图3A所示，在本实施例的先进四方扁平无引脚封装结构的制造方法中，首先，提供载体200a。载体200a具有至少一容纳槽220a’、多个第一开口S1’、一形成于载体200a的一上表面210a’上的第一金属层216a’以及一形成于载体200a的一下表面210b’上的第二金属层216b’。第一金属层216a’与第二金属层216b’不对称。具体地，第二金属层216b’包括多个第一金属部217a’以及一第二金属部217b’。第一金属部217a’对应于随后将形成的第二内引脚234aa，且第二金属部217b’对应于随后将形成的晶片座220a”(如图3E中所示)。此外，形成载体200a的步骤类似于图1A至图1C所示的步骤，在此不再赘述。
详细而言，每一容纳槽220a’具有一中心部222a以及一围绕中心部222a配置的周边部224a。如图3A所示，载体200a的第一金属层216a’通过第一开口S1’定义成多个第一内引脚232aa、多个第二内引脚234aa以及至少一连接部236a。具体而言，第一内引脚232aa靠近或环绕周边部224a配置。第二内引脚234aa配置于第一内引脚232aa附近或环绕第一内引脚232aa配置。第一金属层216a’的每一连接部236a配置于每一第一内引脚232aa与每一第二内引脚234aa之间。
在此必须注意的是，每一连接部236a连接一个第一内引脚232aa与一个邻近的第二内引脚234aa。在本实施例中，周边部224a可视为接地环。
接着，如图3B所示，提供至少一晶片300a至容纳槽220a’的中心部222a，其中一黏着层600a配置于晶片300a与容纳槽220a’的中心部222a之间。
接着，如图3C所示，形成多条焊线400a。在本实施例中，焊线400a配置于晶片300a、接地环(周边部)224a与第一内引脚232aa之间。晶片300a通过焊线400a电性连接至接地环224a以及第一内引脚232aa。由于每一连接部236a连接一个第一内引脚232aa与一个邻近的第二内引脚234aa，因此晶片300a可通过连接部236a与焊线400a而电性连接至第二内引脚234aa。即，连接部236a的设计是用于连接两个相邻引脚(例如，第一内引脚232aa及第二内引脚234aa)，可减小焊线400a的长度。
接着，如图3D所示，形成一封装胶体500a以包覆晶片300a、焊线400a、第一内引脚232aa、第二内引脚234aa、接地环(周围部)224a以及连接部236a，并填充于容纳槽220a’以及第一开口S1’内。
接着，如图3E所示，对载体200a的下表面210b’进行一蚀刻制程，以移除载体200a未被第二金属层216b’所覆盖的部分，直至暴露出封装胶体500a且形成多个第二开口S2’为止。填充于第一开口S1’中的封装胶体500a通过第二开口S2’而暴露。因此，第一引脚232a与第二内引脚234a彼此电性绝缘，除了连接部236a所连接的第一引脚232a与第二引脚234a之外。此外，对应于第一内引脚232aa以及连接部236a的载体200a的暴露部分在蚀刻制程期间同时被移除，直至第一开口S1’内的封装胶体500a通过第二开口S2’而暴露为止。即，第一引脚232a以及第二引脚234a通过蚀刻制程而彼此电性绝缘，除了连接部236a所连接的第一引脚232a与第二引脚234a之外。金属部的蚀刻速率和/或厚度，可通过精调而获得最佳效能。
此外，在形成第二开口S2’的蚀刻制程期间，同时定义晶片座220a”。晶片座220a”是由第一内引脚232aa所环绕，且通过第一开口S1’或第二开口S2’与第一内引脚232aa电性隔离。最后，完成具有连接部236a的设计的先进四方扁平无引脚封装结构。
如图3E所示，移除连接至连接部236a的第一内引脚232aa的外引脚。也就是说，连接至连接部236a的第一引脚232a仅具有第一内引脚232aa。然而，如在图4A至图4C中所示，对于大多数未连接至连接部236a的第一引脚232a而言，每一第一引脚232a包括第一内引脚232aa以及第一外引脚232ab。根据产品的要求，有可能修改第二金属层216b’的金属部设计，决定保留还是移除第一引脚232a或第二引脚234a的外引脚。
本实施例的先进四方扁平无引脚封装结构具有连接两个相邻引脚(例如，第一内引脚232aa以及第二内引脚234aa)的连接部236a，可减小焊线400a的长度。因此，本实施例中先进四方扁平无引脚封装结构可避免长线偏移(wire sweep)或交叉线的问题，并增强产品能力。
图4A为本发明的另一实施例的一种先进四方扁平无引脚封装结构的俯视图。图4B为沿图4A的线II-II’的剖面示意图。图4C为图4A的仰视示意图。为了方便说明，图4A中省略示出的部分元件。请结合图4A、图4B与图4C，在本实施例中，先进四方扁平无引脚封装结构100a包括一载体200a、一晶片300a以及多条焊线400a。
在本实施例中，载体200a可以是导线架。具体地，载体200a包括一晶片座220a”以及多个引脚230a。引脚230a包括多个第一引脚232a、多个第二引脚234a以及至少一连接部236a。一般而言，对于大多数的第一引脚232a而言，每一第一引脚232a包括一第一内引脚232aa以及一第一外引脚232ab。对于连接至连接部236a的第一引脚232a而言，第一引脚可仅包括第一内引脚232aa，而无外引脚。对于第二引脚234a而言，每一第二引脚234a包括一第二内引脚234aa以及一第二外引脚234ab。在图4A中，仅示意性地描绘两个连接部236a。每一连接部236a配置于每一第一内引脚232aa与每一第二内引脚234aa之间。
由于引脚230a的材料以及晶片座220a”的形状类似于图1A与图1B中所示的前述实施例，且上文已描述，因此在此不再赘述。
晶片300a配置于晶片座220a”上。焊线400a配置于晶片300a与引脚230a之间。在本实施例中，焊线400a的一端焊接于晶片300a上，而焊线400a的另一端焊接于连接部236a上。然而，由于连接部236a位于第一引脚232a与第二引脚234a之间，因此焊线400a可连接至较近的第一引脚232a或连接部236a的任何位置。一般而言，晶片300a通过焊线400a而电性连接至引脚230a。
另外，本实施例中的先进四方扁平无引脚封装结构100a还包括一封装胶体500a。封装胶体500a包覆晶片300a、焊线400a，并填充引脚230a之间的间隙。即，封装胶体500a包覆第一内引脚232aa、第二内引脚234aa以及连接部236a，而暴露出第一外引脚232ab以及第二外引脚234ab。
另外，本实施例的载体200a还包括用于电性整合设计的至少一接地环240a以及至少一电源环250a。由于接地环240a与电源环250a的位置、配置及数量类似于图2A、图2B与图2C中所示的前述实施例(如上文所描述)，因此在此不再赘述。此外，本实施例中的先进四方扁平无引脚封装结构100a还包括一黏着层600a。黏着层600a配置于晶片300a与晶片座220a”之间，用以增加晶片300a与晶片座220a”之间的粘着力。
简而言之，本实施例的先进四方扁平无引脚封装结构100a具有连接部236a，使得晶片300a可通过第一内引脚232aa与第二内引脚234aa之间的连接部236a而电连接至较远的引脚(例如，第二引脚234a)。因此，连接两个相邻引脚的连接部236a的设计，可减小焊线400a的长度。因此，本实施例的先进四方扁平无引脚封装结构100a可避免长线偏移(wire sweep)或交叉线的问题，并增强产品能力。
综上所述，先进四方扁平无引脚封装结构的浮置端子或连接部可被视为嵌入引脚部，其主要嵌入先进四方扁平无引脚封装结构的封装胶体内，除了其底部表面暴露于封装胶体之外。嵌入引脚部(即浮置端子或连接部)可提供较佳电性连接以及可提高可靠度。
最后应说明的是：以上实施例仅用以说明本发明的技术方案而非对其进行限制，尽管参照较佳实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对本发明的技术方案进行修改或者等同替换，而这些修改或者等同替换亦不能使修改后的技术方案脱离本发明技术方案的精神和范围。

Claims (16)

1、一种先进四方扁平无引脚封装结构，其特征在于，包括：
一载体，具有一晶片座以及多个引脚，其中所述多个引脚包括多个围绕所述晶片座配置的第一引脚、多个围绕多个所述第一引脚配置的第二引脚，以及至少一嵌入引脚部，每一所述第一引脚包括一第一内引脚以及一第一外引脚，每一所述第二引脚包括一第二内引脚以及一第二外引脚，且所述嵌入引脚部位于多个所述第一内引脚与多个所述第二内引脚之间；
一晶片，配置于所述载体的一上表面上且位于所述晶片座内；
多条焊线，配置于所述晶片、多个所述第一内引脚以及所述嵌入引脚部之间，使得所述晶片通过所述多条焊线而电性连接至多个所述第一内引脚和/或所述嵌入引脚部；以及
一封装胶体，包覆所述晶片座上的所述晶片、所述多条焊线、多个所述第一内引脚、多个所述第二内引脚以及所述嵌入引脚部。
2、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，其中所述嵌入引脚部为一配置于多个所述第一内引脚与多个所述第二内引脚之间且与多个所述第一内引脚以及多个所述第二内引脚电性绝缘的浮置端子。
3、根据权利要求2所述的先进四方扁平无引脚封装结构，其特征在于，还包括配置于所述浮置端子与多个所述第二内引脚之一之间的至少一跨接线，使得所述晶片通过所述多条焊线、所述浮置端子以及所述跨接线而电连接至所述第二内引脚。
4、根据权利要求3所述的先进四方扁平无引脚封装结构，其特征在于，其中所述跨接线的材料不同于所述多条焊线的材料。
5、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，其中所述嵌入引脚部为一使多个所述第一内引脚之一与多个所述第二内引脚之一直接连接的连接部，以使所述晶片通过所述焊线与所述连接部而电性连接至所述第二内引脚。
6、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，其中所述载体还包括至少一接地环，位于所述晶片座上且通过所述多条焊线而电性连接至所述晶片。
7、根据权利要求6所述的先进四方扁平无引脚封装结构，其特征在于，其中所述载体还包括至少一电源环，位于所述晶片座上且通过所述多条焊线而电性连接至所述晶片，所述电源环与所述接地环电性绝缘。
8、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，还包括一配置于所述晶片与所述晶片座之间的黏着层。
9、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，其中所述多个引脚的材料包括金或钯。
10、根据权利要求1所述的先进四方扁平无引脚封装结构，其特征在于，其中多个所述第一引脚配置较为靠近所述晶片座，而多个所述第二引脚配置较为远离所述晶片座。
11、一种先进四方扁平无引脚封装结构的制造方法，其特征在于，包括：
提供一载体，所述载体具有至少一容纳槽、多个第一内引脚、多个第二内引脚以及由多个开口所定义的至少一引脚部，其中所述多个第一内引脚围绕所述容纳槽配置，所述多个第二内引脚围绕所述多个第一内引脚配置，且所述引脚部配置于所述多个第一内引脚与所述多个第二内引脚之间，所述载体还包括配置于所述载体的一下表面上且对应于所述多个第一内引脚以及所述多个第二内引脚的多个第一金属部以及对应于所述容纳槽的多个第二金属部；
提供一晶片至所述容纳槽；
形成多条焊线；
在所述载体上形成一封装胶体以包覆所述晶片、所述多条焊线、所述多个第一内引脚、所述多个第二内引脚、所述引脚部，并填充所述容纳槽以及所述多个开口内；以及
通过所述载体的所述下表面上的所述多个第一金属部以及所述多个第二金属部作为蚀刻罩幕来进行一蚀刻制程，以蚀穿所述载体至填充于所述多个开口内的所述封装胶体暴露为止，以便形成多个第一引脚、多个第二引脚以及一晶片座。
12、根据权利要求11所述的先进四方扁平无引脚封装结构的制造方法，其特征在于，其中所述引脚部为一配置于所述多个第一内引脚与所述多个第二内引脚之间并与所述多个第一内引脚以及所述多个第二内引脚电性绝缘的浮置端子。
13、根据权利要求12所述的先进四方扁平无引脚封装结构的制造方法，其特征在于，其中形成所述多条焊线的步骤包括在所述晶片、所述多个第一内引脚与所述浮置端子之间形成所述多条焊线，以及在形成所述封装胶体之前，形成配置于所述浮置端子与所述多个第二内引脚之一之间的至少一跨接线，使得所述晶片通过所述多条焊线、所述浮置端子以及所述跨接线而电性连接至所述第二内引脚。
14、根据权利要求13所述的先进四方扁平无引脚封装结构的制造方法，其特征在于，其中所述跨接线的材料不同于所述多条焊线的材料。
15、根据权利要求11所述的先进四方扁平无引脚封装结构的制造方法，其特征在于，其中形成所述多条焊线的步骤包括在所述晶片与所述多个第一内引脚之间形成所述多条焊线，且所述引脚部为一使所述多个第一内引脚之一与所述多个第二内引脚之一直接连接的连接部，以使得所述晶片通过所述焊线以及所述连接部而电性连接至所述第二内引脚。
16、根据权利要求11所述的先进四方扁平无引脚封装结构的制造方法，其特征在于，其中在提供所述晶片之前，还包括在所述容纳槽内形成一黏着层。
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US8237250B2 (en) 2012-08-07
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