TWI587414B - 先進四方扁平無引腳封裝結構及其製造方法 - Google Patents

先進四方扁平無引腳封裝結構及其製造方法 Download PDF

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Publication number
TWI587414B
TWI587414B TW098143935A TW98143935A TWI587414B TW I587414 B TWI587414 B TW I587414B TW 098143935 A TW098143935 A TW 098143935A TW 98143935 A TW98143935 A TW 98143935A TW I587414 B TWI587414 B TW I587414B
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Taiwan
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package structure
quad flat
wafer
receiving groove
wafer holder
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TW098143935A
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English (en)
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TW201037776A (en
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張簡寶徽
胡平正
江柏興
鄭維倫
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日月光半導體製造股份有限公司
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Description

先進四方扁平無引腳封裝結構及其製造方法
本發明大體上是有關於一種封裝結構及其製造方法。更明確而言，本發明是有關於一種先進四方扁平無引腳(advanced quad flat non-leaded，a-QFN)封裝結構及其製造方法。
依據導線架(leadframe)之引腳的形狀，四方扁平封裝(quad flat package，QFP)可分為I型(QFI)、J型(QFJ)以及無引腳型(QFN)封裝。其中，由於QFN封裝結構具有降低引腳感應係數(inductance)、小型腳位(footprint)、較薄的外形與較快的信號傳輸速度等多個優點。因此，QFN封裝結構已成為封裝結構的一種風行選擇，且適合具有高頻(例如，射頻頻寬)傳輸之晶片封裝(chip package)。
以QFN封裝結構而言，晶片座與環繞的接觸端子(引腳接墊)是從一片狀的導線架結構中所形成。QFN封裝結構一般是透過表面黏著技術(SMT)而焊接於印刷電路板(printed circuit board,PCB)。此外，QFN封裝結構的晶片座或接觸端子/接墊於封裝製程能力內需要被設計得恰當，以促使長時間良好的接合可靠度。
本發明提供一種先進四方扁平無引腳封裝結構及其 製作方法，可幫助減少晶片座與封裝膠體之間的脫層(delamination)現象與提高產品的可靠度。
本發明提供一種先進四方扁平無引腳封裝結構，其具有一具有一晶片座與多個引腳的載體、一配置於載體上的晶片、多條焊線以及一封裝膠體。引腳包括多個內引腳與多個暴露於封裝膠體外的外引腳。晶片座包括至少一周圍部與一被周圍部圍住的容納槽。至少一容納槽具有一粗糙表面，此粗糙表面可增加晶片座與周圍封裝膠體之間的附著力(adhesion)。焊線配置於晶片與內引腳之間。封裝膠體包覆晶片、晶片座、焊線與內引腳，且填充於容納槽內。
根據本發明之一實施例，載體或晶片座的至少一容納槽可設計為具有一粗糙表面，以提升載體或至少一晶片座與周圍封裝膠體的接合能力(bonding capability)。粗糙表面可為一載體的粗化上表面或形成於載體上之一粗糙材料層的一粗糙頂表面。
本發明更提供一種先進四方扁平無引腳封裝結構的製造方法。提供一具有一上表面以及一下表面的基材，且基材包括至少一容納槽與多個由多個開口之間所定義出的內引腳部。內引腳配置環繞容納槽。接著，對基材的上表面進行一粗化處理，以提供一粗糙表面。藉由電鍍一第一金屬層於內引腳部上與一第二金屬層於基材的下表面上而形成多個內引腳。接著，提供一晶片於基材之容納槽的粗糙表面，且形成多條焊線於晶片與內引腳之間。一封裝膠 體形成於基材上，以覆蓋晶片、焊線與內引腳，且填充於容納槽內。之後，藉由第二金屬層為一蝕刻罩幕來進行一蝕刻製程以蝕穿基材，至填充於開口內之封裝膠體暴露出來為止，以形成多個引腳與一晶片座。
根據本發明之一實施例，粗糙表面可藉由粗化基材的上表面或形成一具有一粗糙表面的粗糙材料層於基材上。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
現將詳細參考本發明之目前較佳實施例，其實例在隨附圖式中說明。在任何可能之處，圖式及描述內容中均使用相同參考編號來指代相同或相似部分。
圖1A至圖1G’為本發明之一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
請參考圖1A，提供一具有一上表面110a以及一下表面110b的基材110。基材110的材料例如為銅、銅合金或其他適用的金屬材料。接著，請再參考圖1A，形成一第一圖案化光阻層114a於基材110的上表面110a上，以及形成一第二圖案化光阻層114b於基材110的下表面110b上。
接著，請參考圖1B，藉由第一圖案化光阻層114a作為一蝕刻罩幕，對基材110的上表面110a進行一半蝕刻製程(half-etching process)，以移除部份基材110且形成至 少一容納槽120與多個第一開口S1。半蝕刻製程例如是一濕式蝕刻製程。同時，第二圖案化光阻層114b可保護基材110的下表面110b。容納槽120a具有一中心部122與一環繞中心部122配置的周圍部124。藉由第一開口S1來定義，以形成多個各自獨立的內引腳部130，且內引腳部130與周圍部124分離。內引腳部130環繞周圍部124配置。內引腳部130可排列成多列、多行或多陣列。周圍部124可視為接地環(ground ring)。
請參考圖1C，藉由遺留的第一圖案化光阻層114a作為一蝕刻罩幕，第二圖案化光阻層114b可用以保護基材110的下表面110b，對基材110所暴露出的上表面110a’進行一粗化處理(繪示為箭頭)，而使得暴露出的上表面110a’變成一粗糙或粗化表面110a”。舉例來說，較佳的粗化表面110a”的粗糙度(roughness)為不小於0.15微米(μm)。此外，粗化表面110a”的粗糙度可依據所選擇的封裝膠體而調整。粗化處理或研磨處理(abrading process)可透過進行一物理處理或一化學處理而達成。物理處理例如是一噴砂處理(sand-blasting process)。化學處理例如是一酸性蝕刻製程或一鹼性蝕刻製程。酸性蝕刻製程可例如使用氯化鐵(ferric chloride)作為蝕刻液。鹼性蝕刻製程可例如使用氯化銨(ammonium chloride)作為蝕刻液。
請參考圖1D，接著圖1C之步驟，移除第一圖案化光阻層114a與第二圖案化光阻層114b之後，形成一第三圖案化光阻層113a於基材110的上表面110a上，以及形成 一第四圖案化光阻層113b於基材110的下表面110b上。第三圖案化光阻層113a填滿容納槽120a與第一開口S1。之後，形成一第一金屬層116a於基材110所暴露出的部份上表面110a’，特別是形成於內引腳部130之被暴露出的表面上，而形成內引腳130’。藉由第四圖案化光阻層113b為一罩幕，形成一第二金屬層116b於基材110被暴露出的下表面110b。在本實施例中，第一金屬層116a與第二金屬層116b的形成方式例如是電鍍。由於形成第一金屬層116a是在形成內引腳部130之後，形成於內引腳部130上之第一金屬層116a可能小於下方內引腳部130，至少內引腳部130之面積的50%。也就是說，第一金屬層116a例如覆蓋下方內引腳部130之中心區域的50%~100%。在此所述之第一金屬層116a或第二金屬層116b可由多個不同群組之非連續圖案或一連續層所組成。第一金屬層116a與第二金屬層116b的材質例如是鎳、鈀或金。較佳地，第一金屬層116a或第二金屬層116b可例如為一金/鎳堆疊層。
內引腳部130與形成於其上的第一金屬層116a可視為內引腳130’。周圍部124與形成於其上的第一金屬層116a可是為一接地環125。同樣地，第二金屬層116b的圖案對應內引腳130’與後續將形成之晶片座。
圖2為本發明之一實施例之一種先進四方扁平無引腳封裝結構隨著製程步驟圖1A、圖1B、圖1C與圖1D的俯視示意圖。為了方便說明起見，省略繪示第三圖案化光阻層113a。內引腳130’環繞載體100的接地環125。從俯視 圖來看，除了內引腳130’與接地環125被第一金屬層116a所覆蓋之外，載體100之其他部分的粗化表面110a”是暴露於外。
此外，請參考圖1C'，於圖1B之步驟後，移除第二圖案化光阻層114b。接著，藉由第一圖案化光阻層114a為一罩幕，形成一粗糙材料層115遮蓋於基材110之暴露出的上表面110’上，且覆蓋容納槽120a的至少一底表面122a(形成第一粗糙表面115a)與第一開口S1的至少一底表面122a(形成第二粗糙表面115b)。依據粗糙材料層115的材料特性，凹穴的側壁與/或開口的側壁不會覆蓋或僅部分覆蓋粗糙材料層115。由於粗糙材料層15之粗糙質地，粗糙材料層115可提供一粗糙表面。形成粗糙材料層的步驟可視為一粗化處理。舉例來說，較佳的粗糙材料層115之粗化表面的粗糙度(roughness)為不小於0.15微米(μm)。粗糙材料層115可為一金屬層，例如是藉由電鍍所形成之鎳或鎳合金層。
請參考圖1D'，接著圖1C’之步驟，移除遺留的第一圖案化光阻層114a之後，形成一第三圖案化光阻層113a於基材110的上表面110a上，以及形成一第四圖案化光阻層113b於基材110的下表面110b上。第三圖案化光阻層113a填滿容納槽120a與第一開口S1，因此覆蓋容納槽120a與第一開口S1內的粗糙材料層115。之後，形成一第一金屬層116a於內引腳部130，以形成內引腳130’。藉由第四圖案化光阻層113b為一罩幕，形成一第二金屬層116b 於基材110之暴露出的部分下表面110b上。在本實施例中，第一金屬層116a與第二金屬層116b的形成方法可包括電鍍。此所述之第一金屬層116a或第二金屬層116b可由多個不同群組之非連續圖案或一連續層所組成。
內引腳部130與形成於其上的第一金屬層116a可一同視為內引腳130’。周圍部124與形成於其上的第一金屬層116a可一同視為一接地環125。同樣地，第二金屬層116b的圖案對應內引腳130’與後續將形成之晶片座。
圖3為本發明之另一實施例之一種先進四方扁平無引腳封裝結構隨著製程步驟圖1A、圖1B、圖1C’與圖1D’的俯視示意圖。為了方便說明起見，省略繪示第三圖案化光阻層113a。內引腳130’環繞載體100的接地環125。從俯視圖來看，除了內引腳130’與接地環125被第一金屬層116a所覆蓋之外，載體100之其他部分被粗糙材料層115所覆蓋。
請參考圖1E，接著圖1D的步驟，移除第三圖案化光阻層113a與第四圖案化光阻層113b。接著，至少一晶片150貼附於每一容納槽120a的中心部122，且一黏著層140位於容納槽120a的中心部122與晶片150之間。提供多條焊線160於晶片150與周圍部124之間，以及晶片150與內引腳130’之間。因此，晶片150透過焊線160而電性連接至接地環125與內引腳130’。
接著，請參考圖1F，形成一封裝膠體180以覆蓋晶片150、焊線160、內引腳130’與周圍部124，且填充於容納 槽120a與第一開口S1。雖然在此是以封裝膠體180為例作說明，但其他適合之封裝體(package body)亦可採用。
由於提高了粗糙度，因此於封裝製程中，封裝膠體180填入於容納槽120a與第一開口S1時，封裝膠體180與粗化表面110”(或粗糙材料層115的粗糙表面115a,115b)之間會形成較強的結合力。如此一來，封裝膠體180與接合表面可達成較佳的附著力，且發生於封裝膠體180與載體100之介面的脫層(delamination)現象亦可減少。
接著，請參考圖1G，藉由第二金屬層116b為一蝕刻罩幕，朝著載體100的下表面110b進行一蝕刻製程，以移除部分基材110，因此基材110被蝕穿至填入於第一開口S1中之封裝膠體180暴露出來為止，且同時形成第二開口S2。擁有對第二開口S2的形成，可定義出多個外引腳136，且使得多個內引腳130’彼此電性絕緣。因此，在蝕刻製程後，形成多個引腳或接觸端子138，其中每一引腳或接觸端子138是由一內引腳130’與對應之外引腳136所組成。此外，蝕刻製程更包括定義載體100的至少一晶片座120。引腳138環繞晶片座120，且晶片座120透過第二開口S2與引腳138電性絕緣。一般來說，引腳138透過此次的蝕刻製程而彼此電性絕緣。一般地，第二金屬層116b的圖案對應或大致上對稱(除了形成晶片座的地方外)第一金屬層116a的圖案。
此外，請參考圖1G'以透過圖1A、圖1B、圖1C’、圖1D’、圖1E以及圖1F的步驟而形成封裝結構，藉由第 二金屬層116b為一蝕刻罩幕，朝著載體100的下表面110b進行蝕刻製程，以移除部份基材110。因此，基材110被蝕穿至填入於第一開口S1中之封裝膠體180暴露出來為止，且同時形成第二開口S2。請參考圖1G’，當移除部份位於第一開口S1內之粗糙材料層115時，位於容納槽120a內之粗糙材料層115仍然留著。依據蝕刻參數，位於第一開口S1內之粗糙材料層115可完全被移除。根據本案所揭示之實施例，例如如圖1G'所示，蝕刻製程可使該周圍部124形成上傾斜部124a、下傾斜部124b以及位於該上傾斜部124a與該下傾斜部124b之間的尖端124c，該下傾斜部124b突出該封裝膠體180，且該上傾斜部124a可選擇性地保留第二粗糙表面115b，而該下傾斜部124b上未包含粗糙表面。
詳細而言，在本實施例中，由於容納槽120a內至少存在有粗糙材料層115，使晶片座120與周圍封裝膠體180之間的結合力可提升。因此，脫層現象可大大減少且可有效提高產品的可靠度。
最後，進行一單體化製程(singulation process)，以得到各自獨立的先進四方扁平無引腳封裝結構。
圖4為本發明之一實施例之一種具有一粗糙材料層之先進四方扁平無引腳封裝結構的剖面示意圖。請參考圖4，先進四方扁平無引腳封裝結構20包括一載體200、一晶片250以及多條焊線260。
在本實施例中，載體200例如是一金屬導線架。詳細 而言，載體200包括一晶片座220與多個引腳(接觸端子)238。引腳238包括多個內引腳230與多個外引腳236。內引腳236與外引腳238是由封裝膠體280來定義。也就是說，被封裝膠體280所覆蓋的部份引腳238定義為內引腳230，而暴露於封裝膠體280外的部分引腳238則定義為外引腳230。
於圖4中，引腳238環繞晶片座220配置，且僅示意地繪示三列/行的引腳238。此外，引腳238的排列並不受上述實施例與圖示所限制，其可依據產品的需要而調整。特別是，內引腳230包括位於其上之第一金屬層216a。容納槽220a內之粗糙材料層215配置於晶片250與晶片座220之間。也就是說，晶片250與一黏著層240貼附於晶片座250上之粗糙材料層215。粗糙材料層215的材料可與黏著層240相容，且粗糙材料層215的材質例如是鎳或鎳合金。第一金屬層216a的材質例如是鎳、金、鈀或上述之組合物。
此外，在本實施例中，先進四方扁平無引腳封裝結構20更包括一封裝膠體280。封裝膠體280包覆晶片250、焊線260與內引腳230，且填滿內引腳230之間的開口S1。此時，外引腳236與晶片座220的底表面暴露於外。封裝膠體280的材質例如為環氧樹脂(epoxy resin)或另一適用的聚合物材料。
另外，在本實施例中，為了符合先進四方扁平無引腳封裝結構20的電性整合化設計要求，載體200更包括至少 一接地環225。接地環225配置於引腳238與晶片座220之間且透過焊線260與晶片250電性連接。當接地環225連接晶片座220，晶片座220與接地環225可一同視為一接地平面(ground plane)。
依據上述實施例之先進四方扁平無引腳封裝結構，粗化表面與粗糙材料層的存在為可提供一粗糙表面，介於封裝膠體與載體之間的附著力，特別是封裝膠體與晶片座的部分，有顯著的提升。
本實施例之先進四方扁平無引腳封裝結構是針對封裝膠體的接合力來設計(介於載體與封裝膠體之間的較強附著力)，以解決脫層問題且提升產品可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧先進四方扁平無引腳封裝結構
100、200‧‧‧載體
110、210‧‧‧基材
110a、110a’‧‧‧上表面
110a”‧‧‧粗糙表面
110b‧‧‧下表面
113a‧‧‧第三圖案化光阻層
113b‧‧‧第四圖案化光阻層
114a‧‧‧第一圖案化光阻層
114b‧‧‧第二圖案化光阻層
115、215‧‧‧粗糙材料層
115a‧‧‧第一粗糙表面
115b‧‧‧第二粗糙表面
116a、216a‧‧‧第一金屬層
116b、216b‧‧‧第二金屬層
120a、220a‧‧‧容納槽
122、222‧‧‧中心部
122a‧‧‧底表面
124‧‧‧周圍部
124a‧‧‧上傾斜部
124b‧‧‧下傾斜部
124c‧‧‧尖端
125、225‧‧‧接地環
130‧‧‧內引腳部
130’、230‧‧‧內引腳
136、236‧‧‧外引腳
138‧‧‧接觸端子
140、240‧‧‧黏著層
150、250‧‧‧晶片
160、260‧‧‧焊線
180、280‧‧‧封裝膠體
220‧‧‧晶片座
238‧‧‧引腳
S1‧‧‧第一開口
S1a‧‧‧底表面
S2‧‧‧第二開口
圖1A至圖1G’為本發明之一實施例之一種先進四方扁平無引腳封裝結構之製造方法的剖面示意圖。
圖2為本發明之一實施例之一種先進四方扁平無引腳封裝結構的俯視示意圖。
圖3為本發明之另一實施例之一種先進四方扁平無引腳封裝結構的俯視示意圖。
圖4為本發明之一實施例之一種具有一粗糙材料層之先進四方扁平無引腳封裝結構的剖面示意圖。
20‧‧‧先進四方扁平無引腳封裝結構
200‧‧‧載體
210‧‧‧基材
215‧‧‧粗糙材料層
216a‧‧‧第一金屬層
216b‧‧‧第二金屬層
220‧‧‧晶片座
220a‧‧‧容納槽
222‧‧‧中心部
225‧‧‧接地環
230‧‧‧內引腳
236‧‧‧外引腳
238‧‧‧引腳
240‧‧‧黏著層
250‧‧‧晶片
260‧‧‧焊線
280‧‧‧封裝膠體
S1‧‧‧第一開口
S2‧‧‧第二開口

Claims (23)

  1. 一種先進四方扁平無引腳封裝結構之製造方法，包括：提供一金屬載體，該金屬載體具有一上表面以及一下表面，其中該金屬載體包括至少一容納槽，該容納槽具有一周圍部、一中心部以及多個由存在於該周圍部與該中心部之間的多個開口所定義出的內引腳部；對該金屬載體的該容納槽與該些開口進行一粗化處理，以分別提供一第一粗糙表面以及一第二粗糙表面；形成一第一金屬層於該些內引腳部與該周圍部上；形成一第二金屬層於該金屬載體的該下表面上；提供一晶片於該金屬載體的該容納槽；形成多個焊線於該晶片與該些內引腳部及該周圍部上的該第一金屬層之間；形成一封裝膠體於該金屬載體上，以覆蓋該晶片、該些焊線、該第一金屬層與該些內引腳部，並填充於該容納槽與該些開口內；以及藉由該金屬載體之該下表面的該第二金屬層作為一蝕刻罩幕來進行一第一蝕刻製程，以蝕穿該金屬載體至填充於該些開口內的該封裝膠體暴露為止，以便形成多個引腳以及一晶片座。
  2. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構之製造方法，其中從該金屬載體的該上表面來提供該金屬載體的步驟，包括： 形成一第一圖案化光阻層於該金屬載體的該上表面上；以及藉由該第一圖案化光阻層作為一蝕刻罩幕，對該金屬載體的該上表面進行一第二蝕刻製程。
  3. 如申請專利範圍第2項所述之先進四方扁平無引腳封裝結構之製造方法，其中進行該粗化處理的步驟，包括：藉由該第一圖案化光阻層作為一蝕刻罩幕，對該金屬載體的該上表面進行一第三蝕刻製程，以粗化該金屬載體所暴露出的該上表面，而形成該粗糙表面。
  4. 如申請專利範圍第3項所述之先進四方扁平無引腳封裝結構之製造方法，其中該第三蝕刻製程為一使用氯化鐵的酸性蝕刻製程。
  5. 如申請專利範圍第3項所述之先進四方扁平無引腳封裝結構之製造方法，其中該第三蝕刻製程為一使用氯化銨的鹼性蝕刻製程。
  6. 如申請專利範圍第2項所述之先進四方扁平無引腳封裝結構之製造方法，其中進行該粗化處理的步驟，包括：藉由該第一圖案化光阻層作為一蝕刻罩幕，對該金屬載體的該上表面進行一噴砂處理，以粗化該金屬載體所暴露出的該上表面，而形成該粗糙表面。
  7. 如申請專利範圍第2項所述之先進四方扁平無引腳封裝結構之製造方法，其中進行該粗化處理的步驟，包 括：形成一粗糙材料層於已圖案化之該金屬載體的該上表面上，以覆蓋該容納槽的該至少一底表面。
  8. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構之製造方法，其中該第一金屬層與該第二金屬層的形成方法包括電鍍。
  9. 如申請專利範圍第1項所述之先進四方扁平無引腳封裝結構之製造方法，於提供該晶片之前，更包括形成一黏著層於該容納槽內。
  10. 一種先進四方扁平無引腳封裝結構，包括：一載體，具有一晶片座以及多個環繞該晶片座配置的引腳，其中該些引腳環繞該晶片座，且該晶片座包括一周圍部以及一容納槽，該周圍部圍住該容納槽；一晶片，配置於該晶片座上，其中該晶片位於該晶片座的該容納槽內且配置於該容納槽的一第一粗糙表面上；多條焊線，配置於該晶片與該些引腳的多個內引腳之間；以及一封裝膠體，包覆該晶片座上的該晶片、該些焊線與該些內引腳，且填充於該晶片座的該容納槽內，其中該晶片座的該周圍部包括一上傾斜部、一下傾斜部以及位於該上傾斜部與該下傾斜部之間的一尖端，該下傾斜部突出該封裝膠體，且一第二粗糙表面選擇性地形成於該上傾斜部上而不形成於該下傾斜部上。
  11. 如申請專利範圍第10項所述之先進四方扁平無 引腳封裝結構，更包括：一第一金屬層，配置於該周圍部的上表面與該些引腳的上表面上；以及一第二金屬層，配置於該晶片座的下表面與該些引腳的下表面上。
  12. 如申請專利範圍第11項所述之先進四方扁平無引腳封裝結構，其中配置於該些引腳之上表面上的該第一金屬層覆蓋該些引腳的上表面。
  13. 如申請專利範圍第10項所述之先進四方扁平無引腳封裝結構，其中該周圍部為一接地環，且該接地環透過該些導線與該晶片電性連接。
  14. 如申請專利範圍第10項所述之先進四方扁平無引腳封裝結構，更包括一黏著層，配置於該晶片與該第一粗糙表面之間。
  15. 如申請專利範圍第10項所述之先進四方扁平無引腳封裝結構，其中該封裝膠體直接連接於該容納槽的該第一粗糙表面。
  16. 如申請專利範圍第10項所述之先進四方扁平無引腳封裝結構，其中該第一粗糙表面的粗糙度不小於0.15微米。
  17. 一種先進四方扁平無引腳封裝結構，包括：一載體，具有一晶片座以及多個環繞該晶片座配置的引腳，其中該些引腳環繞該晶片座，且該晶片座包括一周圍部以及一容納槽，該周圍部圍住該容納槽，而該容納槽 包括形成於其上的一粗糙材料層，該粗糙材料層的一頂表面為一粗糙表面，其中該粗糙材料層的材質不同於該載體的材質；一晶片，配置於該晶片座上，其中該晶片位於該晶片座的該容納槽內且配置於位於該容納槽內之該粗糙材料層的該粗糙表面上；多條焊線，配置於該晶片與該些引腳的多個內引腳之間；以及一封裝膠體，包覆該晶片座上的該晶片、該些焊線與該些內引腳，且填充於該晶片座的該容納槽內。
  18. 如申請專利範圍第17項所述之先進四方扁平無引腳封裝結構，更包括：一第一金屬層，配置於該周圍部的上表面與該些引腳的上表面上；以及一第二金屬層，配置於該晶片座的下表面與該些引腳的下表面上。
  19. 如申請專利範圍第18項所述之先進四方扁平無引腳封裝結構，配置於該些引腳之上表面上的該第一金屬層覆蓋該些引腳的上表面。
  20. 如申請專利範圍第17項所述之先進四方扁平無引腳封裝結構，更包括一黏著層，配置於該晶片與粗糙材料層的該頂表面之間。
  21. 如申請專利範圍第17項所述之先進四方扁平無引腳封裝結構，其中該封裝膠體直接連接於位於該容納槽內之該粗糙材料層的該頂表面。
  22. 如申請專利範圍第17項所述之先進四方扁平無引腳封裝結構，其中該粗糙材料層的材質包括鎳。
  23. 如申請專利範圍第17項所述之先進四方扁平無引腳封裝結構，其中該粗糙表面的粗糙度不小於0.15微米。
TW098143935A 2009-04-10 2009-12-21 先進四方扁平無引腳封裝結構及其製造方法 TWI587414B (zh)

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