FR3089055B1 - Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. - Google Patents
Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. Download PDFInfo
- Publication number
- FR3089055B1 FR3089055B1 FR1871795A FR1871795A FR3089055B1 FR 3089055 B1 FR3089055 B1 FR 3089055B1 FR 1871795 A FR1871795 A FR 1871795A FR 1871795 A FR1871795 A FR 1871795A FR 3089055 B1 FR3089055 B1 FR 3089055B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- flexible
- carrier
- module
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
- G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H01L23/49541—Geometry of the lead-frame
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Theoretical Computer Science (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
L’invention concerne un procédé de fabrication d’un support (2) flexible de circuit intégré (7). Ce procédé comprend la réalisation d’au moins une cavité (12) sur la première face principale (13a) d’une feuille de matériau conducteur (13), préalablement à la fixation d’au moins un circuit intégré (7) dans cette cavité (12). L’invention concerne également un support (2) flexible de circuit intégré (7) réalisé selon ce procédé et un module comprenant un support (2) et un circuit intégré (7) logé dans la cavité (12). Figure à publier avec l’abrégé : Fig 4
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1871795A FR3089055B1 (fr) | 2018-11-23 | 2018-11-23 | Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. |
PCT/FR2019/052797 WO2020104759A1 (fr) | 2018-11-23 | 2019-11-25 | Procédé de fabrication d'un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1871795A FR3089055B1 (fr) | 2018-11-23 | 2018-11-23 | Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3089055A1 FR3089055A1 (fr) | 2020-05-29 |
FR3089055B1 true FR3089055B1 (fr) | 2021-08-27 |
Family
ID=66690456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1871795A Active FR3089055B1 (fr) | 2018-11-23 | 2018-11-23 | Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR3089055B1 (fr) |
WO (1) | WO2020104759A1 (fr) |
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US6585905B1 (en) * | 1998-06-10 | 2003-07-01 | Asat Ltd. | Leadless plastic chip carrier with partial etch die attach pad |
US6452255B1 (en) * | 2000-03-20 | 2002-09-17 | National Semiconductor, Corp. | Low inductance leadless package |
JP2006253732A (ja) * | 2000-12-28 | 2006-09-21 | Renesas Technology Corp | 半導体装置 |
TW200425427A (en) * | 2003-05-02 | 2004-11-16 | Siliconware Precision Industries Co Ltd | Leadframe-based non-leaded semiconductor package and method of fabricating the same |
US20050230842A1 (en) * | 2004-04-20 | 2005-10-20 | Texas Instruments Incorporated | Multi-chip flip package with substrate for inter-die coupling |
US7091581B1 (en) * | 2004-06-14 | 2006-08-15 | Asat Limited | Integrated circuit package and process for fabricating the same |
CN200944402Y (zh) * | 2006-03-10 | 2007-09-05 | 上海长丰智能卡有限公司 | 一种集成电路封装用载带 |
US8174096B2 (en) * | 2006-08-25 | 2012-05-08 | Asm Assembly Materials Ltd. | Stamped leadframe and method of manufacture thereof |
CN101447036B (zh) * | 2007-11-28 | 2012-05-23 | 上海长丰智能卡有限公司 | 一种非接触智能电子标签用微型模块及载带 |
TWI398933B (zh) * | 2008-03-05 | 2013-06-11 | Advanced Optoelectronic Tech | 積體電路元件之封裝結構及其製造方法 |
US8673687B1 (en) * | 2009-05-06 | 2014-03-18 | Marvell International Ltd. | Etched hybrid die package |
CN102013419A (zh) * | 2009-09-08 | 2011-04-13 | 上海长丰智能卡有限公司 | 一种微型射频模块封装用载带 |
CN102148213B (zh) * | 2011-03-08 | 2014-06-04 | 日月光半导体(威海)有限公司 | 高功率芯片封装构造的导线架及其制造方法 |
DE202012100694U1 (de) | 2012-02-29 | 2012-03-30 | Heraeus Materials Technology Gmbh & Co. Kg | Substrat mit vergrößerter Chipinsel |
US8674487B2 (en) * | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
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2018
- 2018-11-23 FR FR1871795A patent/FR3089055B1/fr active Active
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2019
- 2019-11-25 WO PCT/FR2019/052797 patent/WO2020104759A1/fr active Application Filing
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WO2020104759A1 (fr) | 2020-05-28 |
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