CN106711113B - 具有集成散热片的半导体封装体 - Google Patents

具有集成散热片的半导体封装体 Download PDF

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Publication number
CN106711113B
CN106711113B CN201610145000.XA CN201610145000A CN106711113B CN 106711113 B CN106711113 B CN 106711113B CN 201610145000 A CN201610145000 A CN 201610145000A CN 106711113 B CN106711113 B CN 106711113B
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leads
bare chip
semiconductor
package body
semiconductor bare
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CN106711113A (zh
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E·M·卡达格
J·塔利多
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STMicroelectronics International NV
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STMicroelectronics Inc Philippines
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Abstract

一个或多个实施例涉及具有集成散热片的半导体封装体以及形成这些半导体封装体的方法。在一个实施例中，封装体包括多根引线，这些引线支撑并封闭该半导体裸片的多个周边部分。这些引线具有形成该封装体的多个外表面的第一和第二相对的表面。这些引线的第一表面可以形成散热片而这些引线的第二表面形成该封装体的用于耦接至另一个器件、衬底或板上的多个焊区。该封装体包括包封材料，该包封材料包围该半导体裸片并且位于这些引线的这些上部部分之间。该封装体进一步包括后部填充材料(或绝缘材料)，该后部填充材料在该半导体裸片下方并且在这些引线的这些下部部分之间。

Description

具有集成散热片的半导体封装体
技术领域
本披露的实施例涉及半导体封装体和装配半导体封装体的方法。
背景技术
在期望小尺寸封装体的应用中经常使用无引线的(或没有引线的)封装体。通常，扁平无引线封装体提供由平坦引线框形成的近芯片级包封的封装体。位于封装体的底表面上的焊区提供到板(例如印刷电路板(PCB))上的电连接。
通常，无引线封装体包括被安装至裸片焊盘上并且如通过导电线电性地耦接至引线的半导体裸片或芯片。使封装体更薄的改进已经消除了对裸片焊盘的需要。具体地，引线上芯片(COL)封装体在没有裸片焊盘的情况下使半导体裸片直接安装在引线上。
目前针对半导体封装的应用期望具有减小的厚度的封装体，同时高效地去除由封装体中的半导体裸片产生的热量。
发明内容
一个或多个实施例涉及具有集成散热片的半导体封装体以及形成这些半导体封装体的方法。在一个实施例中，封装体包括多根引线，这些引线支撑并封闭该半导体裸片的多个周边部分。这些引线具有形成该封装体的多个外表面的第一和第二相对的表面。这些引线的第一表面可以形成散热片而这些引线的第二表面形成该封装体的用于耦接至另一个器件、衬底或板上的多个焊区。该封装体包括包封材料，该包封材料包围该半导体裸片并且位于这些引线的这些上部部分之间。该封装体进一步包括后部填充材料(或绝缘材料)，该后部填充材料在该半导体裸片下方并且在这些引线的这些下部部分之间。
附图说明
在这些附图中，相同的参考号标识相似的元件。未必按比例绘制附图中的元件的尺寸和相对位置。
图1A至图1D是根据本披露的一个实施例的无引线封装体的各个视图的示意性展示。
图2是图1A至图1D中的附接至板上的封装体的示意性展示的横截面视图。
图3A至图3H展示了根据本披露的实施例的形成引线框条带的各个阶段。
图4A至图4F展示了根据本披露的实施例的用于形成封装体(如图1A至图1D的封装体)的装配工艺的各个阶段的横截面视图。
图5A至图5C是根据本披露的另一个实施例的无引线封装体的各个视图的示意性展示。
图6A至图6F展示了根据本披露的另一个实施例的用于形成封装体(如图5A至图5C的封装体)的另一个装配工艺的各个阶段的横截面视图。
图7A至图7F展示了根据本披露的又一个实施例的用于形成封装体(如图5A至图5C的封装体)的另一个装配工艺的各个阶段的横截面视图。
具体实施方式
应当理解的是，虽然出于说明性目的在此描述了本披露的具体实施例，但是可在不脱离本披露的精神和范围的情况下做出各种修改。
在以下说明中，陈述了某些具体细节以便提供对所披露的主题的不同方面的全面理解。然而，所披露的主题可以在没有这些具体细节的情况下实施。在一些实例中，尚未对包括在此所披露的主题的实施例的众所周知的半导体加工结构和方法进行详细描述以避免模糊本披露的其他方面的描述。
图1A至图1C是根据本披露的一个实施例的无引线封装体10的横截面视图。图1B是图1A的封装体10的俯视平面图，而图1C是图1A的封装体10的仰视平面图。
如在图1A中最佳地示出的，封装体10包括第一表面12和第二相对的表面14以及多根引线16，这些引线具有从第一表面12延伸至第二表面14的多个部分。半导体裸片18位于多根引线16之间并且由这多根引线16支撑。具体地，半导体裸片18位于多根引线16的上部部分20之间并且由该多根引线16的下部部分22支撑。
如在图1B和图1C中示出的，封装体10包括沿着两侧延伸至封装体的周边的六根引线。然而，该封装体可以包括位于任意数量的侧面上的任意数量的引线。
如在图1B中最佳示出的，在封装体10的第一表面12处，这些引线16中的每一根引线包括上表面24，该上表面是平面的并且形成封装体10的第一表面12的一部分。如在图2中示出的，每根引线16的上表面24形成焊区，该焊区被配置成用于电性地耦接至另一个器件或板，如印刷电路板。如在图1C中最佳示出的，在封装体10的第二表面14处，这些引线16中的每一根引线形成封装体10的多个外侧表面，该封装体包括下表面26，该下表面是平面的并且形成封装体10的第二表面14的一部分。
每根引线16的下表面26保持外露并且充当耗散由半导体裸片18产成的热量的散热片。在封装体10的侧表面处，引线16从封装体10的第一表面12延伸至封装体10的第二表面14并且具有基本上对应于封装体10的总厚度的厚度。如在图1A中最佳地示出的，引线16的下部部分22具有在封装体10的内部的内表面25。
半导体裸片18的后表面30通过粘合剂材料32耦接至引线16的内表面25。粘合剂材料32可以是被配置成用于将裸片18固定于引线16的下部部分22的内表面25的任何材料，如粘胶、粘膏、胶带、环氧树脂或任何合适的材料。引线16的下部部分22具有用于提供合适的强度以支撑半导体裸片18的厚度。
半导体裸片18是包括电子器件(如集成电路或机电传感器)的任何半导体裸片。半导体裸片18具有与后表面30相对的前表面34。前表面34包括多个键合焊盘，这些键合焊盘可以位于前表面34的周边。通过导电线36将半导体裸片18电性地耦接至引线16的下部部分22。例如，导电线36的第一端被耦接至裸片18的键合焊盘，并且导电线的第二端被耦接至引线16的下部部分22的内表面25。导电线36可以是将半导体裸片18电性地耦接至引线16的任何导电材料。
引线16的上表面24和下表面22可以被镀上一个或多个导电层40。该一个或多个导电层40是纳米层或微层，并且可以是任何导电材料制成。在一个实施例中，一个或多个导电层40是多个堆叠的金属层，如Ni/Pd/Ag、Ni/Pd/Au-Ag合金或Ni/Pd/Au/Ag。如将于下文解释的，一个或多个导电层40可以形成掩模层，该掩模层用于在装配工艺过程中蚀刻引线框条带的多个部分以形成封装体的这些引线。
包封材料42包封半导体裸片18和导电线36以及引线16的上部部分20的侧表面。包封材料42形成封装体10的第一表面12和侧表面的一部分。包封材料42是绝缘材料，保护半导体裸片的电气部件和导电线不受损坏，如腐蚀、物理损坏、湿气损坏或对电气器件和材料的损坏的其他原因。在一个实施例中，包封材料42是聚合物，如环氧树脂模。
在封装体10的第二表面14处，在半导体裸片18和包封材料42下方并且在这些引线16的下部部分22之间的是后部填充材料44。后部填充材料44是绝缘材料并且可以是环氧树脂、硅、光刻胶、具有低模量特性的任何材料或者任何合适的材料。
如在图1C中最佳示出的，后部填充材料44在封装体10的第二表面14处填充这些引线16的下部部分22之间的空间并且使这些引线16的下部部分22彼此电性地隔离。后部填充材料44抵靠着半导体裸片18后表面30(或粘合剂材料32)和包封材料42。此外，后部填充材料44抵靠着这些引线16的下部部分22的侧表面。后部填充材料44可以被配置成用于提供对封装体10的电气部件的附加机械支撑和/或保护。
应当理解，封装体10的总厚度与用于形成封装体的引线框的厚度相同。在一个实施例中，引线框厚度(即，封装体的厚度)约为0.2毫米。
图2展示了图1A至图1D的安装在板(如印刷电路板(PCB)46)上的封装体10。封装体10的第一表面12面向PCB 46的表面。因此，这些引线16的上表面24在图2中面向下方以耦接至PCB 46。也就是，如在本领域中众所周知的，这些引线16的上表面24通过在其之间的导电凸块48电性地和机械地耦接至PCB 46的多个焊区。可以在封装体10的第一表面12与PCB 46之间提供底部填充材料(未示出)。引线16的下表面26背向PCB 46并且充当散热片以将由半导体裸片18产生的热量耗散至外部环境。在一个实施例中，引线16的下表面26占据了封装体10的第二表面14的50％至70％。就此而言，引线16的下部部分22充当集成散热片，用于去除从封装体10产生的热量并将该热量转移至外部环境。因此，其中集成了散热片的封装体10的总厚度远小于散热片安装在封装体上的厚度。
图3A至图3G展示了根据本披露的实施例在各个制造阶段被形成引线框条带50的导电箔52的一部分的横截面视图，并且图3H展示了图3G的引线框条带的等距视图。在图3G和图3H中示出的引线框条带50可以用于制作图1的引线框封装体10。
图3A示出了导电箔52，该导电箔是用于形成引线框条带50的基材。导电箔52是任何导电材料，并且可以是金属材料，如铜或铜合金。导电箔52具有上表面54和相对的下表面56。
如在图3B中示出的，光敏材料58(如光刻胶)是在导电条带50的第一表面54和第二表面56上沉积的覆盖层。如在图3C中示出的，光敏材料58被图案化以形成本领域中众所周知的掩模层。光敏材料58可以是正性或负性光刻胶。例如，在一个实施例中，光敏材料58的多个部分可以外露于紫外线辐射下并且然后被光刻胶显影剂去除，从而使导电箔52的外露部分60留在第一表面54和第二表面56上。
如在图3D中示出的，使用已知技术将一个或多个导电层40电镀于导电箔52的外露部分60上。电镀可以包括电镀一个或多个导电层40，其可以是一叠金属层，如Ni/Pd/Ag、Ni/Pd/Au-Ag合金、Ni/Pd/Au/Ag或任何其他堆叠。替代地，该一个或多个导电层可以是单层，如单金属层。
如在图3E中示出的，在区域62处将光敏材料58从第一表面去除。光敏材料58保留在第一表面54和第二表面56的其他区域上。该一个或多个导电层40与光敏材料58一起形成掩模层。如在图3F中示出的，如本领域中众所周知的，导电箔在区域62处的上表面被蚀刻以形成开口64。如将在以下更加详细解释的，导电箔被蚀刻大于半导体裸片的厚度的距离以被装配于其中。在一个实施例中，导电箔被蚀刻介于导电箔厚度的50％与80％之间，并且在一个实施例中被蚀刻导电箔的70％。在一个实施例中，导电箔52可以通过浸入蚀刻剂浴中而被蚀刻并且在一些情况中包括搅拌技术。
如将参照展示了装配工艺的图4A至图4F更加详细解释的，导电箔52的开口64形成内表面25，其一部分是图1A至图1D的引线的下部部分26，而第一表面54的凸起的非蚀刻部分形成图1A至图1D的引线的上部部分20。最后，如在图3G中示出的，从导电箔52的第一表面54和第二表面56上去除光敏材料64，由此形成引线框条带50供在装配过程中使用。
图3H是引线框条带50的等距视图。如在图3H中示出的，在图3F的蚀刻步骤形成的开口64在引线的相邻上部部分20之间延伸。引线框条带50具有由内表面25和第二表面56限定的第一厚度以及由引线的上部部分20和第二表面56限定的第二厚度。这些引线的上部部分20通过连接部分66保持为彼此耦接。这些引线的内表面25通过内连接部分67耦接在一起。
图4A至图4F展示了根据本披露的一个实施例的装配封装体(如图1A至图1D的封装体10)的各个阶段的横截面视图。图4A示出了引线框条带50，如图3G至图3H的引线框条带50。
如在图4B中示出的，半导体裸片18耦接至引线的上部部分20之间的引线框条带50的内表面25和内连接部分67。例如，在将半导体裸片18放置在内表面25上之前，粘合剂材料32可以被放置在半导体裸片18的底表面30上和/或在引线框条带50的内表面25上。
通过导电线36使用标准接线键合技术，半导体裸片18电性地耦接至该组引线。也就是说，分别地，导电线36的第一端耦接至半导体裸片18的键合焊盘，而导电线36的第二端耦接至引线框条带50在半导体裸片18与引线的上部部分20之间的内表面25上。
如在图4C中示出的，使用常规技术围绕半导体裸片18和导电线36形成包封材料42。例如，包封材料可以在模制工艺中被模制。应当理解，引线框条带50不包括延伸至下表面的贯通开口。因此，围绕半导体裸片18形成的包封材料42不流过引线框条带50的下表面。包封材料42被模制在引线框条带50的内表面25之上以及在引线的上部部分20之间。包封材料42随着时间推移而硬化，并且可以在固化步骤中硬化。
在图4D中，引线框条带50被翻转，从而使得引线框条带50的下表面面朝上。使用已知的引线框蚀刻技术从下表面蚀刻引线框条带50的多个部分。在蚀刻步骤过程中，引线框条带50的上表面和下表面上的一个或多个导电层40充当蚀刻图案。因此，引线框条带50在其上具有一个或多个导电层40的这些部分不被蚀刻，而引线框材料50所外露的区域被蚀刻掉。因此，内连接部分67被蚀刻以使半导体裸片18(或粘合剂材料)外露。此外，相邻封装体的引线之间的连接部分66被蚀刻。尽管未在横截面视图中示出，但对引线框条带50的蚀刻将封装体内的相邻引线之间的引线框材料(如延伸进入并离开页面的那些)分开。
在单独封装体的相邻引线之间形成的包封材料42保留在相邻封装体的引线之间；然而，包封材料42的厚度是如参照图3E所描述的边缘的深度的厚度。如将于以下讨论的，在相邻封装体之间的包封材料42形成划切轨道用于单一切割单独的封装体。
如在图4E中示出的，在半导体裸片18的后表面30上并且在参照图4D所描述的蚀刻步骤中外露的包封材料42之上沉积后部填充材料44。如以上所讨论的，后部填充材料44是绝缘材料并且可以是环氧树脂、硅、光刻胶、具有低模量特性的材料、或者任何其他合适的材料。
如在图3F中所示，装配工艺进一步包括将每个封装体10分隔成单独的封装体10。封装体10可以通过各种切割方法(包括锯切、冲切以及激光)被分开。包封材料42和/或后部填充材料44可以用作划切轨道，该划切轨道作为针对切割工具的视觉对准。
应当认识到，以上方法在装配工艺过程中不要求支撑结构或胶带背衬材料。也就是，引线框条带50足够硬到支撑该装配工艺。应注意的是，引线框条带不具有贯通整个材料厚度延伸的贯通开口，这可以减少引线框条带的硬度。
此外，本文中所描述的装配工艺涉及切割透包封材料42和/或后部填充材料44，这些材料相比于引线框材料更易于被切割透。因此，通过使用蚀刻步骤来分隔这些引线并然后切割透包封材料42和/或后部填充材料44可以获得许多益处。具体地，切割透包封材料42和/或后部填充材料44而不必切割透引线框材料可以阻止或减少在引线的表面上形成锯切毛边。也就是说，已知切透引线框材料会导致锯切毛边。此外，在蚀刻步骤过程中分隔引线进一步消除引线拖尾，该引线拖尾与锯片切割透引线框材料相关联。此外，通过锯切透包封材料和/或后部填充材料，可以增加锯切速度，由此通过锯切工具提高生产量。此外，用于将封装体切成单独的封装体的锯片的刀片寿命将增加。此外，还可以使用通过冲切的单一切割。
图5A至图5C展示了根据本披露的另一个实施例的无引线封装体10a。图5A至图5C的无引线封装体10a在结构和针对图1A至图1D的无引线封装体10的装配加工上基本上相同并且因此为了简洁起见将不重复那些特征。图5A至图5C的封装体10a与图1A至图1D的封装体10的不同之处在于，引线16不延伸至封装体10a的边缘并且半导体裸片18以倒装芯片安排被附接于这些引线。具体地，半导体裸片18的第一表面面向引线16的下部部分22的内表面25。导电凸块70(如焊料凸块)将半导体裸片18的键合焊盘电性地耦接于引线16的下部部分22的内表面25。应理解的是，本文中所描述的任何实施例可以涉及以倒装芯片安排或通过接线键合将半导体裸片18安装在引线16上。也就是说，如本领域众所周知的，可以用倒装芯片配置将封装体10中的裸片电性地耦接于这些引线，并且可以通过接线键合将封装体10a中的裸片电性地耦接于这些引线。
如以上所指示的，封装体10a的引线16不延伸至封装体10a的边缘。而且，如在图5B和图5C中示出的，包封材料42和后部填充材料44位于封装体10a的周边周围。
图6A至图6F展示了根据本披露的另一个实施例的装配封装体10a的各个阶段的横截面视图。概括地描述，图6A至图6F的装配工艺与图4A至图4G的装配工艺不同之处在于，引线框材料在划切轨道中未被完全地蚀刻掉。此外，引线16被形成使得它们不延伸至封装体10a的侧表面。而且，引线16是后拉配置，因为这些引线从封装体的边缘偏移并且包封材料42和后部填充材料44位于封装体的边缘或侧表面处。应理解的是，后拉引线可以与也参照图4A至图4F描述的装配工艺一起被利用。最后，以倒装芯片配置将半导体裸片18电性地和机械地耦接于引线16。
如在图6A中示出的，引线框条带50a可以被形成为具有位于划切轨道的相对侧上的引线16的外部的多个空腔72。可以在任何阶段(包括在加工引线框条带50时)形成这些空腔72。例如，如将对本领域普通技术人员而言清楚的是，参照图3E，可以在开口64被蚀刻的同时形成这些空腔。替代地，空腔72可以在之后的步骤中被蚀刻。
如在图6B中示出的，如本领域众所周知的，以倒装芯片安排将半导体裸片18耦接于引线框条带50a在引线16的上部部分20之间的内表面25。例如，导电凸块70可以耦接于半导体裸片18的键合焊盘并且然后被安装于引线16上。可以在半导体裸片18与引线16的内表面25之间提供底部填充材料(未示出)。
如在图6C中示出的，围绕半导体裸片18形成包封材料42。也在空腔72中模制包封材料42。
如在图6D中示出的，引线框条带50a被翻转过来，从而使得引线框条带的下表面面向上并且从该下表面蚀刻引线框条带50a的多个部分。具体地，外露且未被一个或多个导电层40覆盖的引线框材料的多个部分被蚀刻。例如，内连接部分67被蚀刻以使半导体裸片18外露。此外，连接部分66也被蚀刻。然而，如在图6D中示出的，连接部分66未被完全蚀刻透而仅蚀刻到一半。
如在图6E中示出的，在半导体裸片18之上以及在被填充至空腔中的包封材料42之上沉积后部填充材料44。尽管未示出，可以在保留的引线框材料的连接部分66之上沉积后部填充材料44。
参照图6F，该方法包括将每个封装体分隔成单独的封装体10a。
图7A至图7F展示了根据本披露的另一个实施例的装配封装体10a的各个阶段的横截面视图。概括地描述，图7A至图7F的装配工艺与图6A至图6F的装配工艺基本上相同。然而，不同之处在于当形成开口64时，还形成了开口69而不是空腔72。开口69位于相邻封装体的相邻引线20之间。如在图7C中示出的，在围绕半导体裸片18的开口64中形成包封材料42的同一步骤过程中，包封材料42填充开口69。因此，在图7D的蚀刻步骤过程中，在相邻封装体之间去除所有引线框材料从而外露出下面的包封材料42。如在图7E中示出的，在相邻封装体之间在外露的包封材料42之上沉积后部填充材料44。在图7F中示出的单一切割可以通过切割或冲压透包封材料42而发生。
上述各实施例可以被组合以提供进一步的实施例。在本说明书中所提及的和/或在申请资料表中所列出的所有美国专利、美国专利申请出版物、美国专利申请、国外专利、国外专利申请和非专利出版物都以其全文通过引用并入本文。如有必要，可以对实施例的各方面进行修改，以利用各专利、申请和出版物的概念来提供更进一步的实施例。
鉴于以上详细说明，可以对实施例做出这些和其他变化。总之，在以下权利要求书中，所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例，而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。因此，权利要求书并不受到本披露的限制。

Claims (22)

1.一种半导体封装体，包括：
引线框架的多根引线，所述多根引线具有带有多个上部外表面的多个上部部分、带有多个下部外表面的多个下部部分以及多个内表面；
半导体裸片，所述半导体裸片具有第一表面和第二表面，所述半导体裸片位于所述多根引线的所述多个上部外表面与所述多个下部外表面之间，所述半导体裸片的所述第二表面的周边部分耦接至所述多根引线的所述多个内表面；
多个导电耦接元件，所述多个导电耦接元件将所述半导体裸片电性地耦接至所述多根引线的所述多个内表面；
包封材料，所述包封材料围绕所述半导体裸片的所述第一表面、所述多个导电耦接元件、并且处在所述多根引线的所述多个上部部分之间；以及
介于所述多根引线的所述多个下部部分之间的绝缘材料，所述绝缘材料是与所述包封材料不同的材料，所述绝缘材料支撑所述半导体裸片的所述第二表面的中心部分，所述多根引线的所述多个下部部分的所述多个下部外表面占据所述半导体封装体的下表面的50％到70％，并且所述多根引线的所述多个下部部分用作热沉。
2.如权利要求1所述的半导体封装体，其中，所述绝缘材料是环氧树脂、硅或光刻胶。
3.如权利要求1所述的半导体封装体，其中，所述多根引线延伸至所述封装体的多个侧表面。
4.如权利要求1所述的半导体封装体，其中，所述包封材料和所述绝缘材料具有彼此抵靠的多个表面。
5.如权利要求1所述的半导体封装体，其中，所述多根引线从所述封装体的多个外表面偏移。
6.如权利要求1所述的半导体封装体，进一步包括在所述半导体裸片的所述第二表面的所述中心部分与所述绝缘材料之间的粘合剂材料。
7.一种半导体封装体，包括：
引线框架的多根引线，所述多根引线具有多个上部部分和多个下部部分，所述多个下部部分包括多个内表面；
半导体裸片，所述半导体裸片位于所述多根引线的所述多个上部部分之间，所述半导体裸片耦接至所述多根引线的所述多个下部部分的所述多个内表面；
多个导电耦接元件，所述多个导电耦接元件将所述半导体裸片电性地耦接至所述多根引线的所述多个下部部分的所述多个内表面；
包封材料，所述包封材料围绕所述半导体裸片、所述多个导电耦接元件、并且处在所述多根引线的所述多个上部部分之间；以及
介于所述多根引线的所述多个下部部分之间的绝缘材料，其中所述绝缘材料是与所述包封材料不同的材料，所述多根引线的所述多个下部部分的多个下部外表面占据所述半导体封装体的下表面的50％到70％，并且所述多根引线的所述多个下部部分用作热沉。
8.如权利要求7所述的半导体封装体，其中，所述绝缘材料面向所述半导体裸片的表面。
9.如权利要求8所述的半导体封装体，其中，所述多根引线的所述多个下部部分具有与所述绝缘材料共面的表面。
10.如权利要求8所述的半导体封装体，其中，所述封装体的多个侧表面包括抵靠着所述绝缘材料的所述包封材料。
11.如权利要求8所述的半导体封装体，其中，所述绝缘材料是环氧树脂、硅或光刻胶。
12.如权利要求7所述的半导体封装体，其中，所述多个导电耦接元件是多个导电凸块，所述多个导电凸块具有耦接至所述半导体裸片的多个键合焊盘上的多个第一端以及耦接至所述多根引线的所述多个下部部分的所述多个内表面上的多个第二端。
13.如权利要求7所述的半导体封装体，其中，所述导电耦接元件是多条导电线，所述多条导电线具有耦接至所述半导体裸片的多个键合焊盘上的多个第一端以及耦接至所述多根引线的所述多个下部部分的所述多个内表面上的多个第二端。
14.如权利要求7所述的半导体封装体，其中，所述多根引线在所述封装体的多个侧表面处是外露的。
15.一种方法，包括：
将半导体裸片的第一表面的外周部分耦接至引线框架的多根引线的多个下部部分的多个内表面，其中，所述半导体裸片位于所述多根引线的多个上部部分之间；
用包封材料包封所述半导体裸片并且在所述多根引线的多个上部部分之间；并且
在所述半导体裸片的所述第一表面之上并且在所述多根引线的多个下部部分之间沉积绝缘材料，以形成半导体封装体，所述绝缘材料是与所述包封材料不同的材料，其中所述多根引线的所述多个下部部分的多个下部外表面占据所述半导体封装体的下表面的50％到70％，并且所述多根引线的所述多个下部部分用作热沉。
16.如权利要求15所述的方法，其中，耦接包括通过多个耦接导电凸块将所述半导体裸片电性地和机械地耦接至所述多根引线的所述多个下部部分的所述多个内表面。
17.如权利要求15所述的方法，其中，包封包括在所述多根引线的多个上部部分与所述多根引线的多个外露表面之间进行包封。
18.如权利要求15所述的方法，其中，沉积绝缘材料包括沉积环氧树脂、硅或光刻胶中的至少一者。
19.如权利要求15所述的方法，其中，所述多根引线的所述多个下部部分包括多个连接部分，所述方法进一步包括在沉积所述绝缘材料之前去除在所述多根引线的所述多个下部部分之间的多个连接部分。
20.如权利要求19所述的方法，其中，在围绕所述多根引线的周边的多个划切轨道中去除多个连接部分。
21.如权利要求19所述的方法，其中，去除多个连接部分包括蚀刻在所述多根引线的所述多个下部部分之间的所述多个连接部分并且使在所述半导体裸片的所述第一表面处的粘合剂材料外露。
22.如权利要求19所述的方法，其中，去除多个连接部分使所述包封材料的多个表面外露。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750545B1 (en) * 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
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* Cited by examiner, † Cited by third party
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US6707149B2 (en) * 2000-09-29 2004-03-16 Tessera, Inc. Low cost and compliant microelectronic packages for high i/o and fine pitch
DE60304651T2 (de) * 2002-10-15 2007-05-10 Dainippon Ink And Chemicals, Inc. Epoxidharzzusammensetzung und Verfahren zur Herstellung von Epoxidharzen
SG132533A1 (en) 2005-11-21 2007-06-28 St Microelectronics Asia Ultra-thin quad flat no-lead (qfn) package and method of fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750545B1 (en) * 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
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