TWI556370B - 半導體封裝及用於其之方法 - Google Patents

半導體封裝及用於其之方法 Download PDF

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TWI556370B
TWI556370B TW103135955A TW103135955A TWI556370B TW I556370 B TWI556370 B TW I556370B TW 103135955 A TW103135955 A TW 103135955A TW 103135955 A TW103135955 A TW 103135955A TW I556370 B TWI556370 B TW I556370B
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wire
width
conductive
solder
semiconductor package
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TW103135955A
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TW201519380A (zh
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江詳燁
鄭季洋
金秉進
朴音貝
貝捷民
朴諾孫
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艾馬克科技公司
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Description

半導體封裝及用於其之方法
在此揭示的具體態樣大致關於電子封裝，更特別的是關於半導體封裝及其製造方法，其中結構改善了用於接合覆晶導線框和電子裝置的焊料接合以具有增強的耦合力。
一般而言，導線框是一種用於製造半導體封裝的基板。導線框是此種封裝的中央支撐結構，並且典型而言是以化學蝕刻或機械壓印金屬條所製造。導線框典型而言包括界定整個框架的側框、用於安裝一或更多個半導體晶片的晶片墊、將側框整合連接到晶片墊的一或更多根繫棒、從側框延伸而相鄰於或靠近晶片墊各側的多根導線。部分的導線框是在封裝本體的內部或被塑性包封劑(例如模製化合物)所完全包圍。導線框的部分導線可以從封裝本體向外延伸或者可以在當中部分暴露，以用於將封裝電連接到另一構件。於特定的半導體封裝中，導線框的部分晶粒墊也在封裝本體裡保持暴露。
有一類的半導體封裝稱為近晶片規模封裝(chip scale package，CSP)，其包括極薄細的間距和近似半導體晶片尺寸的小面積導線框。此種封裝包括MicroLeadFrame®(MLF，微導線框)型的封裝。這些封裝典型而言具有範圍從1毫米到13毫米的封裝本體尺寸和範圍從0.3毫米到2.1 毫米的封裝高度。為了提升單位生產力，例如MLF型封裝的近晶片規模封裝係組裝成多重導線框的矩陣並且包封於頂模製過程。然後典型而言使用切鋸過程而將個別的MLF結構分開成單獨的封裝，這切割穿過模製化合物和導線框。
於某些應用中，相較於使用電線所連接的半導體晶片，半導體晶片對導線框的覆晶附接正持續成長。覆晶附接的成長尤其正由形狀因子和產品效能所驅動。覆晶附接中看到成長的半導體晶片類型尤其包括微處理器、特定應用積體電路(application specific integrated circuit，ASIC)、場可程式化閘陣列(field programmable gate array，FPGA)、數位訊號處理器(digital signal processor，DSP)、媒體產品和圖形晶片。
早期覆晶附接的半導體晶片使用蒸鍍凸塊(譬如C4凸塊)和電鍍凸塊(譬如高鉛凸塊)。目前而言，工業正移動朝向更廣泛使用導電柱結構(譬如銅柱結構)，特別是具有較小的幾何處理節點者。偏好的是銅柱結構，尤其因為它們係建構成提供小形狀因子以支援較小的晶粒尺寸、改善電效能和更環保的(亦即無鉛的)製造解決方案。
將導電柱結構用於近晶片規模封裝(例如MLF型封裝)已經呈現出幾個製造問題。特定而言，隨著工業要求導線框具有極細微的導線間距，每根導線的寬度正在減少。同時，為了改善電效能，導電凸塊(例如銅柱)的尺寸正在增加。然而，隨著導線寬度減少，已經發現柱和導線之間所形成的焊料接合是令人不滿的微弱並且是可靠性問題的來源。
據此，想要具有克服前面所述和其他的相關覆晶封裝問題的半導體封裝結構和方法。也想要具有成本效益、容易整合到組裝流程和可 靠的結構和方法。
於一具體態樣中，一半導體封裝包括多根導線，每根導線具有結合指。半導體晶片具有多個導電凸塊，每個導電凸塊包括導電柱和焊料部分，每個導電凸塊附接到某一結合指。模製化合物樹脂模製成密封半導體晶片、至少部分的導線和導電凸塊，其中導電柱的寬度大於每根導線的寬度，以及其中焊料部分延伸超過結合指的上表面並且至少部分包圍部分結合指的表面積。
於另一具體態樣中，焊料部分完全包圍部分結合指的表面積。於進一步具體態樣中，至少部分的表面積包括凹下部分。於更進一步具體態樣中，每根結合指在截面圖之相對的側表面上具有凹下部分。於另一具體態樣，半導體封裝可以進一步包括在結合指之主表面中的凹窩，其中凹窩配置在凹下部分之間。於進一步具體態樣中，結合指之附接導電凸塊的部分包括窄頸，其具有的寬度小於結合指的另一寬度。於更進一步具體態樣中，半導體封裝可以進一步包括在結合指之主表面中的凹窩，而至少部分的焊料部分配置在凹窩裡。於另一具體態樣中，凹窩可以是在相鄰於半導體晶片之結合指的上主表面中。於進一步具體態樣中，半導體封裝可以具有約2或更大之凸塊對導線的比例。於更進一步具體態樣中，半導體封裝可以包括微導線框封裝。
10‧‧‧半導體晶片
11‧‧‧導線框
12‧‧‧導電結合墊
14‧‧‧外表面
16‧‧‧下表面
20‧‧‧導線
21‧‧‧寬度
22‧‧‧結合指
24‧‧‧著陸部分
28‧‧‧凹陷或蝕刻部分
30‧‧‧導電凸塊
31‧‧‧銅柱
32‧‧‧焊料部分或層
35‧‧‧寬度
40‧‧‧模製化合物樹脂、包封層
100‧‧‧半導體封裝
101‧‧‧半導體晶片
121‧‧‧結合墊
200‧‧‧導線框
201‧‧‧導線
203‧‧‧寬度
222‧‧‧結合指
231‧‧‧彎曲形狀或凹下部分
241‧‧‧著陸部分
261‧‧‧接地墊
271‧‧‧窄頸部分
281‧‧‧蝕刻或凹陷部分
291‧‧‧凹窩
300‧‧‧電子封裝、半導體封裝
301‧‧‧導電凸塊結構、導電凸塊
320‧‧‧寬度
321‧‧‧導電柱
341‧‧‧焊料部分或焊料蓋
342‧‧‧焊料層
400‧‧‧電子封裝、半導體封裝
500、600‧‧‧電子封裝導線結構
圖1顯示覆晶電子封裝結構的截面圖； 圖2顯示用於本發明之具體態樣的導線框結構；圖3示範依據本發明的第一具體態樣之電子封裝的部分截面圖；圖4示範依據本發明的第二具體態樣之電子封裝的部分截面圖；圖5示範依據本發明的第三具體態樣之電子封裝導線結構的部分俯視圖；圖5A示範圖5之具體態樣的截面圖；圖6示範依據本發明的進一步具體態樣之電子封裝導線結構的部分俯視圖；圖6A示範圖6之具體態樣的截面圖；圖7A示範相關電子封裝之導線結構和柱結構的俯視圖；以及圖7B示範依據本發明另一具體態樣的電子封裝之導線結構和柱結構的俯視圖。
為了簡單和清楚的示範，圖中的元件未必按照比例繪製，並且不同圖中的相同參考數字可以表示相同的元件。使用約、差不多或實質上等詞意謂預期元件數值所具有的參數係靠近所述數值或位置。然而，如此技藝所熟知的，總是會有次要的變異而避免該等數值或位置如所述般的精確。附帶而言，可以為了簡單描述而省略熟知步驟和元件的敘述和細節。
本發明的諸多方面和達成該等方面的方法將藉由參照要在此參考伴隨圖式來描述的具體態樣而變得明顯。要了解在此所述的具體態樣只是示範性的，並且本發明並不限於此而是可以採取替換選擇的形式來實施。此外，要了解在此所述之多樣具體態樣的特色可以彼此組合，除非 特別另外註明不行。
一般而言，本發明的具體態樣關於提供較強接合力的結構和方法，以用於導線框裡的導線和導電凸塊的焊料之間的結合接合。提供這較強的接合力，即使減少導線寬度以支援較細微間距的導線框以及即使增加導電柱的寬度亦然。於一具體態樣，每根導線係建構成具有小於導電凸塊寬度的寬度，並且進一步建構成利於來自導電凸塊的焊料流動而部分或完全圍繞每根導線以提供強化的焊料接合。於一具體態樣，每根導線的結合指部分係建構成強化焊料接合。於另一具體態樣，每根導線的著陸部分係建構成強化焊料接合。於一具體態樣，每根導線係建構成具有凹下側表面部分以提供強化的焊料接合。於另一具體態樣，每根導線提供有窄頸部分，其提供強化的焊料接合。於進一步具體態樣，每根導線係建構有凹窩部分，其提供強化的焊料接合。
下文參考圖1來描述使用導線框11(例如微導線框)的半導體封裝100。圖1顯示在半導體封裝100已經使用單粒化過程而分離之後的覆晶附接之電子裝置的截面圖。如圖1所示，半導體封裝100包括電子裝置，例如半導體晶片10，其使用導電凸塊30而附接到導線框11(譬如微導線框)的導線20。於典型的結構，半導體晶片10包括多個導電結合墊12，其形成在半導體晶片10的主表面上並且電連接到半導體晶片10裡的多樣電路元件。鈍化層(未顯示)典型而言形成在結合墊12上並且具有開口以暴露部分的結合墊12。凸塊下金屬(under bump metal，UBM)層(未顯示)典型而言係提供在結合墊12的暴露部分上並且典型而言包括鈦和/或氮化鈦。於導電柱過程，例如銅柱，可光成像的阻劑係用於界定柱結構將被鍍覆的地方，然 後焊料層或焊料蓋可以透過膏過程或電鍍過程而施加到每根柱結構的尖端。然後剝掉阻劑層，多餘的材料可加以蝕刻，然後焊料層可以接受回流過程。
如果半導體晶片10上的結合墊12和每根導線20就如相關技藝般藉由電線而彼此連接，則需要形成電線迴圈的高度，因此不合意的導致半導體封裝的整個厚度有所增加。不像電線結構，半導體封裝100係建構成使得半導體晶片10上的結合墊12和每根導線20使用覆晶組態而彼此連接，其方式能夠讓半導體晶片10和導線20來往做電訊號交換。因此，此種結構有利的減少半導體封裝的整個厚度，並且提供更輕、更薄、更小、更緊緻的產品。
於一具體態樣，導線框11的每根導線20係建構成功能類似於晶片安裝板以在上面安裝半導體晶片10。於一具體態樣，接地墊提供在中央部分而靠近每根導線20的末端部分。此外，每根導線20包括附接覆晶的結合指22和將半導體封裝100附接到組件之另一層級(譬如主機板)的著陸部分24。著陸部分24進一步提供半導體晶片10和其他電子裝置之間的電溝通。凹陷或蝕刻部分28舉例而言藉由蝕刻而減少厚度，其形成在結合指22的下表面上或從結合指22的下表面往內延伸。
半導體晶片10附接到導線20的結合指22。特定而言，於一具體態樣，半導體晶片10上的結合墊12使用覆晶結構而連接到每根導線20的結合指22，其方式允許電訊號交換，然後進行模製過程而以模製化合物樹脂40來密封半導體晶片10、覆晶結構和至少部分的導線20，以提供如圖1所示的相關半導體封裝100。
導電凸塊30舉例而言包括銅柱31和焊料部分或層32。如之前所述，銅柱31可以使用電鍍技術或其他技術而形成覆蓋性結合墊12，如此技藝中具一般技術者所知的。焊料部分32可以藉由鍍覆或藉由沉積焊料膏而整合形成在銅柱31的末端上。於一具體態樣，每根導線20之著陸部分24的外表面14和下表面16暴露到外面，並且每根導線20的凹陷部分28填充了模製化合物樹脂40，因而增加了每根導線20和模製化合物樹脂40之間的耦合力。
於相關的封裝，導電凸塊30的銅柱31具有50微米的典型寬度或直徑。導線20的結合指22典型而言具有70微米的寬度。這尺寸組態提供0.7的柱對導線之比例，這允許形成在銅柱31之末端上的焊料部分32電熔融並且輕易座落在每根導線20之結合指22的頂表面上。然而，如果減少每根導線的寬度並且增加導電凸塊的尺寸以支援用於每根導線的細微間距之導線框和導電凸塊之銅柱部分的尺寸或寬度增加的需求，則已經發現導電凸塊相對於每根導線的焊料接合被弱化。以下的具體態樣係建構成尤其要來強化焊料接合。
圖2示範用於本發明的具體態樣之導線框200的俯視圖。於一具體態樣，導線框200舉例而言係建構成微導線框並且包括多根導線201。導線框200的導線201係建構成功能類似於晶片安裝板以在上面安裝半導體晶片101。於一具體態樣，接地墊261提供在中央部分而靠近每根導線201的末端部分。於一具體態樣，多根導線201可以包括至少四組而配置成靠近接地墊261的四側。此外，每根導線201可以包括附接電子晶片或半導體晶片101的結合指222和將電子封裝附接到組件之次一層級(譬如主機 板)的著陸部分241。著陸部分241進一步提供上面所安裝的半導體晶片101與其他電子裝置之間的電溝通。
圖3示範電子封裝300(例如半導體封裝300)的部分截面圖，其係依據第一具體態樣而包括圖2所示範的導線框200。半導體封裝300是以來自多根導線201的一根導線來示範，其可以建構成晶片安裝墊或晶片安裝板。於半導體封裝300，導線201可以包括結合指222和著陸部分241(其示範於圖2)。於一具體態樣，結合指222可以形成在導線201的內區域中而在其縱向上，以作為覆晶附接半導體晶片101的地方。於一具體態樣，著陸部分241可以形成在每根導線201的外區域中以電連接到組件的次一層級(例如主機板)並且放置成與其他電子裝置做電溝通。於某些具體態樣，蝕刻或凹陷部分281藉由蝕刻而減少厚度，其可以形成在結合指222的下表面上。
半導體晶片101可以使用導電凸塊結構301或導電凸塊301而附接到或安裝到導線201。於一具體態樣，導電凸塊結構301連接到半導體晶片101之表面上的結合墊121並且連接到導線201的結合指222。
依據本具體態樣，導電凸塊結構301包括導電柱321和焊料部分341或焊料蓋341。於某些具體態樣，導電柱321包括金屬材料，例如銅或其他材料，如此技藝中具一般技術者所知的。於一具體態樣，導電柱321可以使用可光成像的層和電鍍過程來形成。焊料部分341然後可以使用電鍍過程或焊料膏沉積過程而形成在導電柱321的尖端或末端部分上。於一具體態樣，焊料部分341可以是銀/錫焊料或別種合金焊料。在形成焊料部分341之後，可以移除可光成像的層。於可選用的步驟，焊料部分341 和導電柱321可以接受回流過程。於一具體態樣，具有導電凸塊結構301的半導體晶片101舉例而言使用拾放工具而放置成接觸多根導線201。組件然後接受升高的溫度以回流焊料部分341而與導線201形成焊料接合。
依據本具體態樣和如圖7B(導線201的俯視圖，亦即上結合表面)所示範，每根導線201的寬度203(亦即靠近導線之上結合表面的寬度)相較於如圖7A所示範的相關封裝則有所減少。於圖7A，相關導線20具有寬度21，其典型而言為70微米或更大。於一具體態樣，每根導線201的寬度203是約60微米或更小，如此以支援具有較細微導線間距的封裝(例如微導線框封裝)。此外，依據本具體態樣，導電柱321具有約120微米或更大的寬度320，如此以改善封裝之半導體裝置的電效能。於如圖7A所示範的相關封裝，相關的凸塊30具有寬度35，其典型而言為50微米或更小。
換個方式來說，相關裝置典型而言具有約0.7或更小之凸塊對導線寬度的比例，而本具體態樣具有約2或更大之凸塊對導線寬度的比例。於相關裝置，此種凸塊對導線寬度的比例會導致導電凸塊和導線之間的焊料接合弱化，如之前所述。依據本具體態樣，半導體封裝301係建構成提供增進的焊料接合或較強的接合力以用於每根導線201和導電凸塊301的焊料部分341之間的接合。更特別而言，導線201係建構成使得焊料部分341至少部分包圍每根導線201的外表面積。於一具體態樣，焊料部分341延伸超過每根導線221的頂表面並且附接到每根導線201之至少部分的側表面，如圖3所大致示範。依據本具體態樣，即使導線201的寬度以此方式而減少並且銅柱321的尺寸以此方式而增加，仍可能顯著強化接合力以用於每根導線201和導電凸塊301的焊料部分341之間的接合。
於某些具體態樣，每根導線201提供有結合指部分222，其建構成利於焊料部分341流動於每根導線201之至少部分的側表面周圍。於較佳的具體態樣，每根導線的側表面可以提供有大致彎曲的形狀或凹下部分231，以藉由部分的焊料部分341來填充至少部分的凹下部分231而進一步強化每根導線201的結合指222和導電凸塊301的焊料部分341之間的接合力。凹下部分231可以建構成增加結合表面的表面積以與焊料部分341形成焊料接合。
在附接過程之後，至少部分的半導體晶片101、部分的每根導線201和導電凸塊301則以模製化合物樹脂40或包封層40來覆蓋或包封。於一具體態樣，模製化合物樹脂40可以使用頂模製過程來形成。在頂模製過程之後，半導體封裝可以使用單粒化過程(例如鋸切過程)而分離成單獨的構件。部分的導線201和/或導線框200(譬如接地墊261)可以穿過模製化合物樹脂而暴露到外面。
圖4示範依據第二具體態樣之電子封裝400(例如半導體封裝400)的部分截面圖。半導體封裝400類似於半導體封裝300，例外之處在於半導體封裝400中的焊料層342一路延伸或整個包圍導線201之部分的結合指222，因此進一步提升或強化接合力以用於每根導線201和導電凸塊301的焊料層342之間的接合(亦即焊料接合)。即使如圖7B所示範的減少導線201的寬度和增加銅柱321的尺寸，本具體態樣仍建構成強化接合力以用於每根導線201和導電凸塊301的焊料層342之間的接合。
圖5示範依據第三具體態樣之電子封裝導線結構500的部分頂部。圖5A示範沿著圖5參考線A-A之導線結構500的截面圖。為了強 化用於每根導線201的結合指222和導電凸塊301的焊料部分341之間接合的接合力，結合指222之要熔融焊料層34的部分係建構成具有窄頸部分271，其具有的寬度小於結合指222的原始寬度。結合指222的其他部分可以有原始的寬度以對結構提供額外的強度和/或穩定度。於一具體態樣，窄頸部分271使用遮罩和蝕刻技術來形成。
依據本具體態樣，當形成在導電凸塊301的銅柱321之末端上的焊料部分342焊接到導線201之結合指222的上表面上時，焊料部分342部分或完全包圍結合指222的表面積，並且窄頸271形成在每根導線201的結合指222上。於此組態，焊料部分342可以更容易包圍結合指222的部分表面積，因此導致每根導線201的結合指222和導電凸塊301的焊料部分342之間的接合有強化的接合力。於一具體態樣，導線結構500可以包括沿著頸部分271之側表面或在其中的凹下部分231。
圖6示範依據另一具體態樣之電子封裝導線結構600的部分頂部。圖6A示範沿著圖6參考線B-B之導線結構600的截面圖。為了強化用於每根導線201的結合指222和導電凸塊301的焊料部分341之間接合的接合力，凹窩291可以形成在結合指222上面要熔融焊料部分341的主表面(譬如上表面)上。於一具體態樣，凹窩291可以使用遮罩和蝕刻過程來形成。於另一具體態樣，凹窩291可以使用壓印技術來形成。於替代性具體態樣，當焊料部分341完全包圍部分的導線201時，凹窩291可以形成在結合指222的下表面中。
依據本具體態樣，當形成在導電凸塊301的銅柱321之末端上的焊料部分341焊接到導線201之結合指222的上表面上時，焊料部分 341部分或完全包圍結合指222的表面積。附帶而言，凹窩291形成在每根導線201的結合指222上。於結合指222的這組態，焊料部分341在填充凹窩291的同時可以更容易包圍結合指222的表面積，因此導致強化了用於每根導線201的結合指222和導電凸塊301的焊料部分341之間接合的接合力。凹窩291係建構成增加表面積以與焊料部分341形成焊料接合。於一具體態樣，導線結構600可以包括沿著結合指222之側表面或在其中的凹下部分231。於一具體態樣，凹窩291是在凹下部分231之間，舉例而言大致如圖6A所示範。
熟於此技藝者將體會所述的具體態樣也可以像在結合指222一樣而實施在每根導線201的著陸部分241上。舉例來說，於著陸部分的實施例，焊料部分341較佳而言僅部分包圍著陸部分的表面積，並且此種著陸部分可以建構成包括一或更多個凹下部分231，以進一步提升焊料部分341和每根導線201之間結合力的強度。
從以上所有而言，熟於此技藝者可以決定如下。根據一具體態樣，半導體封裝包括：半導體晶片；多根導線，上面安裝了半導體晶片；導電凸塊，其使半導體晶片的結合墊與每根導線的結合指電連接；以及模製化合物樹脂，其模製成密封半導體晶片、導線和導電凸塊。導電凸塊之導電柱的尺寸大於每根導線的寬度，如此則當形成在導電柱之末端上的焊料焊接到導線之結合指的上表面上時，焊料被焊接而同時部分或完全包圍結合指的表面積。
於另一具體態樣，凹下部分可以藉由蝕刻過程而形成在結合指的每個相對側上。於進一步具體態樣，結合指之要熔融焊料的部分可以 經歷蝕刻過程以形成窄頸，其具有的寬度小於結合指的原始寬度。於更進一步具體態樣，凹窩可以形成在結合指之上面要熔融焊料的上表面上。
從以上所有而言，熟於此技藝者可以決定如下。根據另一具體態樣，半導體封裝包括多根導線，每根導線具有結合指。半導體晶片具有多個導電凸塊，每個導電凸塊包括導電柱和焊料部分，每個導電凸塊附接到某一結合指。模製化合物樹脂模製成密封半導體晶片、至少部分的導線和導電凸塊，其中導電柱的寬度大於每根導線的寬度，並且其中焊料部分延伸超過結合指的上表面並且至少部分包圍結合指的部分表面積。
於另一具體態樣，焊料部分完全包圍結合指的部分表面積。於進一步具體態樣，至少部分的表面積包括凹下部分。於更進一步具體態樣，每根結合指在截面圖之相對的側表面上具有凹下部分。於另一具體態樣，半導體封裝可以進一步包括在結合指之主表面中的凹窩，其中凹窩配置在凹下部分之間。於進一步具體態樣，結合指之附接導電凸塊的部分包括窄頸，其具有的寬度小於結合指的另一寬度。於更進一步具體態樣，半導體封裝可以進一步包括在結合指之主表面中的凹窩，而至少部分的焊料部分配置在凹窩裡。於另一具體態樣，凹窩可以是在結合指的上主表面中而相鄰於半導體晶片。於進一步具體態樣，半導體封裝可以具有約2或更大之凸塊對導線的比例。於更進一步具體態樣，半導體封裝可以包括微導線框封裝。
從以上所有而言，熟於此技藝者可以決定如下。根據進一步具體態樣，電子封裝結構包括具有第一寬度的導線。電子晶片在主表面上具有導電凸塊，其中導電凸塊具有大於第一寬度的第二寬度，並且其中導 電凸塊附接到導線，其中部分的導電凸塊延伸成至少部分包圍導線的側表面。模製化合物樹脂則密封電子晶片、導電凸塊和至少部分的導線。
於另一具體態樣，導線進一步包括具有第一寬度的結合指，其中導電凸塊附接到結合指。於進一步具體態樣，導線的側表面具有凹下部分。於更進一步具體態樣，電子封裝可以進一步包括在導線之主表面中的凹窩，其中部分的導電凸塊是在凹窩裡。於另一具體態樣，部分的導電凸塊完全包圍部分的導線。於更進一步具體態樣，導電凸塊包括導電柱和在導電柱之尖端上的焊料部分，其中焊料部分延伸成至少部分覆蓋導線的側表面。於另一具體態樣，導線進一步包括窄頸部分，該窄頸部分具有第一寬度，並且其中導線具有大於第一寬度的第三寬度。於進一步具體態樣，第二寬度對第一寬度的比例是約2或更大。
從以上所有而言，熟於此技藝者可以決定如下。根據更進一步具體態樣，形成半導體封裝的方法包括提供具有導線的導線框，而導線具有第一寬度。該方法包括提供半導體晶片，其在主表面上具有導電凸塊，導電凸塊具有大於第一寬度的第二寬度。該方法包括將導電凸塊附接到導線，其中在附接步驟之後，部分的導電凸塊延伸成至少部分包圍導線的側表面。該方法包括包封半導體晶片、導電凸塊和至少部分的導線。
於另一具體態樣，提供導線框的步驟可以包括提供具有以下一或更多者的導線：在導線之側表面上的凹下部分、窄頸部分、或在導線之上表面中的凹窩。於進一步具體態樣，提供導電凸塊可以包括提供導電柱，而在導電柱的末端表面上具有焊料部分。於更進一步具體態樣，第二寬度對第一寬度的比例大於或等於約2。
鑒於以上全部，顯然揭示了新穎的結構和製作該結構的方法。尤其包括的是電子封裝，其具有的導線係建構成以覆晶或晶片附接安排來附接到電子晶片(例如半導體晶片)。於一具體態樣，導線要比用於將電子晶片附接到導線的導電凸塊來得窄。導線係建構成利於強化焊料接合。於一具體態樣，導線係建構成利於焊料部分流動於導線的側表面周圍。於一具體態樣，側表面係建構成增加表面積以用於焊料附接。於一具體態樣，導線的側表面具有凹形部分。於另一具體態樣，焊料層完全包圍部分的導線。於進一步具體態樣，導線係建構成具有窄頸部分以將導電凸塊附接到導線。窄頸部分可以建構成利於焊料流動成部分或完全圍繞著導線。於進一步具體態樣，凹窩置於導線的主表面中以增加用於形成焊料接合的表面積。
前面的具體態樣尤其提供用於每根導線和導電凸塊的焊料之間接合的較強接合力，即使在使用較小的導線框(例如微導線框)來製造半導體封裝時之每根導線的寬度有所減少並且導電凸塊的導電柱尺寸有所增加亦然。更特別而言，即使每根導線的寬度減少並且導電凸塊的尺寸增加以對付每根導線的細微間距和導電凸塊的銅柱尺寸增加，焊接仍進行成使得焊料包圍至少部分的導線，因此提供了用於導電凸塊的焊料接合相對於每根導線的改善接合力。
雖然本發明的主題是以特定較佳的具體態樣和範例性具體態樣來描述，不過前面的圖式及其敘述僅顯示主題的典型具體態樣，因此不是要視為限制其範圍。熟於此技藝者顯然將明白有許多替代方案和變化。舉例而言，頸部分271和凹窩291的組態只是示範性的，並且可能有其 他的樣式、形狀和組態來提供想要的結合強化。同時，模製化合物樹脂40可以藉由頂模製和鋸穿技術來形成、藉由空腔模製和衝壓技術來形成、或藉由其他技術來形成，如此技藝中具一般技術者所知的。
如下文之申請專利範圍所反映的，發明方面可以落在少於前面揭示之單一具體態樣的所有特色。因此，下文表達的申請專利範圍明確併入此【實施方式】，而每個請求項自立成為本發明的個別具體態樣。再者，雖然在此所述的某些具體態樣包括了其他具體態樣所未包括的一些特色，但是不同具體態樣的特色組合意謂是在本發明的範圍裡並且形成不同的具體態樣，如熟於此技藝者所會理解。
40‧‧‧模製化合物樹脂、包封層
101‧‧‧半導體晶片
121‧‧‧結合墊
201‧‧‧導線
222‧‧‧結合指
231‧‧‧彎曲形狀或凹下部分
281‧‧‧蝕刻或凹陷部分
301‧‧‧導電凸塊結構、導電凸塊
321‧‧‧導電柱
341‧‧‧焊料部分或焊料蓋

Claims (20)

  1. 一種半導體封裝，其包括：多根導線，每根導線具有結合指以及比該結合指厚的著陸部分；半導體晶片，其具有多個導電凸塊，每個導電凸塊包括導電柱和焊料部分，每個導電凸塊附接到該等結合指之一；以及模製化合物樹脂，其模製成密封該半導體晶片、至少部分的該等導線和該導電凸塊，其中該導電柱的寬度大於該等導線之每一者的寬度，以及其中該焊料部分延伸超過該結合指的上表面並且至少部分包圍該結合指之部分的表面積，並且其中每一個著陸部分至少暴露於該模製化合物樹脂的表面之外面。
  2. 如申請專利範圍第1項的半導體封裝，其中該焊料部分完全包圍該結合指之該部分的該表面積。
  3. 如申請專利範圍第1項的半導體封裝，其中至少部分的該表面積包括凹下部分。
  4. 如申請專利範圍第1項的半導體封裝，其中每根結合指在截面圖之相對的側表面上具有凹下部分。
  5. 如申請專利範圍第4項的半導體封裝，其進一步包括在該結合指之主表面中的凹窩，其中該凹窩配置在該等凹下部分之間。
  6. 如申請專利範圍第1項的半導體封裝，其中該結合指之附接該導電凸塊的部分包括窄頸，其具有的寬度小於該結合指的另一寬度。
  7. 如申請專利範圍第1項的半導體封裝，其進一步包括在該結合指之主表面中的凹窩，而至少部分的該焊料部分配置在該凹窩裡。
  8. 如申請專利範圍第7項的半導體封裝，其中該凹窩是在相鄰於該半導體晶片之該結合指的上主表面中。
  9. 如申請專利範圍第1項的半導體封裝，其中該半導體封裝具有約2或更大之凸塊對導線寬度的比例。
  10. 如申請專利範圍第9項的半導體封裝，其中該半導體封裝包括微導線框封裝。
  11. 一種電子封裝結構，其包括：導線，其具有第一寬度，其中該導線的側表面具有凹下部分；電子晶片，其在主表面上具有導電凸塊，其中該導電凸塊具有大於該第一寬度的第二寬度，並且其中該導電凸塊附接到該導線，其中部分的該導電凸塊延伸成至少部分包圍該導線的該側表面；以及模製化合物樹脂，其密封該電子晶片、該導電凸塊和至少部分的該導線。
  12. 如申請專利範圍第11項的結構，其中該導線進一步包括結合指，其具有該第一寬度，其中該導電凸塊附接到該結合指。
  13. 如申請專利範圍第12項的結構，其中該導線進一步包括穿過該模製化合物樹脂的表面而暴露的著陸部分。
  14. 如申請專利範圍第11項的結構，其進一步包括在該導線之主表面中的凹窩，其中部分的該導電凸塊是在該凹窩裡。
  15. 如申請專利範圍第11項的結構，其中該導電凸塊的該部分完全包圍部分的該導線。
  16. 如申請專利範圍第11項的結構，其中該導電凸塊包括導電柱和在該 導電柱之尖端上的焊料部分，其中該焊料部分延伸成至少部分覆蓋該導線的側表面。
  17. 如申請專利範圍第11項的結構，其中該導線進一步包括窄頸部分，該窄頸部分具有該第一寬度，並且其中該導線具有大於該第一寬度的第三寬度。
  18. 如申請專利範圍第11項的結構，其中該第二寬度對第一寬度的比例是2或更大。
  19. 一種形成半導體封裝的方法，其包括：提供具有導線的導線框，該導線具有第一寬度；提供半導體晶片，其在主表面上具有導電凸塊，該導電凸塊具有大於該第一寬度的第二寬度；將該導電凸塊附接到該導線，其中在該附接步驟之後，部分的該導電凸塊延伸成至少部分包圍該導線的側表面；以及包封該半導體晶片、該導電凸塊和至少部分的該導線。
  20. 如申請專利範圍第19項的方法，其中：提供該導線框包括提供具有以下一或更多者的導線：在導線之側表面上的凹下部分、窄頸部分或在該導線之上表面中的凹窩；提供該導電凸塊包括提供導電柱，其具有在該導電柱之末端表面上的焊料部分；以及該第二寬度對第一寬度的比例是大於或等於約2。
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US20160118319A1 (en) 2016-04-28
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US9184148B2 (en) 2015-11-10
US9543235B2 (en) 2017-01-10
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