KR0163526B1 - 자외선/오존을 조사하여 접속패드에 보호막을 형성하는 단계를 포함하는 반도체소자 제조방법 - Google Patents
자외선/오존을 조사하여 접속패드에 보호막을 형성하는 단계를 포함하는 반도체소자 제조방법 Download PDFInfo
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- KR0163526B1 KR0163526B1 KR1019950012206A KR19950012206A KR0163526B1 KR 0163526 B1 KR0163526 B1 KR 0163526B1 KR 1019950012206 A KR1019950012206 A KR 1019950012206A KR 19950012206 A KR19950012206 A KR 19950012206A KR 0163526 B1 KR0163526 B1 KR 0163526B1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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Abstract
본 발명은 반도체칩의 접속패드에 보호막을 형성시키는 단계를 포함하는 반도체소자 제조방법으로서 패키지재료인 성형수지 성분으로 인한 흡습 또는 고온·고압 강제 흡습검사 등으로 인하여 흡수된 물이나 할로겐 이온이 접속패드를 부식시키는 것을 방지하기 위해서, 자외선과 오존을 이용하여 접속패드 상면에 산화막을 형성하고 이 접속패드에 직접 금속선을 접합하여 부식 발생원으로부터 접속패드를 차단하고 반도체 패키지의 신뢰성을 향상시키는 효과를 단수한 제조공으로 이룰 수 있다.
Description
제1도는 접속패드에 보호막을 형성하는 단계를 나타내는 단면도.
제2도는 보호막이 형성된 접속패드와 내부단자가 금속선에 의해서 연결된 것을 도시한 단면도.
제3도는 제2도 A부분의 확대도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체칩 3 : 접속패드
5 : 비활성층(passivation layer) 7 : 보호막
10 : 반도체 패키지 12 : 다이패드
14 : 내부단자 16 : 외부단자
18 : 성형수지 20 : 금속선
22 : 볼(ball)
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 구체적으로는 자외선을 조사하여 오존을 여기(勵起) 산소로 분해하여 반도체칩의 접속패드에 산화 보호막을 형성시켜 반도체소자를 제조하는 방법에 관한 것이다.
웨이퍼 프로세서에 의해 원하는 회로 패턴 형성이 완료된 반도체칩은 외부와의 전기적인 연결을 위한 접속패드 제조공정을 거친다. 접속패드가 형성되고 나면, 이 접속패드를 제외한 전표면에 비활성층(passivation layer)를 입힌 다음 패키지 공정으로 넘어간다. 패키지 공정은 먼지, 열, 습기, 전기 및 기계적 부하 등 각종의 외부 요인에 의한 칩의 손상을 방지하고 반도체 소자와 외부 간의 전기적인 연결을 위한 것이다. 패키지 공정은 주로 패키지된 제품의 신뢰성을 향상시키기 위해 칩 주위를 금소, 세라믹 또는 수지(혹은 수지계 성형재료)에 의하여 밀봉(encapsulation)한 패키지 형태로 실용화되고 있다.
그 중에서, 에폭시 계열의 성형수지를 이용한 플라스틱 밀봉법은 경제적인 효율 측면이나 대량 생상성 면에서 여러 이점을 가지고 있으나, 에폭시의 흡습에 의한 부식 등의 신뢰성에 문제를 가지는 단점이 있다. 예를 들어서, 패키지 신뢰성 검사법 중 하나인 증기압 시험(PCT ; Pressure Cooker Test, 약 2기압의 압력과 약 121℃ ±2℃ 정도의 온도에서 검사를 하는 고온고압 강제 흡습검사) 동안에 습기가 에폭시 수지에 의해 흡수되거나 성형 수지와 단자 프레임 계면을 통해 침투하게 되어 칩 표면에 도달하게 되고 비활성층으로 보호되지 않은 접속패드 부분에서 부식이 발생하게 된다.
이러한 흡습에 의한 부식을 방지하기 위해 많은 방법들이 이미 제시되었고, 접속패드 표면에 습기와 부식을 유발하는 할로겐족 이온의 침투를 억제하는 보호층을 형성시키는 여러 가지 방법도 제시된 바 있으나 공정에 적용하기 어렵거나 크게 개선 효과를 보이지 않아 널리 적용되고 있지 못한 실정이다.
예를 들면, 일본 특허공개공보 116634/1981에 개시된 방법은 금속선 접합후의 반도체 패키지를 고온의 수증기에 노출시켜 알루미늄 접속패드 표면에 보호막을 형성시켰으며, 일본 특헝공개공보 50687/1977에 개시된 방법은 반도체 패키지를 80℃ 내지 250℃의 고온 수조(水槽)에 5분 내지 100분간 담가서 알루미늄 접속패드 표면에 수산화층을 형성시킨 것이다. 그러나, 수증기나 물은 이온을 포함하고 있지 않을 경우에도 산도(pH)값에 해당하는 OH-와 H+농도를 가지므로 오히려 부식을 유발시킬 가능성을 내포하고 있어 현실적으로 공정에서 사용되지 않고 있다.
또한, 실리콘 젤 등의 폴리머를 금속선 접합후의 칩 표면에 도포하여 습기나 이온의 침투를 막는 확산경계층(Diffusion barrier film)을 형성시키는 방법이 있으나 폴리머의 흡습 특성상 습기로부터 반도체 소자를 보호하기에는 적절치 못한 단점을 가지고 있다.
또한, Improvement of Moisture Resistance by the New Surface Treatment of Aluminum Bonding Pads in LSI, ISTFA ' 93, The 19th International Symposium for Testing Failure Analysis에는 접속패드에 얇은 알루미늄 산화막을 형성시켜서 흡습에 의한 부식을 방지하는 방법이 개시되어 있다. 이 논문에서는 웨이퍼 프로세서의 최종 단계에서 알루미늄 접속패드가 형성된 반도체 웨이퍼를 오존(O3) 용액에 담가서 접속패드에 알루미늄 산화막을 형성시킨다. 이렇게 하면, PCT 검사에 의한 불량율이 현저하게 감소하게 됨을 알 수 있다.
그러나, 이 논문에 개시되어 있는 오존 용액을 사용한 방법은 탈이온수(de-ionized water)에 오존을 불어 넣어 오존의 농도를 증가시킨 다음 알루미늄 금속을 산화시키는 것으로서 물속에 포함된 오존에 의해 반응이 일어나므로 공기 중의 오존에 비해서 용액속의 오존의 확산계수가 낮기 때문에 반응성이 떨어진다는 단점이 있다. 또한, 웨이퍼를 오존 용액에 담가서 처리하기 때문에 이 용액에 의해 웨이퍼가 오염될 우려가 있다.
따라서 본 발명의 목적은 보다 간단한 공정으로 보다 효과적으로 접속패드에 보호막을 형성시키는 것을 포함하는 반도체 소자 제조방법을 제공하는 것이다.
본 발명에 따른 산화 보호막 형성방법은 웨이퍼 공정이 완료된 상태의 반도체칩에 자외선을 조사(照射)하여 오존을 여기 산소로 분해하고 이때 생성된 여기 산소와 접속패드의 금속 원자가 결합하여 최종적으로 접속패드에 보호막을 형성시키는 것을 이용하는 것이다.
제1도는 본 발명에 따른 보호막이 형성된 반도체 소자의 단면도이다.
웨이퍼 프로세서에 의해 반도체칩(1)에 형성되어 외부와 전기적인 연결을 하기 위한 접속패드(3)를 제외한 반도체칩의 전표면에 비활성층(5)을 도포하여 반도체칩 표면을 보호한다. 이렇게 제조 공정이 끝난 웨이퍼 상태의 반도체칩을 오존(O3)분위기에 노출시키고 자외선(UV)을 조사하면, 오존으로부터 여기 산소가 생성되며, 이 여기 산소는 접속패드를 이루는 금속과 반응하여 접속패드상에 산화물 보호막(7)을 얇게 형성한다. 이 보호막은 접속패드의 금속 재료가 주로 알루미늄이므로 Al2O3가 될 것이다.
본 발명에 따른 보호막(7)은 자외서/오존 발생장치에 의해 생성되는데, 자외선/오존 발생 장치에 의한 생성 조건으로서 본 발명자가 행한 실시예의 조건을 기술하면 아래의 표와 같다.
보호막 생성에 관한 화학 반응식을 기술하면 다음과 같다.
이러한 반응에 의해 생성되는 보호막(Al2O3)은 웨이퍼상태의 반도체칩의 오존/자외선 처리를 간단하게 하여 반도체칩의 부식 저항성을 높일 수 있다.
제2도는, 위와 같이 하여 보호막이 형성된 접속패드에 금속선을 접합하여(wire bonding) 완성한 반도체 패키지의 단면도이다. 제3도는 제2도 A부분의 확대도이다.
제2도 및 제3도를 참조하면, 반도체 패키지(10)는 반도체칩(1)과 다이패드(12)와 내부단자(14)와 외부단자(16)와 성형수지(18)로 이루어진다. 다이패드(12)에는 반도체칩(1)이 은에폭시 등에 의해 접착되어 있고 접속패드(3)와 내부단자(14)는 금속선(20)에 의해 전기적으로 연결된다. 외부단자(16)는 내부단자(14)와 일체형으로 제작되는데, 이 외부단자(16)는 패키지 밖으로 노출되어 외부회로와 접속된다.
제3도를 참조하면, 앞에서 설명한 것과 같이 자외선/오존 처리에 의해 Al2O3보호막(7)이 형성되어 있는 접속패드(3)에 금속선 접합 공정이 행해진다. 접합되는 금속선(20)은 접속패드와의 접합 부분에서 높은 내식성과 고속 접합이 요구되기 때문에 일반적으로 볼 본딩(22)에 의해 접속패드에 접합된다. 여기서, 비록 접속패드(3)에는 본 발명에 따른 보호막(7)이 형성되어 있지만, 그 두께가 얇고 (즉50 이하) 금속선 접합시 비교적 높은 압력과 온도(약 300℃) 또는 초음파에너지가 가해지기 때문에, 보호막(7)이 볼(22)의 면적만큼 파괴되어 볼(22)이 접속패드(3)에 완전히 접합될 수 있다. 따라서, 별도의 마스크없이도 접속패드에 보호막을 남겨둔 채로 금속선 접합을 행할 수 있다.
이상 설명한 것과 같이, 여기산소와 오존이 노출되어 있는 알루미늄 접속패드를 산화시켜 치밀하고 견고한 보호막을 형성시켜 부식을 유발하는 물과 이온으로부터 접속패드를 보호하게 된다. 즉, 자외선/오존 처리는 자외선/오전 발생장치에서 생성된 오존과 여기 산소가 웨이퍼 표면에 작용하여 산화 반응을 일으키고, 따라서 노출되어 있는 알루미늄 접속패드에 치밀한 보호막이 형성되어 신뢰성 검사시 습기와 이온이 알루미늄 접속패드로 침투되지 못하도록 한다. 습기의 침투를 막는 것이 완벽하지 못할지라도 습기가 알루미늄 접속패드에 도달할 때까지 걸리는 시간이 훨씬 증가되므로 이것은 반도체 소자의 신뢰성이 향상됨을 뜻한다.
따라서, 본 발명에 따른 반도체소자 제조방법에 의하면 반도체 패키지로부터 접속패드로의 습기 침투가 현저히 감소되며 반도체 패키지 표면에 노출된 금속표면에 부식 저항성이 강한 산화물 보호막을 형성시켜서, 신뢰성이 우수한 반도체 패키지를 간단한 공정으로 제조할 수 있는 효과가 있다.
Claims (6)
- 접속패드와 이 접속패드를 제외한 전표면에 비활성층이 도포된 반도체칩을 준비하는 단계, 상기 반도체칩을 오존에 노출시키면서 오존에 자외선을 조사하여, 자외선에 의해 여기된 산소가 접속패드를 이루는 금속원자와 반응하여 산화막을 형성하는 단계, 산화막이 형성된 접속패드와 내부단자를 금속선으로 접합하는 단계, 반도체칩을 성형수지로 밀봉하여 패키징하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조방법.
- 제1항에 있어서, 상기 접속패드를 이루는 금속원자는 알루미늄원자인 것을 특징으로 하는 반도체소자 제조방법.
- 제1항 또는 제2항에 있어서, 상기 자외선의 파장은 253.7nm 또는 184.9nm인 것을 특징으로 하는 반도체소자 제조방법.
- 제1항 또는 제2항에 있어서, 상기 자외선을 5분 내지 10분 정도 조사(照射)하는 것을 특징으로 하는 반도체소자 제조방법.
- 제4항에 있어서, 자외선을 조사할 때 접속패드의 온도는 약 150℃인 것을 특징으로 하는 반도체소자 제조방법.
- 제1항 또는 제2항에 있어서, 산화막의 두께는 약 50Å이하인 것을 특징으로 하는 반도체소자 제조방법.
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US08/505,910 US5595934A (en) | 1995-05-17 | 1995-07-24 | Method for forming oxide protective film on bonding pads of semiconductor chips by UV/O3 treatment |
JP7189469A JPH08316267A (ja) | 1995-05-17 | 1995-07-25 | 半導体チップのボンディングパッド保護膜形成方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS5050687A (ko) * | 1973-09-07 | 1975-05-07 | ||
JPS56116634A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor device |
JPS63216352A (ja) * | 1987-03-04 | 1988-09-08 | Nec Corp | 半導体装置の製造方法 |
JPH01316945A (ja) * | 1988-06-17 | 1989-12-21 | Nec Corp | 半導体装置 |
JPH0787189B2 (ja) * | 1990-01-19 | 1995-09-20 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JPH03276736A (ja) * | 1990-03-27 | 1991-12-06 | Nec Corp | 半導体装置の製造方法 |
US5213996A (en) * | 1990-07-04 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for forming interconnection pattern and semiconductor device having such interconnection pattern |
JPH07118522B2 (ja) * | 1990-10-24 | 1995-12-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 基板表面を酸化処理するための方法及び半導体の構造 |
FR2675309A1 (fr) * | 1991-03-22 | 1992-10-16 | Siemens Ag | Procede pour eliminer localement des couches isolantes transparentes aux ultraviolets, situees sur un substrat semiconducteur. |
JPH06188419A (ja) * | 1992-12-16 | 1994-07-08 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタの製造方法 |
-
1995
- 1995-05-17 KR KR1019950012206A patent/KR0163526B1/ko not_active IP Right Cessation
- 1995-07-24 US US08/505,910 patent/US5595934A/en not_active Expired - Lifetime
- 1995-07-25 JP JP7189469A patent/JPH08316267A/ja active Pending
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KR960043058A (ko) | 1996-12-21 |
US5595934A (en) | 1997-01-21 |
JPH08316267A (ja) | 1996-11-29 |
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