TWI657516B - 承載結構及封裝結構 - Google Patents

承載結構及封裝結構 Download PDF

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TWI657516B
TWI657516B TW107126152A TW107126152A TWI657516B TW I657516 B TWI657516 B TW I657516B TW 107126152 A TW107126152 A TW 107126152A TW 107126152 A TW107126152 A TW 107126152A TW I657516 B TWI657516 B TW I657516B
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substrate
substrates
area
surrounding portion
item
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TW202008480A (zh
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蕭憲隆
白裕呈
羅家麒
陳思先
張書齊
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矽品精密工業股份有限公司
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Priority to TW107126152A priority Critical patent/TWI657516B/zh
Priority to CN201810895243.4A priority patent/CN110767624B/zh
Priority to US16/232,735 priority patent/US11239125B2/en
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Abstract

一種承載結構，係包括：複數基板、連結於各該基板之間的隔離部、以及設於該複數基板外圍且具有至少一開口之圍繞部，以藉由該開口之設計，減少該承載結構之絕緣層之面積，進而減少靜電於該承載結構中之整體積存空間。

Description

承載結構及封裝結構
本發明係有關一種封裝技術，尤指一種半導體封裝結構及其承載結構。
目前半導體封裝製程中，所採用之封裝基板條係設計有電鍍匯流排與電鍍橋接線，以供電鍍圖案化金屬層，其中，該些電鍍匯流排係延伸至該封裝基板條之側邊。
如第1A及1A’圖所示，前述封裝基板條係包括：複數置晶區1a、連結於各該置晶區1a之間的隔離區1b、以及位於該置晶區1a與該隔離區1b外圍之圍繞區1c，該置晶區1a具有陣列排設之複數基板10，且該圍繞區1c配置有電鍍匯流排13，其中，該基板10係具有介電體100與設於該介電體100中之線路層101。
在封裝過程中，經由一軌道(圖未示)傳送該封裝基板條，以將半導體元件11設於該基板10上並電性連接該基板10，再以封裝膠體12包覆該半導體元件11，以形成封裝結構1。之後，切除該圍繞區1c，再如第1B圖所示，沿該隔離區1b進行切單製程，以獲取複數個半導體封裝件。
惟，習知封裝製程中，由於該基板10之本體(該介電體100)係為高分子複合材，故於封裝製程中，摩擦/吸取及放置等加工動作容易於該高分子複合材中產生高靜電壓之積存，且該半導體元件11接置於該基板10上後，兩者可視為同一結構組合，因而當高靜電壓碰觸導體或接地後，若超出該半導體元件11之靜電負荷極限量，會造成靜電破壞產品。
例如，當傳送該封裝基板條時，該電鍍匯流排13外露於該封裝基板條之側面，致使該電鍍匯流排13與該軌道會相互接觸摩擦，因而該介電體100之積存靜電會產生靜電放電(Electrostatic Discharge，簡稱ESD)效應，導致靜電觸發產生之電流會沿著該電鍍匯流排13、電流導引線(其配置於該隔離區1b以連接該電鍍匯流排13與該線路層101)及線路層101導通到半導體元件11，若該電流量大於該半導體元件11之靜電流負荷之極限量，則該靜電觸發產生之電流會破壞該半導體元件11之電性功能，如燒壞該半導體元件11。
或者，當該半導體元件11以打線或覆晶方式設置於該基板10上之後，在進行形成該封裝膠體12之模壓作業中，因金屬上、下模具於脫模過程中會快速分離，故該介電體100之積存靜電會產生靜電放電(ESD)效應，靜電觸發產生之電流會沿著該電鍍匯流排13、電流導引線及線路層101導通到半導體元件11，若該電流量大於該半導體元件 11之靜電流負荷之極限量，則該靜電觸發產生之電流會破壞該半導體元件11之電性功能。
另一方面，為了解決靜電經由該電鍍匯流排13導入該半導體元件11之問題，遂有在各該隔離區1b上銑出狹長之貫通開槽(如第1A’圖所示之虛線表示之長條狀14)，以移除該隔離區1b中之電流導引線，致使該電鍍匯流排13與該線路層101之間形成斷路，但該開槽不僅會使該封裝基板條容易變形，且該開槽之寬度需大於該隔離區1b之寬度，導致該置晶區1a之可佈線平面面積減少，因而會增加封裝製程之成本(如增加該基板10之層數以達到所需之佈線數量)。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種承載結構，係定義有相鄰接之保留區與移除區，該承載結構包括：複數基板，係位於該保留區；一隔離部，係位於該保留區且連結於各該基板之間；以及一圍繞部，係位於該移除區且形成有至少一開口。
本發明亦提供一種封裝結構，係包括：一承載結構，係定義有相鄰接之保留區與移除區，該承載結構包含：複數基板，係位於該保留區；一隔離部，係位於該保留區且連結於各該基板之間；及一圍繞部，係位於該移除區且形成有至少一開口；複數電子元件，係設於各該基板上並電 性連接該基板；以及包覆層，係形成於該保留區上以包覆該複數電子元件。
前述之基板結構與封裝結構中，該基板係包含有至少一線路層。
前述之基板結構與封裝結構中，該圍繞部之表面係形成有一絕緣層。例如，該開口係形成於該絕緣層上。
前述之基板結構與封裝結構中，該開口中係形成有導電體。例如，該導電體係貫穿該圍繞部或未貫穿該圍繞部。
前述之基板結構與封裝結構中，該圍繞部係具有複數電鍍導線，其對應電性連接各該基板。例如，該些電鍍導線之至少兩者係相互串連。
由上可知，本發明之承載結構及封裝結構，主要藉由該圍繞部具有至少一開口之設計，以減少該承載結構之絕緣層之面積，因而可減少該靜電於該承載結構中之整體積存空間，亦即，可減少該基板上之靜電量或可調控該基板之靜電分佈，故相較於習知技術，本發明之結構不僅該靜電觸發產生之電流量不會超過大於該電子元件之靜電流負荷之極限量，且能避免該承載結構發生變形，更無需縮減該基板之可佈線平面面積，因而能降低封裝製程之成本。
1,3‧‧‧封裝結構
1a‧‧‧置晶區
1b‧‧‧隔離區
1c‧‧‧圍繞區
10,20‧‧‧基板
100‧‧‧介電體
101,201‧‧‧線路層
11‧‧‧半導體元件
12‧‧‧封裝膠體
13‧‧‧電鍍匯流排
14‧‧‧長條狀
2‧‧‧承載結構
2a‧‧‧第一側
2b‧‧‧第二側
2c‧‧‧側面
200‧‧‧介電層
202‧‧‧電性接觸墊
203‧‧‧防銲層
203a‧‧‧開孔
21‧‧‧隔離部
22‧‧‧圍繞部
220‧‧‧開口
221‧‧‧導電體
222‧‧‧電鍍導線
223‧‧‧延伸導線
30‧‧‧電子元件
31‧‧‧導電凸塊
32‧‧‧包覆層
A‧‧‧保留區
B‧‧‧移除區
第1A及1B圖係為習知半導體封裝件之製法之剖面示意圖；第1A’圖係為第1A圖之上視示意圖；第2A圖係為本發明之承載結構之上視示意圖； 第2A’圖係為本發明之封裝結構之上視示意圖；第2B圖係為第2A’圖之局部剖面示意圖；第2C圖係為第2A圖之局部剖面示意圖；第2C’圖係為第2C圖之另一實施例；以及第2D圖係為第2A圖之局部側面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A及2B圖，係為本發明之承載結構2的示意圖。如圖所示，所述之承載結構2係定義有相鄰接之保留區A與移除區B(兩者交界如第2A圖所示之虛線)，且該承載結構2係包括：複數位於該保留區A之基板20、位 於該保留區A且連結於各該基板20之間的隔離部21、以及位於該移除區B且具有至少一開口220之圍繞部22。
所述之承載結構2係為整版面型式，如封裝基板條，其具有相對之第一側2a與第二側2b及鄰接該第一側2a與第二側2b之側面2c。
所述之基板20係陣列排設，且如第2B圖所示，該基板20係為具有核心層之線路佈設或無核心層(coreless)之線路佈設，其具有複數介電層200與線路層201，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且形成該基板20之主要材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該基板20亦可為其它承載晶片之承載件，如有機板材、半導體材、或其他具有金屬佈線(routing)之載板，並不限於上述。
於本實施例中，該線路層201於該承載結構2之第一側2a之處具有複數電性接觸墊202，且該基板20於該承載結構2之第一側2a之處形成有一如綠漆或介電材之防銲層203，並使該防銲層203形成有複數外露該些電性接觸墊202之開孔203a，俾供電子元件30藉由複數導電元件31電性連接該些電性接觸墊202。
所述之隔離部21係作為切單製程之切割路徑，其構造係可依據該基板20之製程及構造製作，例如，可由該些介電層200(及該防銲層203)構成該隔離部21，且該隔 離部21形成有導通各該線路層201之電流導引線(圖未示)。
所述之圍繞部22係連結該隔離部21並於後續切邊作業中隨該移除區B一併移除，且該圍繞部22之構造係可依據該基板20之製程及構造製作，例如，可由該些介電層200構成該圍繞部22，且該圍繞部22於該承載結構2之第一側2a之處之表面係為絕緣層，如該防銲層203。
於本實施例中，該開口220係形成於該圍繞部22之絕緣層，例如，形成於該防銲層203。
再者，該開口220中亦可形成有導電體221，如第2C及2C’圖所示，且該導電體221未電性連接該線路層201及該電性接觸墊202。具體地，該導電體221係可依據該基板20之製程及構造製作，例如，於該些介電層200中形成線路態樣、導電盲孔態樣及/或墊狀態樣之金屬層，且可依需求令該導電體221貫穿該圍繞部22(如第2C圖所示之延伸於所有介電層200)或未貫穿該圍繞部22(如第2C’圖所示之延伸於部分介電層200)，以調控靜電分佈，較佳地，可將靜電平均分佈至該承載結構2(或該基板20)之各介電層200。
又，該圍繞部22係具有複數電鍍導線222，其可導通該隔離部21之電流導引線且外露於該承載結構2之側面2c之處，如第2D圖所示之網狀，以於製作該基板20之各層線路層201時作為電鍍匯流排，因而於完成所有基板20之製作後，各該電鍍導線222會對應電性連接各該基板20 之線路層201，但該導電體221未電性連接該些電鍍導線222。較佳地，該些電鍍導線222之至少兩者可依需求相互串連，如第2D圖所示，於該承載結構2之側面2c之處，至少兩該電鍍導線222之間藉由至少一延伸導線223相連接，使兩該電鍍導線222呈現串連狀態，以利於將靜電集合於該圍繞部22(該電鍍導線222或延伸導線223)中，進而調控靜電分佈，例如，可將靜電平均分佈至該承載結構2(或該基板20)之各介電層200。
另外，藉由該承載結構2進行後續封裝製程，以形成一封裝結構3，如第2A’及2B圖所示。例如，該封裝結構3之製作係先將電子元件30設於該基板20上並電性連接該基板20，再以包覆層32形成於該保留區A上以包覆該電子元件30，且可依需求將該包覆層32形成於該移除區B上以覆蓋該圍繞部22。
所述之電子元件30係依所需之數量佈設於各該基板20上，其可為主動元件、被動元件或其組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。具體地，該電子元件30係具有複數電極墊(圖略)，其可藉由複數如銲線(圖未示)之導電元件以打線方式電性連接該電性接觸墊202；或者，該電子元件30之電極墊藉由複數如導電凸塊31之導電元件以覆晶方式設於該基板20上並電性連接該電性接觸墊202；亦或，該電子元件30可嵌埋於該基板20中或直接結合該線路層201。然而，有關該電子元件30配置及電性連接該基板20之方 式不限於上述。
所述之包覆層32係結合至該承載結構2之第一側2a上，其為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，並其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構2之第一側2a上。然而，有關該包覆層32之材質及製作方式並不限於上述。
因此，本發明之封裝結構3係藉由該圍繞部22於該承載結構2之第一側2a具有開口220之設計，以減少該承載結構2之第一側2a之絕緣層之面積，因而能減少該靜電於該承載結構2中之整體積存空間，故於封裝製程中，能減少該基板20(如該介電層200或該防銲層203)中靜電壓之積存量，以避免該靜電觸發產生之電流量超出該電子元件30之靜電流負荷之極限量之情況發生，進而避免靜電破壞產品之問題。
再者，藉由該導電體221作為電荷導引路徑，以將靜電經由該開口220導引集中於該圍繞部22中，故於封裝製程中，不僅能降低該基板20之靜電積存量，且能分散靜電之分佈(分散於該圍繞部22與該基板20)，以避免靜電大量積存於該保留區A或該基板20，避免該靜電觸發產生之電流量超出該電子元件30之靜電流負荷之極限量，進而降低產品於生產過程中遭受靜電破壞之風險。
又，藉由該些電鍍導線222之串連設計，以將靜電導引集中於該圍繞部22中，故於封裝製程中，不僅能降低該 基板20之靜電積存量，且於靜電觸發產生電流時，該些電鍍導線222之間形成短路，致使靜電觸發產生之電流無法流過該電子元件30，進而降低產品於生產過程中遭受靜電破壞之風險。
綜上所述，本發明之承載結構及封裝結構，係藉由圍繞部具開口及導電體之設計，以減少基板上之靜電量或調控基板之靜電分佈，故相較於習知技術，本發明之結構不僅令靜電觸發產生之電流量不會超過電子元件之靜電流負荷之極限量，且能避免承載結構發生變形，更無需縮減基板之可佈線面積，因而能降低封裝製程之成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (10)

  1. 一種承載結構，係定義有相鄰接之保留區與移除區，該承載結構包括：複數基板，係位於該保留區；一隔離部，係位於該保留區且連結於各該基板之間；以及一圍繞部，係位於該移除區且形成有至少一開口。
  2. 一種封裝結構，係包括：一承載結構，係定義有相鄰接之保留區與移除區，其中，該承載結構包含有：複數基板，係位於該保留區；一隔離部，係位於該保留區且連結於各該基板之間；及一圍繞部，係位於該移除區且形成有至少一開口；複數電子元件，係設於各該基板上並電性連接該基板；以及包覆層，係形成於該保留區上以包覆該複數電子元件。
  3. 如申請專利範圍第1或2項所述之結構，其中，該基板係包含有至少一線路層。
  4. 如申請專利範圍第1或2項所述之結構，其中，該圍繞部之表面係形成有一絕緣層。
  5. 如申請專利範圍第4項所述之結構，其中，該開口係形成於該絕緣層上。
  6. 如申請專利範圍第1或2項所述之結構，其中，該開口中係形成有導電體。
  7. 如申請專利範圍第6項所述之結構，其中，該導電體係貫穿該圍繞部。
  8. 如申請專利範圍第6項所述之結構，其中，該導電體係未貫穿該圍繞部。
  9. 如申請專利範圍第1或2項所述之結構，其中，該圍繞部係具有複數電鍍導線，其對應電性連接各該基板。
  10. 如申請專利範圍第9項所述之結構，其中，該複數電鍍導線之至少兩者係相互串連。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140175623A1 (en) * 2010-05-14 2014-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
TW201603215A (zh) * 2014-07-11 2016-01-16 矽品精密工業股份有限公司 封裝結構及其製法
TWI619224B (zh) * 2017-03-30 2018-03-21 矽品精密工業股份有限公司 電子封裝件及其製法
TW201838136A (zh) * 2017-04-12 2018-10-16 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI279894B (en) * 2001-11-14 2007-04-21 Advanced Semiconductor Eng Package substrate having electrostatic discharge protection mechanism
CN1251325C (zh) * 2002-07-29 2006-04-12 矽统科技股份有限公司 晶片封装基板
CN100337325C (zh) * 2002-08-26 2007-09-12 日月光半导体制造股份有限公司 具有静电放电防护的封装基板
TWI222186B (en) * 2003-09-04 2004-10-11 Advanced Semiconductor Eng Method for manufacturing package substrate strip and structure from the same
CN101064261A (zh) * 2006-04-25 2007-10-31 矽品精密工业股份有限公司 半导体封装件及其呈阵列排列的基片结构与制法
JP2008020529A (ja) * 2006-07-11 2008-01-31 Toshiba Matsushita Display Technology Co Ltd 表示素子
TWI346996B (en) * 2007-12-28 2011-08-11 Powertech Technology Inc Substrate strip for semiconductor packages
TWI584418B (zh) * 2016-05-16 2017-05-21 Egis Tech Inc 指紋感測器及其封裝方法
KR101942728B1 (ko) * 2016-11-04 2019-01-28 삼성전기 주식회사 어레이 기판 및 이를 이용한 전자 소자 모듈

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140175623A1 (en) * 2010-05-14 2014-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
TW201603215A (zh) * 2014-07-11 2016-01-16 矽品精密工業股份有限公司 封裝結構及其製法
TWI619224B (zh) * 2017-03-30 2018-03-21 矽品精密工業股份有限公司 電子封裝件及其製法
TW201838136A (zh) * 2017-04-12 2018-10-16 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法

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