WO2008105496A1 - キャパシタ搭載インターポーザ及びその製造方法 - Google Patents

キャパシタ搭載インターポーザ及びその製造方法 Download PDF

Info

Publication number
WO2008105496A1
WO2008105496A1 PCT/JP2008/053523 JP2008053523W WO2008105496A1 WO 2008105496 A1 WO2008105496 A1 WO 2008105496A1 JP 2008053523 W JP2008053523 W JP 2008053523W WO 2008105496 A1 WO2008105496 A1 WO 2008105496A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
substrate
interposer
main body
electrode
Prior art date
Application number
PCT/JP2008/053523
Other languages
English (en)
French (fr)
Inventor
Akinobu Shibuya
Yasuhiro Ishii
Toru Mori
Koichi Takemura
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009501297A priority Critical patent/JP5463908B2/ja
Priority to US12/529,378 priority patent/US20100044089A1/en
Publication of WO2008105496A1 publication Critical patent/WO2008105496A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

　キャパシタ搭載インターポーザ（１００）は、ビアプラグ（１２）が形成されたプラグ基板（１０）と、キャパシタが形成されたキャパシタ基板（２０）とを有する。キャパシタ基板（２０）は、基板本体（２１）と、基板本体の主面上に形成されたキャパシタ（２２）と、キャパシタを覆うカバー絶縁膜（２５）と、キャパシタの電極に接続されカバー絶縁膜の表面に形成された端子電極（２６）と、基板本体の裏面に形成された電極パッド（２４）と、端子電極と電極パッドとを接続するビアプラグ２３とを備える。プラグ基板（１０）は、基板本体（１１）と、基板本体の主面上に、キャパシタ基板の端子電極に対応して形成された電極パッド（１３）と、基板本体を貫通し電極パッドに接続されるビアプラグ（１２）とを備える。
PCT/JP2008/053523 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法 WO2008105496A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009501297A JP5463908B2 (ja) 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法
US12/529,378 US20100044089A1 (en) 2007-03-01 2008-02-28 Interposer integrated with capacitors and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-051131 2007-03-01
JP2007051131 2007-03-01

Publications (1)

Publication Number Publication Date
WO2008105496A1 true WO2008105496A1 (ja) 2008-09-04

Family

ID=39721320

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053523 WO2008105496A1 (ja) 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法

Country Status (3)

Country Link
US (1) US20100044089A1 (ja)
JP (1) JP5463908B2 (ja)
WO (1) WO2008105496A1 (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014531756A (ja) * 2011-09-14 2014-11-27 インヴェンサス・コーポレイション 低ｃｔｅインターポーザ
US9245814B2 (en) 2013-04-05 2016-01-26 Hoya Corporation Substrate assembly, method of manufacturing substrate assembly and method of manufacturing chip package
JP2018133362A (ja) * 2017-02-13 2018-08-23 Tdk株式会社 電子部品内蔵基板
WO2018211614A1 (ja) * 2017-05-17 2018-11-22 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
JP2022508408A (ja) * 2019-08-23 2022-01-19 エスケイシー・カンパニー・リミテッド パッケージング基板及びこれを含む半導体装置
US11437308B2 (en) 2019-03-29 2022-09-06 Absolics Inc. Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus
US11652039B2 (en) 2019-03-12 2023-05-16 Absolics Inc. Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
US11967542B2 (en) 2019-03-12 2024-04-23 Absolics Inc. Packaging substrate, and semiconductor device comprising same
US11981501B2 (en) 2020-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8730647B2 (en) * 2008-02-07 2014-05-20 Ibiden Co., Ltd. Printed wiring board with capacitor
US8765549B2 (en) 2012-04-27 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US8878338B2 (en) 2012-05-31 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US20140151095A1 (en) * 2012-12-05 2014-06-05 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
CN105074825B (zh) * 2013-03-15 2019-01-08 英特尔公司 基于集成电容器的配电
US9692188B2 (en) 2013-11-01 2017-06-27 Quell Corporation Flexible electrical connector insert with conductive and non-conductive elastomers
EP3063836B1 (en) 2013-11-01 2020-12-02 Quell Corporation Very low inductance flexible electrical connector insert
JP6574207B2 (ja) 2014-05-05 2019-09-11 スリーディー グラス ソリューションズ，インク３Ｄ Ｇｌａｓｓ Ｓｏｌｕｔｉｏｎｓ，Ｉｎｃ 光活性基板を製造する、２ｄ及び３ｄインダクタ、アンテナ、並びにトランス
TWI571185B (zh) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US20220157524A1 (en) * 2016-02-25 2022-05-19 3D Glass Solutions, Inc. 3D Capacitor and Capacitor Array Fabricating Photoactive Substrates
KR20180072974A (ko) * 2016-12-22 2018-07-02 삼성전기주식회사 적층형 커패시터 및 그 실장 기판
KR102419713B1 (ko) 2017-12-15 2022-07-13 3디 글래스 솔루션즈 인코포레이티드 결합 전송 라인 공진 rf 필터
AU2020253553A1 (en) 2019-04-05 2021-10-28 3D Glass Solutions, Inc. Glass based empty substrate integrated waveguide devices
CA3177603C (en) 2020-04-17 2024-01-09 3D Glass Solutions, Inc. Broadband induction
US20220310777A1 (en) * 2021-03-26 2022-09-29 Intel Corporation Integrated circuit package redistribution layers with metal-insulator-metal (mim) capacitors
US20240079352A1 (en) * 2022-09-02 2024-03-07 Qualcomm Incorporated Integrated circuit (ic) packages employing capacitor interposer substrate with aligned external interconnects, and related fabrication methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002008942A (ja) * 2000-06-16 2002-01-11 Fujitsu Ltd コンデンサ装置、コンデンサ装置の製造方法及びコンデンサ装置が実装されたモジュール
JP2005050883A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
JP2006253631A (ja) * 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4349862A (en) * 1980-08-11 1982-09-14 International Business Machines Corporation Capacitive chip carrier and multilayer ceramic capacitors
US7226654B2 (en) * 2003-07-29 2007-06-05 Kyocera Corporation Laminated wiring board and its mounting structure
US7132743B2 (en) * 2003-12-23 2006-11-07 Intel Corporation Integrated circuit package substrate having a thin film capacitor structure
JP4671829B2 (ja) * 2005-09-30 2011-04-20 富士通株式会社 インターポーザ及び電子装置の製造方法
JP5103724B2 (ja) * 2005-09-30 2012-12-19 富士通株式会社 インターポーザの製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002008942A (ja) * 2000-06-16 2002-01-11 Fujitsu Ltd コンデンサ装置、コンデンサ装置の製造方法及びコンデンサ装置が実装されたモジュール
JP2005050883A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
JP2006253631A (ja) * 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014531756A (ja) * 2011-09-14 2014-11-27 インヴェンサス・コーポレイション 低ｃｔｅインターポーザ
US9245814B2 (en) 2013-04-05 2016-01-26 Hoya Corporation Substrate assembly, method of manufacturing substrate assembly and method of manufacturing chip package
JP2018133362A (ja) * 2017-02-13 2018-08-23 Tdk株式会社 電子部品内蔵基板
WO2018211614A1 (ja) * 2017-05-17 2018-11-22 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
JP6427747B1 (ja) * 2017-05-17 2018-11-28 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
US11652039B2 (en) 2019-03-12 2023-05-16 Absolics Inc. Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
US11967542B2 (en) 2019-03-12 2024-04-23 Absolics Inc. Packaging substrate, and semiconductor device comprising same
US11437308B2 (en) 2019-03-29 2022-09-06 Absolics Inc. Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus
JP7104245B2 (ja) 2019-08-23 2022-07-20 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US11469167B2 (en) 2019-08-23 2022-10-11 Absolics Inc. Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
JP2022508408A (ja) * 2019-08-23 2022-01-19 エスケイシー・カンパニー・リミテッド パッケージング基板及びこれを含む半導体装置
US11728259B2 (en) 2019-08-23 2023-08-15 Absolics Inc. Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
JP7416868B2 (ja) 2019-08-23 2024-01-17 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US11981501B2 (en) 2020-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied

Also Published As

Publication number Publication date
US20100044089A1 (en) 2010-02-25
JPWO2008105496A1 (ja) 2010-06-03
JP5463908B2 (ja) 2014-04-09

Similar Documents

Publication Publication Date Title
WO2008105496A1 (ja) キャパシタ搭載インターポーザ及びその製造方法
WO2008093414A1 (ja) 半導体装置及びその製造方法
TW200727421A (en) Package structure and fabricating method thereof
WO2008126738A1 (ja) インターポーザ
WO2010014550A3 (en) Method and apparatus for packaging crash sensors
WO2009075551A3 (en) Semiconductor light emitting device and method of fabricating the same
WO2008021982A3 (en) Surface mountable chip
WO2006094025A3 (en) Fabricated adhesive microstructures for making an electrical connection
WO2008146243A3 (en) An electronic device comprising a convertible structure, and a method of manufacturing an electronic device
TW200513650A (en) Micro-electromechanical probe circuit film, method for making the same and applications thereof
WO2010038179A3 (en) An oled device and an electronic circuit
SG169929A1 (en) Semiconductor device and method of forming cavity in pcb containing encapsulant or dummy die having cte similar to cte of large array wlcsp
WO2007117829A3 (en) Method for bonding a semiconductor substrate to a metal substrate
WO2009143249A3 (en) Grounding electrode
WO2012058011A3 (en) Interconnect structure with enhanced reliability
EP1826828A3 (en) Photovoltaic apparatus
WO2009001170A3 (en) Filter having impedance matching circuits
WO2009031258A1 (ja) 水晶デバイス及び水晶デバイスの製造方法
WO2010038976A3 (en) Semiconductor light emitting device and method of manufacturing the same
WO2008079467A3 (en) Microphone array with electromagnetic interference shielding means
WO2008108350A1 (ja) 容量素子、プリント配線基板、半導体パッケージ及び半導体回路
WO2009075079A1 (ja) 回路板、回路板の製造方法およびカバーレイフィルム
WO2008155967A1 (ja) 部品内蔵基板及びその製造方法
WO2012149466A3 (en) Body associated device and method of making same
TW201130093A (en) Substrate for mounting element, and method for manufacturing the substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08712094

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009501297

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 12529378

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08712094

Country of ref document: EP

Kind code of ref document: A1