WO2008126738A1 - インターポーザ - Google Patents

インターポーザ Download PDF

Info

Publication number
WO2008126738A1
WO2008126738A1 PCT/JP2008/056565 JP2008056565W WO2008126738A1 WO 2008126738 A1 WO2008126738 A1 WO 2008126738A1 JP 2008056565 W JP2008056565 W JP 2008056565W WO 2008126738 A1 WO2008126738 A1 WO 2008126738A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode section
pad
post
main body
holes
Prior art date
Application number
PCT/JP2008/056565
Other languages
English (en)
French (fr)
Inventor
Shuichi Kawano
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Priority to CN200880000049XA priority Critical patent/CN101542722B/zh
Priority to EP08739676A priority patent/EP2136399A4/en
Priority to JP2008526707A priority patent/JP4695192B2/ja
Publication of WO2008126738A1 publication Critical patent/WO2008126738A1/ja

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0179Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09763Printed component having superposed conductors, but integrated in one circuit layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

 インターポーザ10は、第1及び第2スルーホール14,16を有する基板本体12と、第1及び第2スルーホール14,16の内面並びに基板本体12の第1表面に形成された第1電極部22に誘電体層24と第2電極部26とを積層してなるコンデンサ20と、第1スルーホール14内において第2電極部26に囲まれて形成された空間内に電気絶縁材を充填してなる絶縁層18と、この絶縁層18を貫通し一端が第1電極部22に電気的に接続されると共に第2電極部26と電気的に絶縁されてなる第1ポスト40とを備えている。この第1ポスト40の両端には、それぞれ第1パッド31と第2パッド32が設けられている。一方、第2スルーホール16内には、外周面が第2電極部26に接する一方、第1電極部22とは電気的に絶縁されてなる第2ポストを備える。この第2ポスト42の両端には、それぞれ第3パッド33と第4パッド34が設けられている。
PCT/JP2008/056565 2007-04-10 2008-04-02 インターポーザ WO2008126738A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200880000049XA CN101542722B (zh) 2007-04-10 2008-04-02 中继基板
EP08739676A EP2136399A4 (en) 2007-04-10 2008-04-02 ZWISCHENSTÜCK
JP2008526707A JP4695192B2 (ja) 2007-04-10 2008-04-02 インターポーザ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US91097007P 2007-04-10 2007-04-10
US60/910,970 2007-04-10
US11/969,606 2008-01-04
US11/969,606 US7589394B2 (en) 2007-04-10 2008-01-04 Interposer

Publications (1)

Publication Number Publication Date
WO2008126738A1 true WO2008126738A1 (ja) 2008-10-23

Family

ID=39853518

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/056565 WO2008126738A1 (ja) 2007-04-10 2008-04-02 インターポーザ

Country Status (6)

Country Link
US (1) US7589394B2 (ja)
EP (1) EP2136399A4 (ja)
JP (1) JP4695192B2 (ja)
KR (1) KR20090042753A (ja)
CN (1) CN101542722B (ja)
WO (1) WO2008126738A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079719A (ja) * 2010-09-30 2012-04-19 Chino Corp 機能追加型基板
JP2012227266A (ja) * 2011-04-18 2012-11-15 Shinko Electric Ind Co Ltd 配線基板、半導体装置及び配線基板の製造方法
JP2012227267A (ja) * 2011-04-18 2012-11-15 Shinko Electric Ind Co Ltd 配線基板、半導体装置及び配線基板の製造方法

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7833893B2 (en) * 2007-07-10 2010-11-16 International Business Machines Corporation Method for forming conductive structures
US20090189285A1 (en) * 2008-01-24 2009-07-30 Colt Jr John Zuidema On chip thermocouple and/or power supply and a design structure for same
US20100123993A1 (en) * 2008-02-13 2010-05-20 Herzel Laor Atomic layer deposition process for manufacture of battery electrodes, capacitors, resistors, and catalyzers
US8247288B2 (en) * 2009-07-31 2012-08-21 Alpha & Omega Semiconductor Inc. Method of integrating a MOSFET with a capacitor
JP5500936B2 (ja) * 2009-10-06 2014-05-21 イビデン株式会社 回路基板及び半導体モジュール
US20110089531A1 (en) * 2009-10-16 2011-04-21 Teledyne Scientific & Imaging, Llc Interposer Based Monolithic Microwave Integrate Circuit (iMMIC)
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
CN102610608B (zh) * 2011-01-19 2014-10-15 万国半导体股份有限公司 集成一个电容的金属氧化物半导体场效应晶体管
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
KR101846388B1 (ko) * 2011-11-29 2018-04-09 한국전자통신연구원 수직구조 캐패시터 및 수직구조 캐패시터의 형성 방법
CN103219302B (zh) * 2012-01-19 2016-01-20 欣兴电子股份有限公司 穿孔中介板
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US20130242493A1 (en) * 2012-03-13 2013-09-19 Qualcomm Mems Technologies, Inc. Low cost interposer fabricated with additive processes
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
TWI497661B (zh) * 2012-08-15 2015-08-21 Ind Tech Res Inst 半導體基板
US9343393B2 (en) 2012-08-15 2016-05-17 Industrial Technology Research Institute Semiconductor substrate assembly with embedded resistance element
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9408313B2 (en) * 2012-12-28 2016-08-02 Unimicron Technology Corp. Packaging substrate and method of fabricating the same
TWM459517U (zh) * 2012-12-28 2013-08-11 Unimicron Technology Corp 封裝基板
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US10014843B2 (en) * 2013-08-08 2018-07-03 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic structures with embedded filters
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10950689B2 (en) * 2015-09-23 2021-03-16 Nanyang Technological University Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
WO2018026002A1 (ja) * 2016-08-04 2018-02-08 大日本印刷株式会社 貫通電極基板及び実装基板
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326305A (ja) 2000-05-12 2001-11-22 Shinko Electric Ind Co Ltd 半導体装置用インターポーザー、その製造方法および半導体装置
JP2001352017A (ja) 2000-06-06 2001-12-21 Fujitsu Ltd 電子装置実装基板及びその製造方法
JP2005203680A (ja) * 2004-01-19 2005-07-28 Murata Mfg Co Ltd インターポーザキャパシタの製造方法
JP2006253631A (ja) * 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法
JP2006278553A (ja) * 2005-03-28 2006-10-12 Fujitsu Ltd 電子回路部品、半導体パッケージ、および電子回路部品の作製方法
EP1758151A2 (en) 2005-08-24 2007-02-28 Tokyo Electron Limited Capacitor and manufacturing method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101084525B1 (ko) * 1999-09-02 2011-11-18 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
US6446317B1 (en) * 2000-03-31 2002-09-10 Intel Corporation Hybrid capacitor and method of fabrication therefor
TW525417B (en) * 2000-08-11 2003-03-21 Ind Tech Res Inst Composite through hole structure
US6532143B2 (en) * 2000-12-29 2003-03-11 Intel Corporation Multiple tier array capacitor
JP3711343B2 (ja) * 2002-06-26 2005-11-02 株式会社トッパンNecサーキットソリューションズ 印刷配線板及びその製造方法並びに半導体装置
KR100455891B1 (ko) * 2002-12-24 2004-11-06 삼성전기주식회사 커패시터 내장형 인쇄회로기판 및 그 제조 방법
US7233061B1 (en) * 2003-10-31 2007-06-19 Xilinx, Inc Interposer for impedance matching
CN101271890B (zh) * 2005-02-14 2010-06-02 富士通株式会社 半导体器件及其制造方法与电容器结构及其制造方法
US20080017407A1 (en) * 2006-07-24 2008-01-24 Ibiden Co., Ltd. Interposer and electronic device using the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326305A (ja) 2000-05-12 2001-11-22 Shinko Electric Ind Co Ltd 半導体装置用インターポーザー、その製造方法および半導体装置
JP2001352017A (ja) 2000-06-06 2001-12-21 Fujitsu Ltd 電子装置実装基板及びその製造方法
JP2005203680A (ja) * 2004-01-19 2005-07-28 Murata Mfg Co Ltd インターポーザキャパシタの製造方法
JP2006253631A (ja) * 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法
JP2006278553A (ja) * 2005-03-28 2006-10-12 Fujitsu Ltd 電子回路部品、半導体パッケージ、および電子回路部品の作製方法
EP1758151A2 (en) 2005-08-24 2007-02-28 Tokyo Electron Limited Capacitor and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2136399A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079719A (ja) * 2010-09-30 2012-04-19 Chino Corp 機能追加型基板
JP2012227266A (ja) * 2011-04-18 2012-11-15 Shinko Electric Ind Co Ltd 配線基板、半導体装置及び配線基板の製造方法
JP2012227267A (ja) * 2011-04-18 2012-11-15 Shinko Electric Ind Co Ltd 配線基板、半導体装置及び配線基板の製造方法

Also Published As

Publication number Publication date
EP2136399A1 (en) 2009-12-23
JPWO2008126738A1 (ja) 2010-07-22
CN101542722A (zh) 2009-09-23
US7589394B2 (en) 2009-09-15
US20080253097A1 (en) 2008-10-16
CN101542722B (zh) 2010-12-22
EP2136399A4 (en) 2011-05-25
KR20090042753A (ko) 2009-04-30
JP4695192B2 (ja) 2011-06-08

Similar Documents

Publication Publication Date Title
WO2008126738A1 (ja) インターポーザ
WO2009050829A1 (ja) 配線基板及びその製造方法
TW200726335A (en) Substrate structure with capacitance component embedded therein and method for fabricating the same
WO2009037346A3 (de) Elektrisches vielschichtbauelement
WO2008105496A1 (ja) キャパシタ搭載インターポーザ及びその製造方法
WO2012074783A3 (en) Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
JP2010003295A5 (ja)
WO2008021982A3 (en) Surface mountable chip
WO2009143249A3 (en) Grounding electrode
WO2006108272A3 (en) Metal/fullerene anode structure and application of same
TW200833211A (en) Circuit board structure with capacitor embedded therein and method for fabricating the same
WO2009013826A1 (ja) 半導体装置
WO2007121412A3 (en) Conductive polymer electronic devices with surface mountable configuration and methods for manufacturing same
WO2011034642A3 (en) Wrapped stator coil
TW200715325A (en) Feedthrough multilayer capacitor array
TW200735147A (en) Multilayer feedthrough capacitor array
TW200723988A (en) Via structure of printed circuit board
JP6461871B2 (ja) 変換器
WO2008155967A1 (ja) 部品内蔵基板及びその製造方法
TW200710893A (en) Multilayer capacitor
TW200729252A (en) Chip type electric device and method, and display device including the same
TW200943329A (en) A laminated electronic part and its manufacturing method
WO2007070356A3 (en) Package using array capacitor core
WO2006119753A3 (de) Elektrisches durchführungsbauelement mit vielschichtstruktur und verfahren zu dessen herstellung
TW200727747A (en) Circuit board device with fine conducting structure

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880000049.X

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2008526707

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2008739676

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020087016360

Country of ref document: KR

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08739676

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE