JP2022508408A - パッケージング基板及びこれを含む半導体装置 - Google Patents
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Abstract
Description
本出願は、2019年8月23日に出願された米国仮出願特許出願番号62/890,689による優先権の利益を有し、前記優先権の基礎出願の内容はいずれも本出願の内容に含まれる。
韓国公開特許公報第10-2019-0008103号、
韓国公開特許公報第10-2016-0114710号、
韓国登録特許公報第10-1468680号などがある。
互いに向かい合う第1面及び第2面を有するガラス基板を含むコア層;及び
前記ガラス基板を厚さ方向に貫通する多数のコアビア;を含み、
前記コアビアは、開口部が円形である円形コアビアと、開口部のx-y方向のアスペクト比が1.2以上の非円形コアビアとを含み、
前記非円形コアビア上には、1個又は2個以上の電力伝達素子が位置し得る。
前記非円形ビア分配パターンは、
前記非円形コアビアの内部空間が全て電気伝導性層で充填された充填ビアパターン;及び
前記非円形コアビアの内部空間の一部は電気伝導性層で充填され、残りの部分は絶縁層で充填された複合型ビアパターン;
のうちいずれか一つ以上を含むことができる。
前記非円形コアビアの内部空間が全て電気伝導性層で充填された充填ビアパターンI;及び
前記非円形コアビアはコンフォーマルビアパターンを含み、その内部空間が全て電気伝導性層で充填された充填ビアパターンII;
のうちいずれか一つ以上のパターンを含むことができる。
前記非円形コアビアの内径面と実質的に当接するように電気伝導性層が形成され、前記非円形コアビア内の残りの部分に絶縁層が充填された複合型ビアパターンI;及び
前記非円形コアビアの内径面と実質的に当接するように絶縁層が形成され、前記絶縁層以外の空間に電気伝導性層が形成された複合型ビアパターンII;
のうちいずれか一つ以上を含むことができる。
1以上の半導体素子を含む半導体素子部;
前記半導体素子部と電気的に連結されるパッケージング基板;及び
前記パッケージング基板と電気的に連結され、前記半導体素子に外部の電気的信号を伝達し、前記半導体素子を互いに連結するマザーボード;を含むことができる。
30:半導体素子部 32:第1半導体素子
34:第2半導体素子 36:第3半導体素子
20:パッケージング基板 22:コア層
223:コア絶縁層 21、21a:ガラス基板
213:第1面 214:第2面
23:コアビア 231a:円形コアビア
231b:非円形コアビア 233:第1開口部
234:第2開口部 235:最小内径部
24:コア分配層 241:コア分配パターン
241a:第1面分配パターン 241b:コアビア分配パターン
241c:第2面分配パターン 242:非円形ビア分配パターン
242a:コンフォーマルビアパターン 242b:充填ビアパターンI
242c:充填ビアパターンII 242d:複合型ビアパターンI
242e:複合型ビアパターンII 26:上部層
25:上部分配層 251:上部分配パターン
252:ブラインドビア 253:上部絶縁層
27:上面接続層 271:上面接続電極
272:上面連結パターン 29:下部層
291:下部分配層 291a:下部分配パターン
291b:下部絶縁層 292:下面接続層
292a:下面接続電極 292b:下面連結パターン
48:電力伝達素子 481:電力伝達素子の電極
50:連結部 51:素子連結部
52:ボード連結部 60:カバー層
21b:ガラス欠陥 21c:シード層、プライマー層
21d:コア分配層 21e:コア分配層のエッチング層
23a:絶縁層 23b:絶縁層のエッチング層
23c:電気伝導性層 23d:電気伝導性層のエッチング層
23e:絶縁層 23f:絶縁層のエッチング層
23g:電気伝導性層 23h:電気伝導性層のエッチング層
Claims (10)
- 互いに向かい合う第1面及び第2面を有するガラス基板を含むコア層;及び
前記ガラス基板を厚さ方向に貫通する多数のコアビア;を含み、
前記コアビアは、開口部が円形である円形コアビアと、開口部のx-y方向のアスペクト比が1.2以上の非円形コアビアと、を含み、
前記非円形コアビア上には、1個又は2個以上の電力伝達素子が位置する、パッケージング基板。 - 前記非円形コアビアの内部には、最小厚さが5μm以上の電気伝導性層が位置する、請求項1に記載のパッケージング基板。
- 前記非円形コアビアの内部には、前記非円形コアビアの内部体積の30%以上を充填する電気伝導性層が位置する、請求項1に記載のパッケージング基板。
- 前記非円形コアビアは、その開口部の形態が楕円形、四角形、L型、又はU型であるものを含む、請求項1に記載のパッケージング基板。
- 前記非円形コアビアの内部に位置する非円形ビア分配パターンを含み、
前記非円形ビア分配パターンは、
前記非円形コアビアの内部空間が全て電気伝導性層で充填された充填ビアパターン;及び
前記非円形コアビアの内部空間の一部は電気伝導性層で充填され、残りの部分は絶縁層で充填された複合型ビアパターン;
のうちいずれか一つ以上を含む、請求項1に記載のパッケージング基板。 - 前記充填ビアパターンは、
前記非円形コアビアの内部空間が全て電気伝導性層で充填された充填ビアパターンI;及び
前記非円形コアビアは、内径面を電気伝導性層が覆う形態であるコンフォーマルビアパターンを含み、その内部空間が全て電気伝導性層で充填された充填ビアパターンII;
のうちいずれか一つ以上のパターンを含む、請求項5に記載のパッケージング基板。 - 前記複合型ビアパターンは、
前記非円形コアビアの内径面と実質的に当接するように電気伝導性層が形成され、前記非円形コアビア内の残りの部分に絶縁層が充填された複合型ビアパターンI;及び
前記非円形コアビアの内径面と実質的に当接するように絶縁層が形成され、前記絶縁層以外の空間に電気伝導性層が形成された複合型ビアパターンII;
のうちいずれか一つ以上を含む、請求項5に記載のパッケージング基板。 - 前記非円形ビア分配パターンの電気伝導性層と前記電力伝達素子の電極とが連結される、請求項5に記載のパッケージング基板。
- 前記コアビアは、前記第1面と接する第1開口部;前記第2面と接する第2開口部;及び前記第1開口部と第2開口部とを連結する全体のコアビアにおいてその内径が最も狭い区域である最小内径部;を含む、請求項1に記載のパッケージング基板。
- 1以上の半導体素子を含む半導体素子部;
前記半導体素子部と電気的に連結されるパッケージング基板;及び
前記パッケージング基板と電気的に連結され、前記半導体素子に外部の電気的信号を伝達し、前記半導体素子を互いに連結するマザーボード;を含み、前記パッケージング基板は、請求項1によるパッケージング基板である、半導体装置。
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EP3905323A4 (en) | 2022-10-19 |
KR102413117B1 (ko) | 2022-06-24 |
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US11728259B2 (en) | 2023-08-15 |
CN113366633B (zh) | 2022-07-12 |
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EP3905323A1 (en) | 2021-11-03 |
US20210391243A1 (en) | 2021-12-16 |
JP7416868B2 (ja) | 2024-01-17 |
JP2022133442A (ja) | 2022-09-13 |
JP7104245B2 (ja) | 2022-07-20 |
CN113366633A (zh) | 2021-09-07 |
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