CN104733379B - 在半导体管芯上形成细节距的rdl的半导体器件和方法 - Google Patents

在半导体管芯上形成细节距的rdl的半导体器件和方法 Download PDF

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CN104733379B
CN104733379B CN201410814198.7A CN201410814198A CN104733379B CN 104733379 B CN104733379 B CN 104733379B CN 201410814198 A CN201410814198 A CN 201410814198A CN 104733379 B CN104733379 B CN 104733379B
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conductive layer
sealant
semiconductor element
conductive
layer
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CN104733379A (zh
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P.C.马里穆图
林耀剑
崔源璟
沈权
沈一权
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在半导体管芯上形成细节距的RDL的半导体器件和方法。半导体器件具有包括多个导电迹线的第一导电层。第一导电层形成在衬底上。利用窄节距形成导电迹线。在第一导电层上放置第一半导体管芯和第二半导体管芯。在第一和第二半导体管芯上沉积第一密封剂。移除衬底。在第一密封剂上沉积第二密封剂。在第一导电层和第二密封剂上形成堆积互连结构。堆积互连结构包括第二导电层。在第一密封剂中放置第一无源器件。在第二密封剂中放置第二无源器件。在第二密封剂中放置垂直互连单元。第三导电层形成在第二密封剂上并且经由垂直互连单元电气连接到堆积互连结构。

Description

在半导体管芯上形成细节距的RDL的半导体器件和方法
技术领域
本发明总地涉及半导体器件，并且更具体地，涉及在扇出型封装中的半导体管芯上形成细节距的RDL的半导体器件和方法。
背景技术
半导体器件常常出现在现代电子产品中。半导体器件在电气部件的数量和密度上改变。分立的半导体器件一般包含一种类型的电气部件，例如，发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含数百到数百万的电子部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行广泛的功能，诸如信号处理、高速计算、发送和接收电磁信号、控制电子器件、将阳光变换成电力以及为电视显示创建视觉投影。半导体器件出现在娱乐、通信、功率转换、网络、计算机和消费产品的领域。半导体器件还出现在军事应用、航空、汽车、工业控制以及办公装备中。
半导体器件利用半导体材料的电气属性。半导体材料的结构允许其电气导电性由电场或基电流的施加或通过掺杂处理来操纵。掺杂将杂质引入半导体材料以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电气电流的流动。通过改变掺杂的级别和电场或基电流的施加，晶体管或者促进或者限制电气电流的流动。包括电阻器、电容器和电感器的无源结构创建对于执行各种电气功能必要的在电压与电流之间的关系。无源和有源结构电气连接以形成电路，所述电路使半导体器件能够执行高速操作和其他有用功能。
半导体器件一般使用两种复杂的制造工艺来制造，即前端制造和后端制造，每种都可能涉及数百个步骤。前端制造涉及多个管芯在半导体晶圆的表面上的形成。每个半导体管芯典型地是相同的并且包含通过电气连接有源和无源部件形成的电路。后端制造涉及从完成后的晶圆单体化（singulating）个体半导体管芯，并封装该管芯以提供结构支持和环境隔离。如本文中所使用的，术语“半导体管芯”指代单数和复数形式的单词二者，并因此，可以指代单个半导体器件和多个半导体器件二者。
半导体制造的一个目标是产生较小的半导体器件。较小的器件典型地消耗较少功率、具有较高性能以及可以被更高效地生产。另外，较小的半导体器件具有较小的覆盖区，这对于较小的最终产品而言是合乎期望的。较小的半导体管芯大小可以通过前端工艺中的改进来实现，从而产生具有较小的、较高密度的有源和无源部件的半导体管芯。后端工艺可以通过电气互连和封装材料中的改进来产生具有较小覆盖区的半导体器件封装。
实现较大集成和较小半导体器件的目的的一种途径是聚焦于2.5-D封装技术，即器件内的相邻半导体管芯之间的电气互连，和3-D封装技术，即，垂直堆叠的半导体管芯或层叠封装（PoP）的半导体器件之间的电气互连。
在扇出嵌入式晶圆级球栅阵列（Fo-eWLB）中，通过堆积互连结构来提供在相邻半导体管芯之间以及在半导体管芯与外部器件之间的电气互连。堆积互连结构形成在半导体管芯和密封剂上，密封剂围绕半导体管芯。堆积互连结构典型地包括多个重分布层（RDL）。当以细或窄节距的RDL来形成堆积互连结构时，密封的半导体管芯接合到临时载体以防止在形成堆积互连结构期间的翘曲，所述细或窄节距的RDL例如是具有5微米（μm）节距的RDL。在堆积互连结构形成之后，诸如导电凸起的多个互连结构形成在堆积互连结构上，并且然后移除临时载体。向密封的半导体管芯接合和解接合临时载体对制造过程添加了步骤，增加了制造时间和成本，并且减小了生产量。另外，以诸如2μm或更小的超细节距的RDL形成具有堆积互连结构的Fo-eWLB是困难的，并且涉及复杂的、高度受控的、昂贵的以及耗时的制造步骤。
在器件内的相邻半导体管芯之间以及在半导体管芯与外部器件之间的电气互连也可以通过在半导体封装内嵌入穿硅通孔（TSV）中介层（interposer）来实现。在2.5D TSV封装中，RDL形成在中介层上并且导电TSV形成穿过中介层以提供电气互连。导电TSV和RDL在放置在中介层上的半导体管芯之间以及在半导体管芯与外部器件之间路由信号。在TSV中介层上形成的RDL可伸缩到亚微尺寸，即，在纳米范围中；然而，形成TSV中介层封装涉及复杂的、昂贵的并且耗时的制造步骤。另外，TSV中介层的垂直互连消耗空间并且增加封装的整体高度。因此，TSV中介层封装不能满足较小半导体器件的X、Y和Z，即长度、宽度和高度要求。
发明内容
存在对成本有效的半导体封装的需要，所述成本有效的半导体封装并入RDL，该RDL具有超窄节距的TSV中介层封装和小形状因子，即，Fo-eWLB封装的较小X、Y和Z尺寸。因此，在一个实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供衬底；在衬底上形成第一导电层；将半导体管芯放置在第一导电层上；将第一密封剂放置在半导体管芯上；移除衬底；将第二密封剂放置在第一密封剂上；以及在第一导电层和第二密封剂上形成互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供第一导电层；在第一导电层上放置第一半导体管芯；在第一半导体管芯上放置第一密封剂；以及在第一导电层上形成与第一半导体管芯相对的互连结构。
在另一实施例中，本发明是一种半导体器件，包括：第一导电层，其包括多个第一导电迹线。第一半导体管芯被放置在第一导电层的第一表面上。包括多个第二导电迹线的第二导电层被放置在第一导电层的与第一导电层的第一表面相对的第二表面上。第一导电迹线的节距小于第二导电迹线的节距。
在另一实施例中，本发明是半导体器件，其包括第一导电层和放置在第一导电层上的第一半导体管芯。在第一导电层上形成与第一半导体管芯相对的互连结构。
附图说明
图1图示了具有安装到印刷电路板（PCB）的表面的不同类型的封装的PCB；
图2a-2c图示了安装到PCB的代表性半导体封装的进一步细节；
图3a-3i图示了具有通过划片街区（saw street）分离的多个半导体管芯的半导体晶圆；
图4a-4s图示了形成包括细节距的RDL和堆积互连结构的半导体器件的过程；
图5图示了包括细节距的RDL和堆积互连结构的半导体器件；
图6a-6i图示了形成细节距的RDL并在半导体器件内嵌入无源器件的过程；
图7图示了包括细节距的RDL和嵌入的无源器件的半导体器件；
图8a-8i图示了形成细节距的RDL并在半导体器件内嵌入垂直互连单元的过程；
图9图示了包括细节距的RDL和嵌入的垂直互连单元的半导体器件；
图10a-10f图示了形成具有细节距的RDL和双侧RDL的半导体器件的过程；
图11图示了具有细节距的RDL和双侧RDL的半导体器件；以及
图12图示了包括细节距的RDL、双侧RDL和嵌入的无源器件的半导体器件。
具体实施方式
在以下描述中的一个或多个实施例中参照附图描述了本发明，在附图中，相似的标号代表相同或类似的元素。尽管在用于实现本发明的目的的最佳模式方面描述了本发明，但是本领域技术人员将意识到，该描述意图涵盖如可以包括在本发明的精神和范围内的替代、修改和等同物，本发明的精神和范围如由所附权利要求和如以下公开与附图所支持的权利要求的等同物所定义。
半导体器件一般使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及多个管芯在半导体晶圆的表面上的形成。晶圆上的每个管芯包含有源和无源电气部件，这些电气部件被电气连接以形成功能电气电路。诸如晶体管和二极管的有源电气部件具有控制电气电流的流动的能力。诸如电容器、电感器和电阻器的无源电气部件创建对于执行电气电路功能必要的在电压与电流之间的关系。
无源和有源部件通过包括以下的一系列处理步骤形成在半导体晶圆的表面上：掺杂、沉积、光刻、蚀刻以及平面化。掺杂通过诸如离子注入或热扩散的技术将杂质引入半导体材料中。掺杂过程通过响应于电场或基电流而动态地改变半导体材料导电性来修改有源器件中的半导体材料的电气导电性。晶体管包含按照需要布置的改变掺杂类型和程度的区，以使得晶体管能够在电场或基电流施加时促进或者限制电气电流的流动。
有源和无源部件通过具有不同电气属性的材料层来形成。这些层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可以涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电镀以及无电镀工艺。每个层一般被图案化以形成有源部件、无源部件或部件之间的电气连接的部分。
后端制造指代将完成后的晶圆切割或单体化成个体半导体管芯，并且然后封装半导体管芯以进行结构支持和环境隔离。为了单体化半导体管芯，晶圆沿着晶圆的称为划片街区或划线（scribe）的非功能区被刻痕并折断。使用激光切割工具或锯条来单体化晶圆。在单体化后，个体半导体管芯被安装到封装衬底，该封装衬底包括用于与其他系统部件互连的引脚或接触垫。形成在半导体管芯上的接触垫然后连接到封装内的接触垫。可以利用焊料隆起焊盘、柱形凸起（stud bump）、导电胶或丝焊来做出电气连接。密封剂或其他成型材料沉积在封装上以提供物理支持和电气隔离。然后将完成后的封装插入电气系统中，并且使半导体器件的功能性对于其他系统部件为可用。
图1图示了具有芯片载体衬底或PCB 52的电子器件50，PCB 52具有在PCB 52的表面上安装的多个半导体封装。电子器件50可以具有一种类型的半导体封装或者多种类型的半导体封装，这取决于应用。不同类型的半导体封装在图1中示出用于说明的目的。
电子器件50可以是使用半导体封装执行一个或多个电气功能的独立系统。可替代地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数字视频摄像机（DVC）或其他电子通信器件中的部分。可替代地，电子器件50可以是图形卡、网络接口卡或可以插入计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、射频（RF）电路、分立器件或其他半导体管芯或电气部件。小型化和重量减小对于要被市场接受的产品是必要的。半导体器件之间的距离可以降低以实现较高的密度。
在图1中，PCB 52提供了用于安装在PCB上的半导体封装的结构支持和电气互连的一般衬底。导电信号迹线54使用蒸发、电镀、无电镀、丝网印刷或其他合适的金属沉积工艺来形成在PCB 52的表面上或PCB 52的层内。信号迹线54提供了在半导体封装、安装的部件以及其他外部系统部件中的每个之间的电气通信。迹线54还提供了至每个半导体封装的功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级别的封装是用于机械地和电气地将半导体管芯附着到中间载体的技术。第二级别的封装涉及机械地和电气地将中间载体附着到PCB。在其他实施例中，半导体器件可以仅具有第一级别的封装，其中管芯机械地和电气地直接安装到PCB。
出于说明的目的，在PCB 52上示出了若干类型的第一级别的封装，包括接合线封装56和倒装芯片58。另外，示出在PCB 52上安装的若干类型的第二级别的封装，包括球栅阵列（BGA）60、隆起芯片载体（BCC）62、双列直插式封装（DIP）64、连接盘网格阵列（LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（QFN）70以及四侧扁平封装72。取决于系统要求，配置有第一和第二级别的封装样式的任何组合的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为半导体封装包括复杂的功能性，所以可以使用较不昂贵的部件和流水线化的制造工艺来制造电子器件。产生的器件对于制造而言较不可能失败并且较不昂贵，从而导致针对消费者的较低成本。
图2a-2c示出示例性的半导体封装。图2a图示安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区，该有源区包含根据管芯的电气设计实现为形成在管芯内的且电气互连的有源器件、无源器件、导电层和介电层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及形成在半导体管芯74的有源区内的其他电路元件。接触垫76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的导电材料的一个或多个层，并且电气连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，半导体管芯74使用金硅共晶层或诸如热环氧树脂或环氧树脂的粘合材料安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和接合线82在半导体管芯74与PCB 52之间提供电气互连。密封剂84沉积在封装上，以通过防止湿气和粒子进入封装和污染半导体管芯74或接合线82来进行环境保护。
图2b图示了安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底部填充或环氧树脂粘合材料92安装在载体90上。接合线94在接触垫96和98之间提供第一级别的封装互连。成型化合物或密封剂100沉积在半导体管芯88和接合线94上以提供对器件的物理支持和电气隔离。使用诸如电镀或无电镀的合适金属沉积工艺来在PCB 52的表面上形成接触垫102以防止氧化。接触垫102电气连接到PCB 52中的一个或多个导电信号迹线54。凸起104形成在BCC 62的接触垫98与PCB 52的接触垫102之间。
在图2c中，以倒装芯片样式的第一级别的封装向下面向中间载体106安装半导体管芯58。半导体管芯58的有源区108包含实现为根据管芯的电气设计形成的有源器件、无源器件、导电层以及介电层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及在有源区108内的其他电路元件。半导体管芯58通过凸起110电气地和机械地连接到载体106。
BGA 60使用凸起112以BGA样式的第二级别的封装电气地和机械地连接到PCB 52。半导体管芯58通过凸起110、信号线114和凸起112电气地连接到PCB 52中的导电信号迹线54。成型化合物或密封剂116沉积在半导体管芯58和载体106上以提供对器件的物理支持和电气隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短电气导电路径，以减小信号传播距离、降低电容以及改进整体电路性能。在另一实施例中，半导体管芯58可以在没有中间载体106的情况下使用倒装芯片样式的第一级别封装机械地和电气地直接连接到PCB 52。
图3a示出了具有用于结构支持的基衬底材料122的半导体晶圆120，基衬底材料122诸如硅、锗、砷化镓、磷化铟或碳化硅。通过非有源、管芯间晶圆区域或如上文所描述的划片街区126来分离的多个半导体管芯或部件124形成在晶圆120上。划片街区126提供切割区域来将半导体晶圆120单体化成个体半导体管芯124。在一个实施例中，半导体晶圆120具有200-300毫米（mm）的宽度或直径。在另一实施例中，半导体晶圆120具有100-450mm的宽度或直径。
图3b示出了半导体晶圆120的一部分的横截面视图。每个半导体管芯124具有后或非有源表面128和有源表面130，有源表面130包含根据管芯的电气设计和功能实现为形成在管芯内且电气互连的有源器件、无源器件、导电层以及介电层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管以及形成在有源表面130内的其他电路元件，以实现模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、存储器或其他信号处理电路。半导体管芯124还可以包含用于RF信号处理的集成的无源器件（IPD），诸如电感器、电容器以及电阻器。在一个实施例中，半导体管芯124是倒装类型的半导体管芯。
使用PVD、CVD、电镀、无电镀工艺或其他合适的金属沉积工艺将电气导电层132形成在有源表面130上。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的电气导电材料的一个或多个层。导电层132操作为电气连接到有源表面130上的电路的接触垫。导电层132可以形成为并排放置在与半导体管芯124的边缘相距第一距离的接触垫，如图3b中所示。可替代地，导电层132可以形成为在多个行中偏离的接触垫，使得第一行接触垫放置为与管芯的边缘相距第一距离，并且与第一行交替的第二行接触垫放置为与管芯的边缘相距第二距离。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在有源表面130上形成绝缘或钝化层134。绝缘层134包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、氧化钽（Ta2O5）、氧化铝（Al2O3）或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层134覆盖并提供对有源表面130的保护。绝缘层134的一部分通过蚀刻、激光直接烧蚀（LDA）或其他合适工艺被移除以曝露导电层132进行后续电气互连。
半导体晶圆120经受作为质量控制过程的部分的电气测试和检查。手动视觉检查和自动光学系统用于执行对半导体晶圆120的检查。软件可以用在对半导体晶圆120的自动光学分析中。视觉检查方法可以采用诸如以下的装备：扫描电子显微镜、高强度或紫外线光或金相显微镜。针对结构特性检查半导体晶圆120，结构特性包括翘曲、厚度变化、表面颗粒、不规则性、裂缝、分层以及变色。
半导体管芯124内的有源和无源部件经受晶圆级的针对电气性能和电路功能的测试。如图3c中所示，使用探针138或其他测试器件针对功能性和电气参数对每个半导体管芯124进行测试。测试探针头138包括多个探针136。探针136用于与每个半导体管芯124上的节点或接触垫132进行电气接触，并且对接触垫提供电气刺激。半导体管芯124对电气刺激做出响应，该响应被计算机测试系统140测量并与预期响应进行比较以测试半导体管芯的功能性。电气测试可以包括电路功能性、引线完整性、电阻率、连续性、可靠性、结深度、静电放电（ESD）、RF性能、驱动电流、阈值电流、泄漏电流以及特定于部件类型的操作参数。对半导体晶圆120的检查和电气测试使得通过测试的半导体管芯能够被指定为已知良好管芯（KGD）以在半导体封装中使用。
在图3d中，使用PVD、CVD、电镀、无电镀工艺或其他合适的金属沉积工艺将电气导电层或RDL 150形成在导电层132和绝缘层134上。导电层150可以是Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其他合适的电气导电材料的一个或多个层。导电层150的一个部分电气连接到导电层132。导电层150的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124的设计和功能。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化将绝缘或钝化层152形成在绝缘层134和导电层150上。绝缘层152包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层152的一部分通过LDA、蚀刻或其他合适工艺被移除以曝露导电层150。
在图3e中，使用印刷、旋涂或喷涂将图案化或光致抗蚀剂层154形成在绝缘层152和导电层150上。光致蚀刻剂层154的一部分使用激光器156通过LDA被移除以形成图案化的开口158并且曝露绝缘层152和导电层150。可替代地，光致蚀刻剂层154的部分通过蚀刻工艺穿过图案化的光致蚀刻剂层被移除以形成图案化的开口158并且曝露绝缘层152和导电层150。在一个实施例中，图案化的开口158具有圆形横截面积，其被配置为形成具有包括圆形横截面的圆柱形状的导电柱。在另一实施例中，图案化的开口158具有矩形横截面积，其被配置为形成具有包括矩形横截面的立方体形状的导电柱。
在图3f中，使用诸如印刷、PVD、CVD、溅射、电镀和无电镀的图案化和金属沉积工艺在绝缘层152和导电层150上在开口158内共形地施加电气导电层160。可替代地，可以在形成光致蚀刻剂层154之前在绝缘层152和导电层150上形成导电层160。导电层160可以是Al、Cu、Sn、Ti、Ni、Au、Ag或其他合适电气导电材料的一个或多个层。在一个实施例中，导电层160是多层堆叠，包括籽晶层、阻挡层和粘合层。籽晶层可以是钛铜（TiCu）、钛钨铜（TiWCu）或钽氮铜（TaNCu）。阻挡层可以是Ni、镍钒（NiV）、铂（Pt）、钯（Pd）、TiW、CrCu或其他合适材料。粘合层可以是Ti、TiN、TiW、Al或铬（Cr）或其他合适材料。导电层160遵从绝缘层152和导电层150的轮廓。导电层160电气连接到导电层150。
在图3g中，使用蒸发、溅射、电镀、无电镀或丝网印刷工艺将电气导电材料162沉积在开口158内和导电层160上。导电材料162可以是Cu、Al、钨（W）、Au、焊料或其他合适的电气导电材料。在一个实施例中，通过镀Cu将导电材料162沉积在光致蚀刻剂层154的图案化的开口158中。
在图3h中，光致蚀刻剂层154通过蚀刻工艺被移除以留下个体导电柱164。导电柱164可以具有带有圆形或椭圆形横截面的圆柱形状，或者导电柱164可以具有带有矩形横截面的立方体形状。在另一实施例中，导电柱164可以利用堆叠凸起或柱形凸起来实现。
在图3i中，使用蒸发、电镀、无电镀、落球（ball drop）或丝网印刷工艺将电气导电凸起材料沉积在导电柱164上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料可以回流以形成圆凸起帽166。在一些应用中，凸起帽166第二次回流以改进至柱164的电气接触。可替代地，在移除光致蚀刻剂层154之前沉积电气导电凸起材料。导电柱164和凸起帽166的组合构成具有不熔部分（导电柱164）和可熔部分（凸起帽166）的合成互连结构168。合成互连结构168代表可以形成在半导体管芯124上的一种类型的互连结构。互连结构还可以使用接合线、凸起、导电胶、柱形凸起、微凸起或其他电气互连。
半导体晶圆120使用锯条或激光切割工具170通过划片街区126被单体化成个体半导体管芯124。可以针对KGD后单体化的标识对个体半导体管芯124进行检查和电气测试。
图4a-4s图示了与图1和2a-2c相关的用于形成包括细节距的RDL和堆积互连结构的半导体器件的过程。图4a示出了载体或临时衬底180的一部分的横截面视图，载体或临时衬底180包含牺牲基材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支持的其他合适的低成本刚性材料。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层182形成在衬底180上。绝缘层182包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层182被选择为具有良好的选择性以作为硅蚀刻剂，并且可以在之后移除衬底180期间充当蚀刻终止。
使用PVD、CVD、电镀、无电镀工艺或其他合适的金属沉积工艺将电气导电层或RDL184形成在绝缘层182上。导电层184可以是Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其他电气导电材料的一个或多个层。导电层184的部分可以是电气公共的或电气隔离的，这取决于之后安装的半导体管芯的设计和功能。导电层184包括多个导电迹线。导电层184的导电迹线利用细或窄节距形成。例如，在一个实施例中，导电层184的导电迹线具有2µm的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层186形成在绝缘层182和导电层184上。绝缘层186包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层186的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层184。
在图4b中，使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 188共形地沉积在绝缘层186和导电层184上。导电层188可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适电气导电材料的一个或多个层。导电层188的一个部分电气连接到导电层184。导电层188的其他部分可以是电气公共的或者是电气隔离的，这取决于之后安装的半导体管芯的设计和功能。导电层188包括多个导电迹线。导电层188的导电迹线利用细或窄节距形成。在一个实施例中，导电层188的导电迹线利用2µm的节距来形成。
在图4c中，使用PVD、CVD、印刷、旋涂、喷涂、层压、烧结或热氧化将绝缘或钝化层190形成在绝缘层186和导电层188上。绝缘层190包括Si3N4、SiO2、SiON、PI、BCB、PBO、WPR、环氧树脂、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层190是焊阻层。绝缘层190的一部分通过蚀刻、LDA或其他合适的工艺被移除以曝露导电层188。
在图4d中，使用蒸发、电镀、无电镀、落球或丝网印刷工艺将电气导电凸起材料沉积在导电层188上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层188。在一个实施例中，凸起材料通过将材料加热到材料的熔点以上而被回流以形成凸起192。在一些应用中，凸起192第二次回流以改进至导电层188的电气接触。在一个实施例中，凸起192形成在UBM层上。凸起192还可以压缩接合或热压缩接合到导电层188。凸起192代表可以形成在导电层188上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。
绝缘层182、导电层184、绝缘层186、导电层188、绝缘层190和凸起192构成晶圆级重分布层（WL RDL）或堆积互连结构194。WL RDL 194可以包括IPD，诸如电容器、电感器或电阻器。在WL RDL 194内的导电迹线利用细节距形成，例如2µm的节距，并且可伸缩到亚微米尺寸，即在纳米范围中。WL RDL 194中的导电迹线的窄节距允许较高密度（即，较大数量）的导电迹线形成在WL RDL 194内。增加数量的导电迹线增加了互连站点的数量以及WL RDL194的输入/输出（I/O）端子计数。要求增加的I/O的半导体管芯可以安装到WL RDL 194。另外，不同的I/O要求的半导体管芯和/或来自多个制造的管芯可以放置在WL RDL 194上。
在图4e中，来自图3i的半导体管芯124放置在WL RDL 194上。半导体管芯124的互连结构168与凸起192对齐。使用拾取和放置或其他合适的操作将半导体管芯124安装到WLRDL 194。半导体管芯124是在将半导体管芯124安装到WL RDL 194之前已经被测试的KGD。
图4f示出了安装到WL RDL 194以形成重建的晶圆196的半导体管芯124。凸起帽166回流以金相地和电气地将半导体管芯124连接到WL RDL 194。在一些应用中，凸起帽166第二次回流以改进至凸起192的电气接触。互连结构168还可以压缩接合或热压缩接合到凸起192。WL RDL 194根据半导体管芯124的设计和功能在半导体管芯124之间路由电气信号。
在图4g中，使用浆印刷（paste printing）、压缩成型、传递成型、液体密封剂成型、真空层压或其他合适的敷贴器将密封剂或成型化合物198沉积在半导体管芯124和WL RDL194上。密封剂198可以是聚合物合成材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有合适填充物的聚合物。密封剂198是非导电的，提供物理支持，并且在环境上保护半导体器件免受外部元素和污染影响。密封剂198还保护半导体管芯124免于由于曝露于光而导致的退化。在一个实施例中，密封剂198的部分在后续的背面研磨步骤中从密封剂198的表面200被移除。背面研磨操作使密封剂198的表面平面化，并且减小重建的晶圆196的整体厚度。
如图4g中所示，密封剂198在半导体管芯124和WL RDL 194之间并且围绕互连结构168流动。在一个实施例中，诸如环氧树脂的底部填充材料202沉积在半导体管芯124与WLRDL 194之间，如图4h中所示。底部填充材料202可以通过毛细管底部填充工艺来沉积。可替代地，非导电胶或非导电膜可以在附着半导体管芯124之前应用于WL RDL 194。
从图4g继续，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体180。移除载体180留下附着到半导体管芯124的WL RDL 194并曝露绝缘层182，如图4i中所示出的。
在图4j中，使用激光器206通过LDA移除绝缘层182的一部分以曝露导电层184。可替代地，通过曝光和显影工艺、通过蚀刻或其他合适的工艺来移除绝缘层182的一部分以曝露导电层184。
在一个实施例中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体180的一部分，并且使载体180的薄层保留在绝缘层182上，如图4k中所示。然后，使用激光器206通过LDA移除载体180的保留薄层的一部分和绝缘层182的一部分以曝露导电层184。
从图4j继续，划片胶带（dicing tape）或支持载体208应用在绝缘层182上，如图4l中所示。然后，使用锯条或激光切割工具210通过密封剂198和WL RDL 194将重建的晶圆196单体化成个体晶圆级芯片规模的封装（WLCSP）220，包括半导体管芯124和细节距的WL RDL194。划片胶带208在单体化期间支持重建的晶圆196。
在图4m中，来自图4l的WLCSP 220放置在载体或临时衬底230上，载体或临时衬底230包含牺牲基材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支持的其他合适的低成本刚性材料。界面层或双面胶带232在载体230上形成为临时粘合接合膜、蚀刻终止层或热释放层。
载体230可以是圆或矩形面板（大于300mm），具有用于多个WLCSP 220的容量。载体230可以具有比半导体晶圆120和/或重建的晶圆196的表面积更大的表面积。较大的载体减小了半导体封装的制造成本，因为可以在较大的载体上处理更多半导体管芯/封装，从而减小了每单位成本。针对正被处理的晶圆或载体的大小来设计和配置半导体封装和处理装备。
为了进一步减小制造成本，独立于半导体管芯124和WLCSP 220的大小或晶圆120和重建的晶圆196的大小来选择载体230的大小。即，载体230具有固定或标准化的大小，其可以容纳分别从一个或多个晶圆120和重建的晶圆196单体化的各种大小的半导体管芯124和WLCSP 220。在一个实施例中，载体230是具有330mm的直径的圆。在另一实施例中，载体230是具有560mm宽和600mm长的矩形。WLCSP 220放置在标准化的载体230上，其中WLCSP包括具有例如10mm乘以10mm的尺寸的半导体管芯124。可替代地，WLCSP 220放置在相同的标准化的载体230上，其中WLCSP 220包括具有例如20mm乘以20mm的尺寸的半导体管芯124。因此，标准化的载体230可以处理任何大小的半导体管芯或WLCSP，这允许后续半导体处理装备被标准化为公共载体，即，独立于管芯或封装大小或进入的晶圆大小。半导体封装装备可以被设计和配置用于标准载体，其使用公共的一组处理工具、装备和材料清单来处理来自任何进入的晶圆大小的任何半导体管芯大小。公共或标准化的载体230通过减小或消除对于基于管芯或封装大小或进入的晶圆大小的专用半导体处理线的需要，降低了制造成本和资本风险。通过选择预定载体大小来用于来自所有半导体晶圆的任何大小的半导体管芯或封装，可以实现灵活的制造线。
图4n示出了安装到载体230以形成重建的晶圆234的WLCSP 220。使用浆印刷、压缩成型、传递成型、液体密封剂成型、真空层压或其他合适的敷贴器将密封剂或成型化合物236沉积在WLCSP 220和载体230上。密封剂236可以是聚合物合成材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有合适填充物的聚合物。密封剂236是非导电的，提供物理支持，并且在环境上保护半导体器件免受外部元素和污染影响。密封剂236还保护半导体管芯124免于由于曝露于光而导致的退化。在一个实施例中，密封剂236的部分在后续的背面研磨步骤中从密封剂236的表面238被移除。背面研磨操作使密封剂236的表面平面化，并且减小半导体器件的整体厚度。密封剂236的与后侧表面238相对的表面239放置在载体230和界面层232上，使得密封剂236的表面239与WLCSP 220的绝缘层182共面。
在图4o中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体230和界面层232，以曝露WLCSP 220的绝缘层182和密封剂236的表面239。
在图4p中，重建的晶圆234被倒置，并且使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层240形成在绝缘层182和密封剂236的表面239上。绝缘层240包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层240的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层184。在一个实施例中，绝缘层182的部分和绝缘层240的部分被同时移除，即，在单个制造步骤中被移除，以曝露导电层184。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 242形成在绝缘层240和导电层184上。导电层242可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适的电气导电材料的一个或多个层。导电层242的一个部分电气连接到导电层184。导电层242的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124的设计和功能。导电层242包括多个导电迹线。导电层242的导电迹线利用比WL RDL 194内的导电迹线宽的节距来形成。在一个实施例中，导电层242的导电迹线具有15µm或更大的节距。
在图4q中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层244形成在绝缘层240和导电层242上。绝缘层244包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层244的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层242。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 242形成在绝缘层244和导电层242上。导电层246可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适的电气导电材料的一个或多个层。导电层246的一个部分电气连接到导电层242。导电层246的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124的设计和功能。导电层246包括多个导电迹线。导电层246的导电迹线利用比WL RDL 194中的导电层184和188的导电迹线宽的节距来形成。在一个实施例中，导电层242的导电迹线具有15µm或更大的节距。
在图4r中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层248形成在绝缘层244和导电层246上。绝缘层248包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层248是焊阻。绝缘层248的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层246。
绝缘层240、导电层242、绝缘层244、导电层246以及绝缘层248的组合构成在WLCSP220和密封剂236上形成的堆积互连结构250。在堆积互连结构250内包括的绝缘层和导电层的数量取决于电路路由设计的复杂度并且随之变化。因此，堆积互连结构250可以包括任何数量的绝缘层和导电层以促进针对半导体管芯124的电气互连。堆积互连结构250内的导电迹线的放松设计规则和较大节距允许在堆积互连结构250的建造中使用的材料和制造技术的较大灵活性，并且减小制造成本。
在图4s中，使用蒸发、电镀、无电镀、落球或丝网印刷工艺将电气导电凸起材料沉积在导电层246上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层246。在一个实施例中，凸起材料通过将材料加热到材料的熔点以上而被回流以形成球或凸起252。在一些应用中，凸起252第二次回流以改进至导电层246的电气接触。在一个实施例中，凸起252形成在UBM层上。凸起252还可以压缩接合或热压缩接合到导电层246。凸起252代表可以形成在导电层246上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。可以在凸起形成之前或之后执行对重建的晶圆234的用于对齐、单体化和/或封装标识的激光标记。
图4s还示出使用锯条或激光切割工具254通过堆积互连结构250和密封剂236将重建234单体化成个体半导体器件260，包括半导体管芯124、WL RDL 194和堆积互连结构250。
图5示出单体化后的半导体器件260。半导体管芯124通过WL RDL 194和堆积互连结构250电气连接到凸起252以连接到诸如PCB的外部器件。WL RDL 194在半导体管芯124之间以及在半导体管芯124与堆积互连结构250之间路由电气信号。堆积互连结构250在WLCSP220与外部器件之间路由电气信号。形成两种分离的堆积互连结构（即WL RDL 194和堆积互连结构250）允许WL RDL 194利用窄节距 RDL建造技术以增加半导体器件260的I/O和电气性能，而堆积互连结构250利用标准Fo-eWLB建造技术最小化成本并提供至外部部件的附加路由。在附着半导体管芯124之前以超窄节距在临时衬底180上形成WL RDL 194的导电层184和188，从而提供了形成RDL的成本有效的方式，其可伸缩到亚微米尺寸，即在纳米范围中。导电层184和188内的导电迹线的窄节距允许WL RDL 194内的互连的较高密度。互连的高密度在半导体器件的集成方面提供了更多灵活性，并且容纳具有变化的凸起节距的半导体管芯，例如，来自多个制造源的半导体管芯。另外，导电迹线的窄节距减小了WL RDL 194的大小，并且缩短了半导体管芯124与凸起252之间的互连距离，即电气信号必须行进的距离。较短的互连距离增加了半导体器件260的速度和电气性能。
与用于形成TSV中介层封装的工艺相比，使用更快、更不昂贵并且更低风险的工艺来形成半导体器件260内的WL RDL 194和堆积互连结构250。另外，在不必并入TSV中介层的情况下提供电气互连减小了半导体器件260的尺寸和封装轮廓。在堆积互连结构250之前并且独立于堆积互连结构250形成WLCSP 220允许在将WLCSP 220安装到衬底230之前测试在半导体管芯124之间的信号路由和WLCSP 220的功能性。因此，仅已知良好的WLCSP 220被并入半导体器件260。使用仅已知良好的WLCSP 220建造半导体器件260，防止制造时间和材料被浪费于制作有缺陷封装，并因此，半导体器件260的产量增加并且整体成本减小。
堆积互连结构250在半导体器件260内提供了附加导电层。该附加导电层可以用于连接到其他内部或外部器件。堆积互连结构250的导电层242和246利用放松的设计规则使用标准Fo-eWLB工艺来形成。放松堆积互连结构250的设计规则允许在堆积互连结构250的建造中使用的材料和制造技术的较大灵活性。例如，与特定于建造具有超窄节距的导电层的材料相对的，可以使用标准Fo-eWLB装备和材料来形成堆积互连结构250。标准化的装备和材料的使用减小了半导体器件260的制造时间和成本。堆积互连结构250内的导电迹线的较宽节距也提供了在凸起252的放置和节距方面的较大灵活性。可以选择凸起252的节距以反映工业标准。例如，可以利用与标准PCB上的互连垫相同的节距来形成凸起252。在一个实施例中，凸起252具有0.4mm的节距。放松凸起252的设计规则增加了半导体器件260与外部器件的兼容性，并且消除了对额外衬底或中介层的需要。
在牺牲衬底180上形成细节距的WL RDL 194、通过芯片到晶圆成型将WL RDL 194转移到半导体管芯124，以及使用标准Fo-eWLB建造工艺在WLCSP 220上形成堆积互连结构250，以上允许半导体器件260并入具有高和/或不同I/O要求的半导体管芯，同时最小化半导体器件260的大小、制造时间以及成本。
图6a-6i图示了与图1和2a-2c相关的用于形成包括细节距的RDL和嵌入的无源器件的半导体器件的过程。图6a示出了在载体或者临时衬底370上形成的与图4d中的WL RDL194类似的WL RDL或堆积互连结构384。衬底370包含牺牲基材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支持的其他合适的低成本刚性材料。WL RDL 384包括绝缘层372、导电层374、绝缘层376、导电层378、绝缘层380和凸起382。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层372形成在衬底370上。绝缘层372包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层372被选择为具有良好的选择性以作为硅蚀刻剂，并且可以在之后移除衬底370期间充当蚀刻终止。
使用PVD、CVD、电镀、无电镀工艺或其他合适的金属沉积工艺将电气导电层或RDL374形成在绝缘层372上。导电层374可以是Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其他电气导电材料的一个或多个层。导电层374的部分可以是电气公共的或电气隔离的，这取决于之后安装的半导体管芯的设计和功能。导电层374包括多个导电迹线。导电层374的导电迹线利用细节距形成。例如，在一个实施例中，导电层374的导电迹线具有2µm的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层376形成在绝缘层372和导电层374上。绝缘层376包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层376的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层374。
使用PVD、CVD、电镀或无电镀工艺将电气导电层378共形地沉积在绝缘层376和导电层374上。导电层378可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适电气导电材料的一个或多个层。导电层378的一个部分电气连接到导电层374。导电层378的其他部分可以是电气公共的或者是电气隔离的，这取决于之后安装的半导体管芯的设计和功能。导电层378包括多个导电迹线。导电层378的导电迹线利用细节距形成。例如，在一个实施例中，导电层378的导电迹线利用2µm的节距形成。
使用PVD、CVD、印刷、旋涂、喷涂、层压、烧结或热氧化将绝缘或钝化层380形成在绝缘层376和导电层378上。绝缘层380包括Si3N4、SiO2、SiON、PI、BCB、PBO、WPR、环氧树脂、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层380是焊阻层。绝缘层380的一部分通过蚀刻、LDA或其他合适的工艺被移除以曝露导电层378。
使用蒸发、电镀、无电镀、落球或丝网印刷工艺将电气导电凸起材料沉积在导电层378上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层378。在一个实施例中，凸起材料通过将材料加热到材料的熔点以上而被回流以形成凸起382。在一些应用中，凸起382第二次回流以改进至导电层378的电气接触。在一个实施例中，凸起382形成在UBM层上。凸起382还可以压缩接合或热压缩接合到导电层378。凸起382代表可以形成在导电层378上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。
绝缘层372、导电层374、绝缘层376、导电层378、绝缘层380和凸起382构成WL RDL或堆积互连结构384。在WL RDL 384内的导电迹线利用细节距形成，例如2µm的节距，并且可伸缩到亚微米尺寸，即在纳米范围中。WL RDL 384中的导电迹线的窄节距允许较高密度（即，较大数量）的导电迹线形成在WL RDL 384内。增加数量的导电迹线增加了互连站点的数量以及WL RDL 384的I/O端子计数。WL RDL 384容纳要求增加的I/O计数的半导体管芯。另外，不同的I/O要求的半导体管芯和/或来自多个制造的管芯可以放置在WL RDL 384上。
图6a还示出了类似于来自图3i的半导体管芯124的放置在WL RDL 384上的半导体管芯390，以及在半导体管芯390的外围区中的放置在WL RDL 384上的半导体部件或无源器件412。使用例如拾取和放置操作将半导体管芯390和无源器件412放置在WL RDL上。半导体管芯390具有后或非有源表面392和与表面392相对的类似于半导体管芯124的有源表面130的有源表面394。在有源表面394上形成与导电层132类似的电气导电层396。在有源表面394和导电层396上形成与绝缘层134类似的绝缘或钝化层398。绝缘层398的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层396的部分。在绝缘层398上形成与半导体管芯124的导电层150类似的电气导电层或RDL 400。导电层400电气连接到导电层396。在导电层400和绝缘层398上形成与绝缘层152类似的绝缘或钝化层402。绝缘层402的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层400的部分。在导电层400和绝缘层402上形成与导电层160类似的导电层403。在导电层403上形成与半导体管芯124的互连结构168类似的多个互连结构408。互连结构408包括不熔部分（导电柱404）和可熔部分（凸起帽406）。互连结构408代表可以形成在半导体管芯390上的一种类型的互连结构。互连结构还可以使用接合线、凸起、导电胶、柱形凸起、微凸起或其他电气互连。
图6b示出了安装到WL RDL 384以形成重建的晶圆414的半导体管芯390和无源器件412。凸起帽406回流以金相地和电气地将半导体管芯390连接到WL RDL 384。在一些应用中，凸起帽166第二次回流以改进至凸起382的电气接触。半导体管芯390和无源器件412的每个电气连接WL RDL 384。在一个实施例中，在半导体管芯390与WL RDL 384之间放置与图4h中的底部填充材料202类似的底部填充材料。
使用浆印刷、压缩成型、传递成型、液体密封剂成型、真空层压或其他合适的敷贴器将密封剂或成型化合物416沉积在半导体管芯390、无源器件412和WL RDL 384上。密封剂416可以是聚合物合成材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有合适填充物的聚合物。密封剂416是非导电的，提供物理支持，并且在环境上保护半导体器件免受外部元素和污染影响。密封剂416还保护半导体管芯390免于由于曝露于光而导致的退化。在一个实施例中，密封剂416的部分在后续的背面研磨步骤中从密封剂416的表面418被移除。背面研磨操作使密封剂416的表面平面化，并且减小重建的晶圆414的整体厚度。
在图6c中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除衬底370，并且使用激光器420通过LDA移除绝缘层372的一部分以曝露导电层374。可替代地，通过曝光和显影工艺、蚀刻或其他合适的工艺来移除绝缘层372的部分以曝露导电层374。在一个实施例中，在绝缘层372上留下与图4k中的衬底180类似的衬底370的薄层。
在图6d中，划片胶带或支持载体422应用在绝缘层372上。然后，使用锯条或激光切割工具424通过密封剂416和WL RDL 384将重建的晶圆414单体化成个体WLCSP 430，包括半导体管芯124、无源器件412和细节距的WL RDL 384。划片胶带422在单体化期间支持重建的晶圆414。
在图6e中，来自图6d的WLCSP 430放置在载体或临时衬底432上，载体或临时衬底432包含牺牲基材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支持的其他合适的低成本刚性材料。界面层或双面胶带434在载体432上形成为临时粘合接合膜、蚀刻终止层或热释放层。
在载体432和界面层434上相邻于WLCSP 430放置半导体部件或无源器件436。在一个实施例中，WLCSP 430的无源器件412是较小的无源器件，例如01005（度量代码0402）或0201（度量代码0603）大小的无源部件，并且无源器件436是较大的无源器件，例如0402（度量代码1005）或0603（度量代码1608）大小的无源部件。
图6f示出了安装到载体432以形成重建的晶圆438的WLCSP 430和无源器件436。使用浆印刷、压缩成型、传递成型、液体密封剂成型、真空层压或其他合适的敷贴器将密封剂或成型化合物440沉积在WLCSP 430、无源器件436和载体432上。密封剂440可以是聚合物合成材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有合适填充物的聚合物。密封剂440是非导电的，提供物理支持，并且在环境上保护半导体器件免受外部元素和污染影响。密封剂440还保护半导体管芯390免于由于曝露于光而导致的退化。在一个实施例中，密封剂440的部分在后续的背面研磨步骤中从密封剂440的表面442被移除。背面研磨操作使密封剂440的表面平面化，并且减小半导体器件的整体厚度。密封剂440的与后侧表面442相对的表面444放置在载体432和界面层434上，使得密封剂440的表面444与WLCSP 430的绝缘层372共面。
在图6g中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体432和界面层434。移除载体432和界面层434曝露密封剂440的表面444、WLCSP 430的绝缘层372和无源器件436。
在图6h中，堆积互连结构456形成在密封剂440的表面444、WLCSP 430和无源器件436上。堆积互连结构456包括绝缘层446、导电层448、绝缘层450、导电层452和绝缘层454。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层446形成在密封剂440的表面444、绝缘层372和无源器件436上。绝缘层446包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层446的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层374和无源器件436。在一个实施例中，绝缘层372的部分和绝缘层446的部分被同时移除，即，在单个制造步骤中被移除，以曝露导电层374和无源器件436。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 448形成在绝缘层446上。导电层448可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适的电气导电材料的一个或多个层。导电层448的一个部分电气连接到导电层374。导电层448的一个部分电气连接到无源器件436。导电层448的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯390的设计和功能。导电层448包括多个导电迹线。导电层448的导电迹线利用放松的设计规则和比WL RDL 384内的导电迹线宽的节距来形成。在一个实施例中，导电层448的导电迹线具有15µm或更大的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层450形成在绝缘层446和导电层448上。绝缘层450包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层450的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层448。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 452形成在绝缘层450和导电层448上。导电层452可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适的电气导电材料的一个或多个层。导电层452的一个部分电气连接到导电层448。导电层452的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯390的设计和功能。导电层452包括多个导电迹线。导电层452的导电迹线利用比WL RDL 384中的导电层374和378的导电迹线宽的节距来形成。在一个实施例中，导电层452的导电迹线具有15µm或更大的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层454形成在绝缘层450和导电层452上。绝缘层454包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层454是焊阻。绝缘层454的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层452。
绝缘层446、导电层448、绝缘层450、导电层452以及绝缘层454的组合构成在WLCSP430、无源器件436和密封剂440上形成的堆积互连结构456。在堆积互连结构456内包括的绝缘层和导电层的数量取决于电路路由设计的复杂度并且随之变化。因此，堆积互连结构456可以包括任何数量的绝缘层和导电层以促进针对半导体管芯390的电气互连。堆积互连结构456内的导电迹线的放松设计规则和较大节距允许在堆积互连结构456的建造中使用的材料和制造技术的较大灵活性，并且减小制造成本。
在图6i中，使用蒸发、电镀、无电镀、落球或丝网印刷工艺将电气导电凸起材料沉积在导电层452上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层452。在一个实施例中，凸起材料通过将材料加热到材料的熔点以上而被回流以形成球或凸起458。在一些应用中，凸起458第二次回流以改进至导电层452的电气接触。在一个实施例中，凸起458形成在UBM层上。凸起458还可以压缩接合或热压缩接合到导电层452。凸起458代表可以形成在导电层452上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。可以在凸起形成之前或之后执行对重建的晶圆438的用于对齐、单体化和/或封装标识的激光标记。
图6i还示出使用锯条或激光切割工具460通过堆积互连结构456和密封剂440将重建的晶圆438单体化成个体半导体器件470，包括WLCSP 430、无源器件436和堆积互连结构456。
图7示出单体化后的半导体器件470。半导体管芯390通过WL RDL 384和堆积互连结构456电气连接到凸起458以连接到外部器件。WL RDL 384在半导体管芯390之间以及在半导体管芯390与无源器件412之间路由电气信号。堆积互连结构456在WLCSP 430、无源器件412与例如PCB的外部器件之间路由电气信号。形成两种分离的堆积互连结构（即WL RDL384和堆积互连结构456）允许WL RDL 384利用窄节距 RDL建造技术以增加半导体器件470的I/O和电气性能，而堆积互连结构456利用标准Fo-eWLB建造技术最小化成本并提供至外部部件的附加路由。在附着半导体管芯390之前以超窄节距在临时衬底370上形成WL RDL384的导电层374和378，从而提供了形成RDL的成本有效的方式，其可伸缩到亚微米尺寸，即在纳米范围中。导电层374和378内的导电迹线的窄节距允许WL RDL 384内的互连的较高密度。互连的高密度在半导体器件的集成方面提供了更多灵活性，并且容纳具有变化的凸起节距的半导体管芯，例如，来自多个制造源的半导体管芯。另外，导电迹线的窄节距减小了WL RDL 384的大小，并且缩短了半导体管芯390与凸起458之间的互连距离，即电气信号必须行进的距离。较短的互连距离增加了半导体器件470的速度和电气性能。
与用于形成TSV中介层封装的工艺相比，使用更快、更不昂贵并且更低风险的工艺来形成半导体器件470内的WL RDL 384和堆积互连结构456。另外，在不必并入TSV中介层的情况下提供电气互连减小了半导体器件470的尺寸和封装轮廓。在堆积互连结构456之前并且独立于堆积互连结构456形成WLCSP 430允许在将WLCSP 430安装到载体432之前测试在半导体管芯390之间的信号路由和WLCSP 430的功能性。因此，仅已知良好的WLCSP 430被并入半导体器件470。使用仅已知良好的WLCSP 430建造半导体器件470，防止制造时间和材料被浪费于制作有缺陷封装，并因此，半导体器件470的产量增加并且整体成本减小。
堆积互连结构456在半导体器件470内提供了附加导电层，该附加导电层可以用于连接到例如无源器件436的其他内部或外部器件。在半导体器件470内嵌入无源器件436和412增加了半导体器件470的功能性和电气性能，而不会增加封装轮廓。堆积互连结构456的导电层448和452利用放松的设计规则使用标准Fo-eWLB工艺来形成。放松堆积互连结构456的设计规则允许在堆积互连结构456的建造中使用的材料和制造技术的较大灵活性。例如，与特定于建造具有超窄节距的导电层的材料相对的，可以使用标准Fo-eWLB装备和材料来形成堆积互连结构456。标准化的装备和材料的使用减小了半导体器件470的制造时间和成本。堆积互连结构456内的导电迹线的较宽节距也提供了在凸起458的放置和节距方面的较大灵活性。可以选择凸起458的节距以反映工业标准。例如，可以利用与标准PCB上的互连垫相同的节距来形成凸起458。在一个实施例中，凸起458具有0.4mm的节距。放松凸起458的设计规则增加了半导体器件470与外部器件的兼容性，并且消除了对额外衬底或中介层的需要。
在牺牲衬底370上形成细节距的WL RDL 384、通过芯片到晶圆成型将WL RDL 384转移到半导体管芯390，以及使用标准Fo-eWLB建造工艺在WLCSP 430上形成堆积互连结构456，以上允许半导体器件470并入具有高和/或不同I/O要求的半导体管芯，同时最小化半导体器件470的大小、制造时间以及成本。
图8a-8i图示了与图1和2a-2c相关的用于形成包括细节距的RDL和嵌入的垂直互连单元的半导体器件的过程。图8a示出了载体或临时衬底480的一部分的横截面视图，载体或临时衬底480包含牺牲基材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支持的其他合适的低成本刚性材料。界面层或双面胶带482在载体480上形成为临时粘合接合膜、蚀刻终止层或热释放层。
在图8b中，来自图4l的WLCSP 220放置在载体480和界面层482上，其中绝缘层182定向为朝向载体480。在图8c中，多个PCB模块化的垂直互连单元484放置在载体480和界面层482上。垂直互连单元484放置在WLCSP 220的周围或外围区中。垂直互连单元484可以以互锁模式放置在WLCSP 220周围，使得每个WLCSP 220被多个垂直互连单元484环绕。在一个实施例中，垂直互连单元484是单个单元或者片，并且WLCSP 220放置在通过垂直互连单元形成或穿孔的开口中。
垂直互连单元484包括核心衬底486。核心衬底486包括具有环氧酚醛棉纸、环氧树脂、树脂、布纹玻璃、毛玻璃、聚酯、具有填充物的玻璃纤维和其他加固纤维或织物的组合的聚四氟乙烯半固化片FR-4、FR-1、CEM-1或CEM-3的一个或多个层压的层。可替代地，核心衬底486包括一个或多个绝缘或钝化层。
使用激光钻孔、机械钻孔或DRIE形成穿过核心衬底486的多个穿过通孔。使用电镀、无电镀或其他合适的沉积工艺用Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合适的电气导电材料填充这些通孔以形成z方向垂直互连或导电通孔488。在一个实施例中，Cu通过无电镀和电镀沉积在穿过通孔的侧壁上，并且穿过通孔中的剩余空间被填充有绝缘或导电填充物材料。
使用诸如印刷、PVD、CVD、溅射、电镀和无电镀的图案化与金属沉积工艺在核心衬底486和导电通孔488的表面上形成电气导电层或RDL 490。导电层490包括Al、Cu、Sn、Ni、Au、Ag或其他合适的电气导电材料的一个或多个层。导电层490电气连接到导电通孔488。导电层490操作为电气连接到导电通孔488的接触垫。
使用诸如印刷、PVD、CVD、溅射、电镀、无电镀的图案化和金属沉积工艺将电气导电层或RDL 492形成在核心衬底486的与导电层490相对的表面上。导电层492包括Al、Cu、Sn、Ni、Au、Ag或其他合适的电气导电材料的一个或多个层。导电层492电气连接到导电通孔488和导电层490。导电层492操作为电气连接到导电通孔488的接触垫。可替代地，在形成导电层490和/或导电层492之后，穿过核心衬底486形成导电通孔488。
图8d示出了安装到载体480以形成重建的晶圆500的WLCSP 220和垂直互连单元484。在图8e中，使用浆印刷、压缩成型、传递成型、液体密封剂成型、真空层压或其他合适的敷贴器将密封剂或成型化合物502沉积在WLCSP 220和垂直互连单元484上。密封剂502可以是聚合物合成材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有合适填充物的聚合物。密封剂502是非导电的，提供物理支持，并且在环境上保护半导体器件免受外部元素和污染影响。密封剂502还保护半导体管芯124免于由于曝露于光而导致的退化。密封剂502的与后侧表面504相对的表面506放置在载体480和界面层482上，使得密封剂502的表面506与WLCSP 220的绝缘层182共面。
在图8f中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体480和界面层482，并且堆积互连结构522形成在密封剂502的表面506、WLCSP 220和垂直互连单元484上。堆积互连结构522包括绝缘层512、导电层514、绝缘层516、导电层518以及绝缘层520。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层512形成在密封剂502的表面506、WLCSP 220的绝缘层182和垂直互连单元484上。绝缘层512包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层512的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露WLCSP 220的导电层184和垂直互连单元484的导电层492。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 514形成在绝缘层512上。导电层514可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适电气导电材料的一个或多个层。导电层514的一个部分电气连接到WL RDL 194的导电层184。导电层514的一个部分电气连接到垂直互连单元484的导电层492。导电层514的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124的设计和功能。导电层514包括多个导电迹线。导电层514的导电迹线利用比WL RDL 194内的导电迹线宽的节距形成。在一个实施例中，导电层514的导电迹线具有15µm或更大的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层516形成在绝缘层512和导电层514上。绝缘层516包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层516的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层514。
使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 518形成在绝缘层516和导电层514上。导电层518可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适的电气导电材料的一个或多个层。导电层518的一个部分电气连接到导电层514。导电层518的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124的设计和功能。导电层518包括多个导电迹线。导电层518的导电迹线利用比WL RDL 194中的导电层184和188的导电迹线宽的节距来形成。在一个实施例中，导电层518的导电迹线具有15µm或更大的节距。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层520形成在绝缘层516和导电层518上。绝缘层520包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层520是焊阻。绝缘层520的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层518。
绝缘层512、导电层514、绝缘层516、导电层518以及绝缘层520的组合构成堆积互连结构522。在堆积互连结构522内包括的绝缘层和导电层的数量取决于电路路由设计的复杂度并且随之变化。因此，堆积互连结构522可以包括任何数量的绝缘层和导电层以促进针对半导体管芯124的电气互连。堆积互连结构522内的导电迹线的放松设计规则和较大节距允许在堆积互连结构522的建造中使用的材料和制造技术的较大灵活性，这减小整体制造成本。
使用蒸发、电镀、无电镀、落球或丝网印刷工艺将电气导电凸起材料沉积在导电层518上。凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的钎剂溶液。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层518。在一个实施例中，凸起材料通过将材料加热到材料的熔点以上而被回流以形成球或凸起524。在一些应用中，凸起524第二次回流以改进至导电层518的电气接触。在一个实施例中，凸起524形成在UBM层上。凸起524还可以压缩接合或热压缩接合到导电层518。凸起524代表可以形成在导电层518上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。
在图8g中，使用研磨器526从密封剂502的表面504移除密封剂502的一部分。背面研磨操作从半导体管芯124的后表面128上移除密封剂502并减小重建的晶圆500的厚度。移除密封剂502还减小了重建的晶圆500的翘曲。在一个实施例中，在背面研磨操作期间从后表面128移除半导体管芯124的一部分以进一步打薄重建的晶圆500。在背面研磨之后，密封剂502保留在垂直互连单元484上，并且密封剂502的表面528与半导体管芯124的表面128共面。密封剂502的表面528与导电层490之间的厚度D1是10-50µm。可以在背面研磨之后执行对重建的晶圆500的用于对齐、单体化和/或封装标识的激光标记。
在图8h中，从垂直互连单元484上移除密封剂502的一部分以形成开口530。开口530包括垂直或倾斜的侧壁，并且从密封剂502的表面528延伸到垂直互连单元484的导电层490。通过使用激光器532的LDA、蚀刻或其他合适的工艺来形成开口530。通过在半导体管芯124的外围区中形成穿过密封剂502的开口530，从密封剂502的后侧曝露导电层490的一部分。开口530被配置为在半导体管芯124以及在半导体管芯或在WLCSP 220上堆叠的器件之间提供3-D电气互连，所述器件例如是存储器器件、无源器件、声表面波滤波器滤波器、电感器、天线等。在一个实施例中，诸如Cu有机可焊性保护（OSP）的精加工（finish）被应用到曝露的导电层490来防止Cu氧化。在替代实施例中，焊膏被印刷在导电层490的表面上并且回流以形成焊料帽并保护导电层490的表面。在替代实施例中，在形成开口530之后在重建的晶圆500上形成堆积互连结构522和凸起524。
在图8i中，使用锯条或激光切割工具534通过堆积互连结构522、垂直互连单元484的核心衬底486和密封剂502将重建的晶圆500单体化成个体半导体器件538，包括WLCSP220、垂直互连单元484以及堆积互连结构522。
图9示出单体化后的半导体器件538。半导体管芯124通过WL RDL 194和堆积互连结构522电气连接到凸起524以连接到诸如PCB的外部器件。WL RDL 194在半导体管芯124之间以及在半导体管芯124与堆积互连结构522之间路由电气信号。堆积互连结构522在WLCSP220、垂直互连单元484与外部器件之间路由电气信号。形成两种分离的堆积互连结构（即WLRDL 194和堆积互连结构522）允许WL RDL 194利用窄节距 RDL建造技术以增加半导体器件538的I/O和电气性能，而堆积互连结构522利用标准Fo-eWLB建造技术最小化成本并提供至外部部件的附加路由。在附着半导体管芯124之前以超窄节距在临时衬底180上形成WL RDL194的导电层184和188，从而提供了形成RDL的成本有效的方式，其可伸缩到亚微米尺寸，即在纳米范围中。导电层184和188内的导电迹线的窄节距允许WL RDL 194内的互连的较高密度。互连的高密度在半导体器件的集成方面提供了更多灵活性，并且容纳具有变化的凸起节距的半导体管芯，例如，来自多个制造源的半导体管芯。另外，导电迹线的窄节距减小了WL RDL 194的大小，并且缩短了半导体管芯124与凸起524之间的互连距离，即电气信号必须行进的距离。较短的互连距离增加了半导体器件538的速度和电气性能。
与用于形成TSV中介层封装的工艺相比，使用更快、更不昂贵并且更低风险的工艺来形成半导体器件538内的WL RDL 194和堆积互连结构522。另外，在不必并入TSV中介层的情况下提供电气互连减小了半导体器件538的尺寸和封装轮廓。在堆积互连结构522之前并且独立于堆积互连结构522形成WLCSP 220允许在将WLCSP 220安装到衬底480之前测试在半导体管芯124之间的信号路由和WLCSP 220的功能性。因此，仅已知良好的WLCSP 220被并入半导体器件538。使用仅已知良好的WLCSP 220建造半导体器件538，防止制造时间和材料被浪费于制作有缺陷封装，并因此，半导体器件538的产量增加并且整体成本减小。
堆积互连结构522在半导体器件538内提供了附加导电层。该附加导电层可以用于连接到其他内部或外部器件。在密封剂502内嵌入垂直互连单元484提供了对放置在半导体器件538上的器件的电气互连，并且增加了半导体器件538的功能性和电气性能，而不用增加封装轮廓。堆积互连结构522的导电层514和518利用放松的设计规则使用标准Fo-eWLB工艺来形成。放松堆积互连结构522的设计规则允许在堆积互连结构522的建造中使用的材料和制造技术的较大灵活性。例如，与特定于建造具有超窄节距的导电层的材料相对的，可以使用标准Fo-eWLB装备和材料来形成堆积互连结构522。标准化的装备和材料的使用减小了半导体器件538的制造时间和成本。堆积互连结构522内的导电迹线的较宽节距也提供了在凸起524的放置和节距方面的较大灵活性。可以选择凸起524的节距以反映工业标准。例如，可以利用与标准PCB上的互连垫相同的节距来形成凸起524。在一个实施例中，凸起524具有0.4mm的节距。放松凸起524的设计规则增加了半导体器件538与外部器件的兼容性，并且消除了对额外衬底或中介层的需要。
在牺牲衬底180上形成细节距的WL RDL 194、通过芯片到晶圆成型将WL RDL 194转移到半导体管芯124以及使用标准Fo-eWLB建造工艺在WLCSP 220和垂直互连单元484上形成堆积互连结构522，以上允许半导体器件538并入具有高和/或不同I/O要求的半导体管芯，同时最小化半导体器件538的大小、制造时间以及成本。
图10a-10f图示了与图1和2a-2c相关的用于在包括细节距的RDL和嵌入的垂直互连单元的半导体器件上形成双面RDL的过程。从图8e继续，图10a示出了重建的晶圆500，其包括放置在载体480和界面层482上的WLCSP 220和垂直互连单元484。密封剂502沉积在WLCSP 220和垂直互连单元484上。在一个实施例中，与图8g类似地，在后续背面研磨操作中从密封剂502的表面504移除密封剂502的一部分。
从垂直互连单元484上移除密封剂502的一部分以形成开口510。开口510包括垂直或倾斜的侧壁，并且从密封剂502的表面504延伸到垂直互连单元484的导电层490。通过LDA、蚀刻或其他合适的工艺来形成开口510。在半导体管芯124的外围区中形成开口510，并且开口510曝露导电层490的一部分。
在图10b中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层540形成在密封剂502和垂直互连单元484上。绝缘层540包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。绝缘层540的部分通过LDA、蚀刻或其他合适的工艺被移除以曝露垂直互连单元484的导电层490。
在图10c中，使用PVD、CVD、电镀或无电镀工艺将电气导电层或RDL 542形成在绝缘层540和导电层490上。导电层542可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu或其他合适电气导电材料的一个或多个层。导电层542的一个部分电气连接到垂直互连单元484的导电层490。导电层542的一个部分电气连接到垂直互连单元484的导电层492。导电层542的其他部分可以是电气公共的或者是电气隔离的，这取决于半导体管芯124和之后安装的半导体管芯或器件的设计和功能。
在图10d中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层544形成在绝缘层540和导电层542上。绝缘层544包括Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物电介质、低温（小于250ºC）固化聚合物电介质材料或具有类似绝缘和结构属性的其他材料的一个或多个层。在一个实施例中，绝缘层544是焊阻。绝缘层544的一部分通过LDA、蚀刻或其他合适的工艺被移除以曝露导电层542。导电层542的曝露的部分提供3-D电气互连，并且促进在WLCSP 220上半导体管芯或器件的堆叠，所述器件例如是存储器器件、无源器件、声表面波滤波器滤波器、电感器、天线等。
在图10e中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烤、UV光、激光扫描或湿法脱膜来移除载体480和界面层482，并且堆积互连结构522形成在密封剂502的表面506、WLCSP 220和垂直互连单元484上，堆积互连结构522包括绝缘层512、导电层514、绝缘层516、导电层518以及绝缘层520。
在图10f中，凸起524形成在导电层518上。凸起524代表可以形成在导电层518上的一种类型的互连结构。互连结构还可以使用接合线、导电胶、柱形凸起、微凸起或其他电气互连。可替代地，在密封剂502中形成开口510之前在重建的晶圆500上形成堆积互连结构522和凸起524。可以在凸起形成之前或之后执行对重建的晶圆500的用于对齐、单体化和/或封装标识的激光标记。
图10f还示出了使用锯条或激光切割工具546通过堆积互连结构522、垂直互连单元484的核心衬底486和密封剂502将重建的晶圆500单体化成个体半导体器件550，包括WLCSP 220、垂直互连单元484以及双面RDL，即导电层542和导电层514及518。
图11示出单体化后的半导体器件550。半导体管芯124通过WL RDL 194和堆积互连结构522电气连接到凸起524以连接到诸如PCB的外部器件。WL RDL 194在半导体管芯124之间以及在半导体管芯124与堆积互连结构522之间路由电气信号。堆积互连结构522在WLCSP220、垂直互连单元484与外部器件之间路由电气信号。形成两种分离的堆积互连结构（即WLRDL 194和堆积互连结构522）允许WL RDL 194利用窄节距 RDL建造技术以增加半导体器件550的I/O和电气性能，而堆积互连结构522利用标准Fo-eWLB建造技术最小化成本并提供至外部部件的附加路由。在附着半导体管芯124之前以超窄节距在临时衬底180上形成WL RDL194的导电层184和188，从而提供了形成RDL的成本有效的方式，其可伸缩到亚微米尺寸，即在纳米范围中。导电层184和188内的导电迹线的窄节距允许WL RDL 194内的互连的较高密度。互连的高密度在半导体器件的集成方面提供了更多灵活性，并且容纳具有变化的凸起节距的半导体管芯，例如，来自多个制造源的半导体管芯。另外，导电迹线的窄节距减小了WL RDL 194的大小，并且缩短了半导体管芯124与凸起524之间的互连距离，即电气信号必须行进的距离。较短的互连距离增加了半导体器件550的速度和电气性能。
与用于形成TSV中介层封装的工艺相比，使用更快、更不昂贵并且更低风险的工艺来形成半导体器件550内的WL RDL 194和堆积互连结构522。另外，在不必并入TSV中介层的情况下提供电气互连减小了半导体器件550的尺寸和封装轮廓。在堆积互连结构522之前并且独立于堆积互连结构522形成WLCSP 220允许在将WLCSP 220安装到衬底480之前测试在半导体管芯124之间的信号路由和WLCSP 220的功能性。因此，仅已知良好的WLCSP 220被并入半导体器件550。使用仅已知良好的WLCSP 220建造半导体器件550，防止制造时间和材料被浪费于制作有缺陷封装，并因此，半导体器件550的产量增加并且整体成本减小。
堆积互连结构522在半导体器件550内提供了附加导电层,该附加导电层可以用于连接到其他内部或外部器件。在密封剂502内嵌入垂直互连单元484并且在WLCSP 220的两侧（即，密封剂502的表面504上的导电层542和在密封剂502的表面506上的导电层514及518）上形成RDL，以上促进后续放置在半导体器件570上的器件的电气互连和堆叠。在密封剂502内嵌入垂直互连单元484并且在WLCSP 220的两侧上形成RDL增加了半导体器件550的功能性和电气性能，而不用增加封装轮廓。堆积互连结构522的导电层514和518利用放松的设计规则使用标准Fo-eWLB工艺来形成。放松堆积互连结构522的设计规则允许在堆积互连结构522的建造中使用的材料和制造技术的较大灵活性。例如，与特定于建造具有超窄节距的导电层的材料相对的，可以使用标准Fo-eWLB装备和材料来形成堆积互连结构522。标准化的装备和材料的使用减小了半导体器件550的制造时间和成本。堆积互连结构522内的导电迹线的较宽节距也提供了在凸起524的放置和节距方面的较大灵活性。可以选择凸起524的节距以反映工业标准。例如，可以利用与标准PCB上的互连垫相同的节距来形成凸起524。在一个实施例中，凸起524具有0.4mm的节距。放松凸起524的设计规则增加了半导体器件550与外部器件的兼容性，并且消除了对额外衬底或中介层的需要。
在牺牲衬底180上形成细节距的WL RDL 194、通过芯片到晶圆成型将WL RDL 194转移到半导体管芯124，以及使用标准Fo-eWLB建造工艺在WLCSP 220和垂直互连单元484上形成堆积互连结构522，以上允许半导体器件550并入具有高和/或不同I/O要求的半导体管芯，同时最小化半导体器件550的大小、制造时间以及成本。
图12示出了与图11中的半导体器件550类似的半导体器件560。半导体器件560包括放置在密封剂502内的半导体部件或无源器件562。无源器件562电气连接到堆积互连结构522。嵌入在半导体器件560内的无源器件562增加半导体器件560的功能性和电气性能。
半导体管芯124通过WL RDL 194和堆积互连结构522电气连接到凸起524以连接到外部器件。WL RDL 194在半导体管芯124之间以及在半导体管芯124与堆积互连结构522之间路由电气信号。堆积互连结构522在WLCSP 220、无源器件562、垂直互连单元484与诸如PCB的外部器件之间路由电气信号。形成两种分离的堆积互连结构（即WL RDL 194和堆积互连结构522）允许WL RDL 194利用窄节距 RDL建造技术以增加半导体器件560的I/O和电气性能，而堆积互连结构522利用标准Fo-eWLB建造技术最小化成本并提供至外部部件的附加路由。在附着半导体管芯124之前以超窄节距在临时衬底180上形成WL RDL 194的导电层184和188，从而提供了形成RDL的成本有效的方式，其可伸缩到亚微米尺寸，即在纳米范围中。导电层184和188内的导电迹线的窄节距允许WL RDL 194内的互连的较高密度。互连的高密度在半导体器件的集成方面提供了更多灵活性，并且容纳具有变化的凸起节距的半导体管芯，例如，来自多个制造源的半导体管芯。另外，导电迹线的窄节距减小了WL RDL 194的大小，并且缩短了半导体管芯124与凸起524之间的互连距离，即电气信号必须行进的距离。较短的互连距离增加了半导体器件560的速度和电气性能。
与用于形成TSV中介层封装的工艺相比，使用更快、更不昂贵并且更低风险的工艺来形成半导体器件560内的WL RDL 194和堆积互连结构522。另外，在不必并入TSV中介层的情况下提供电气互连减小了半导体器件560的尺寸和封装轮廓。在堆积互连结构522之前并且独立于堆积互连结构522形成WLCSP 220允许在将WLCSP 220安装到衬底480之前测试在半导体管芯124之间的信号路由和WLCSP 220的功能性。因此，仅已知良好的WLCSP 220被并入半导体器件560。使用仅已知良好的WLCSP 220建造半导体器件560，防止制造时间和材料被浪费于制作有缺陷封装，并因此，半导体器件560的产量增加并且整体成本减小。
堆积互连结构522在半导体器件560内提供了附加导电层,该附加导电层可以用于连接到诸如无源器件562的其他内部或外部器件。在密封剂502内嵌入垂直互连单元484并且在WLCSP 220的两侧（即，密封剂502的表面504上的导电层542和在密封剂502的表面506上的导电层514及518）上形成RDL，以上促进后续放置在半导体器件560上的器件的电气互连和堆叠。在密封剂502内嵌入垂直互连单元484并且在WLCSP 220的两侧上形成RDL增加了半导体器件560的功能性和电气性能，而不用增加封装轮廓。堆积互连结构522的导电层514和518利用放松的设计规则使用标准Fo-eWLB工艺来形成。放松堆积互连结构522的设计规则允许在堆积互连结构522的建造中使用的材料和制造技术的较大灵活性。例如，与特定于建造具有超窄节距的导电层的材料相对的，可以使用标准Fo-eWLB装备和材料来形成堆积互连结构522。标准化的装备和材料的使用减小了半导体器件560的制造时间和成本。堆积互连结构522内的导电迹线的较宽节距也提供了在凸起524的放置和节距方面的较大灵活性。可以选择凸起524的节距以反映工业标准。例如，可以利用与标准PCB上的互连垫相同的节距来形成凸起524。在一个实施例中，凸起524具有0.4mm的节距。放松凸起524的设计规则增加了半导体器件560与外部器件的兼容性，并且消除了对额外衬底或中介层的需要。
在牺牲衬底180上形成细节距的WL RDL 194、通过芯片到晶圆成型将WL RDL 194转移到半导体管芯124，以及使用标准Fo-eWLB建造工艺在WLCSP 220、垂直互连单元484以及无源器件562上形成堆积互连结构522，以上允许半导体器件560并入具有高和/或不同I/O要求的半导体管芯，同时最小化半导体器件560的大小、制造时间以及成本。
尽管已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将意识到，可以在不脱离所附权利要求中阐述的本发明的范围的情况下做出对这些实施例的修改和改编。

Claims (13)

1.一种制作半导体器件的方法，包括：
提供衬底；
在所述衬底上形成第一导电层；
将第一半导体管芯放置在所述第一导电层上；
将第一密封剂放置在所述第一半导体管芯、所述衬底和所述第一导电层上；
在沉积第一密封剂之后移除所述衬底的一部分以暴露所述导电层；
在移除所述衬底的所述一部分之后将第二密封剂放置在所述第一密封剂和所述导电层周围；以及
在所述第一导电层和所述第二密封剂上形成第二导电层。
2.根据权利要求1所述的方法，还包括在所述第一密封剂中放置无源器件。
3.根据权利要求1所述的方法，还包括在所述第二密封剂中放置无源器件。
4.根据权利要求1所述的方法，还包括在所述第一导电层上放置第二半导体管芯。
5.根据权利要求1所述的方法，还包括在所述第一半导体管芯的外围区中放置垂直互连单元。
6.一种制作半导体器件的方法，包括：
提供第一导电层；
在所述第一导电层上放置第一半导体管芯；
在所述第一半导体管芯上放置第一密封剂；
单体化所述第一密封剂；以及
在单体化所述第一密封剂之后，在所述第一导电层上形成与所述第一半导体管芯相对的第二导电层。
7.根据权利要求6所述的方法，还包括在所述第一导电层上放置第二半导体管芯。
8.根据权利要求6所述的方法，还包括在所述第一半导体管芯的外围区中放置无源器件。
9.根据权利要求6所述的方法，还包括：
在单体化所述第一密封剂之后，在所述第一密封剂上沉积第二密封剂；以及
在沉积所述第二密封剂之后形成所述第二导电层。
10.根据权利要求6所述的方法，其中，所述第一导电层包括多个第一导电迹线，并且所述第二导电层包括多个第二导电迹线，并且第一导电迹线的节距小于第二导电迹线的节距。
11.一种半导体器件，包括：
第一导电层，包括多个第一导电迹线；
第一半导体管芯，放置在所述第一导电层的第一表面上；
第二导电层，包括多个第二导电迹线，所述第二导电层放置在所述第一导电层的与所述第一导电层的所述第一表面相对的第二表面上，其中第一导电迹线的节距小于第二导电迹线的节距；
沉积在所述第一半导体管芯和所述第一导电层上的第一密封剂; 以及
沉积在所述第一密封剂上并在所述第一导电层周围的第二密封剂。
12.根据权利要求11所述的半导体器件，还包括放置在所述第二密封剂中的垂直互连单元。
13.根据权利要求11所述的半导体器件，还包括放置在所述第一导电层上的第二半导体管芯。
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