CN107331623B - 一种晶片及芯片的封装方法 - Google Patents

一种晶片及芯片的封装方法 Download PDF

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CN107331623B
CN107331623B CN201710536380.4A CN201710536380A CN107331623B CN 107331623 B CN107331623 B CN 107331623B CN 201710536380 A CN201710536380 A CN 201710536380A CN 107331623 B CN107331623 B CN 107331623B
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chip
inscribed
wafer
shape
closed figures
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CN107331623A (zh
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杜渊鑫
王志东
曲连杰
齐永莲
邱云
吕振华
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/991,374 priority patent/US20190006197A1/en
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Abstract

本发明的实施例提供一种晶片及芯片的封装方法，涉及半导体技术领域，可提高产出规模以及产出效率，且降低成本。一种芯片的封装方法，包括：将多个晶片固定于第一面板级衬底上，同时在每个芯片上形成封装用结构；其中，多个晶片无交叠紧密排布于第一面板级衬底上；晶片由晶圆加工得到，所述晶圆包括若干芯片，所述晶片的外形为所述晶圆外形的内接闭合图形；其中，所述内接闭合图形的面积大于所述晶圆外形的内接正方形的面积；所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等。

Description

一种晶片及芯片的封装方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种晶片及芯片的封装方法。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化以及高可靠性方向发展，而集成电路封装直接影响着集成电路、电子模块乃至整机性能，在集成电路晶片逐步缩小、集成度不断提高的情况下，对集成电路封装提出了越来越高的要求。
传统的半导体行业的芯片封装主要包括如下过程：将晶圆上的芯片进行切割，分割成各独立的芯片，将合格的芯片重新按规则排布在衬底上，之后进行封装、形成重布线层(Re-Distribution Layers，简称RDLs)和焊球的工艺。
然而由于半导体行业采用的衬底尺寸较小，一般为6寸、8寸、12寸，使得封装后的产出规模受到限制。
发明内容
本发明的实施例提供一种晶片及芯片的封装方法，可提高产出规模以及产出效率，且降低成本。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种晶片，由晶圆加工得到，所述晶圆包括若干芯片，所述晶片的外形为所述晶圆外形的内接闭合图形；其中，所述内接闭合图形的面积大于所述晶圆外形的内接正方形的面积；所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等。
可选的，所述晶片的外形为所述晶圆外形的内接多边形。
进一步优选的，所述晶片的外形为所述晶圆外形的内接正六边形。
可选的，所述内接闭合图形还包括位于相邻的两条直线之间的弧形角，且所述弧形角由所述晶圆外形的一部分线段得到。
进一步优选的，所述内接闭合图形为四边等长、四角为等度弧形的闭合图形。
第二方面，提供一种芯片的封装方法，包括：将多个第一方面所述的晶片固定于第一面板级衬底上，同时在每个芯片上形成封装用结构；其中，多个所述晶片无交叠紧密排布于所述第一面板级衬底上。
可选的，所述封装用结构包括重布线层；在每个芯片上形成封装用结构之后，所述芯片的封装方法还包括：通过切割形成各独立的所述芯片和与所述芯片连接的所述重布线层，以将所述芯片和与所述芯片连接的所述重布线层重新排布于第二面板级衬底上，对所述芯片进行封装，形成封装层。
可选的，所述封装用结构包括支柱以及焊料帽；在每个芯片上形成封装用结构之后，所述芯片的封装方法还包括：通过切割形成各独立的所述芯片以及与所述芯片电连接的所述支柱和所述焊料帽，以通过所述焊料帽与重布线层连接后对所述芯片进行封装，形成封装层。
本发明的实施例提供一种晶片及芯片的封装方法，通过将晶圆加工成其外形的内接闭合图形形状而得到，其中，通过使内接闭合图形的面积大于所述晶圆外形的内接正方形的面积，可使晶圆的利用率不至于太低(可达到63％以上)，通过使所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等，可保证将晶片排布于第一面板级衬底上时，第一面板级衬底的利用率高于将晶圆排布于第一面板级衬底上时的利用率。综上，本发明可兼容晶圆以及面板级衬底的利用率，从而降低成本。此外，通过将晶片固定于第一面板级衬底上，可在面板领域的产线进行形成封装用结构的工艺，因而可提高产出规模以及产出效率，而且降低了传统半导体行业封装的成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的一种晶片的形状示意图一；
图2为本发明提供的一种晶片的形状示意图二；
图3为本发明提供的一种晶片的形状示意图三；
图4为本发明提供的一种晶片的形状示意图四；
图5为本发明提供的一种晶片的形状示意图五；
图6为本发明提供的一种晶圆的示意图；
图7为本发明提供的一种将多个晶片排布于第一面板级衬底上的示意图一；
图8为本发明提供的一种将多个晶片排布于第一面板级衬底上的示意图二；
图9为本发明提供的一种将多个晶片排布于第一面板级衬底上的示意图三；
图10为本发明提供的一种将多个晶片排布于第一面板级衬底上的示意图四；
图11为本发明提供的一种将多个晶片排布于第一面板级衬底上的示意图五；
图12为本发明提供的一种将多个晶圆排布于第一面板级衬底上的示意图；
图13a为本发明提供的一种在芯片上形成重布线层的示意图；
图13b为在图13a的基础上形成各独立的芯片和与该芯片连接的重布线层的示意图；
图14a为本发明提供的一种在芯片上形成支柱以焊料帽的示意图；
图14b为在图14a的基础上形成各独立的芯片以及与芯片连接的支柱和焊料帽的示意图。
附图标记：
10-晶片；20-晶圆；201-芯片；30-内接正方形；40-第一面板级衬底；50-重布线层；601-支柱；602-焊料帽。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种晶片10，如图1-图5所示，由晶圆20加工得到，该晶圆20包括若干芯片(图1-图5中未示意出)，所述晶片10的外形为该晶圆20外形的内接闭合图形；其中，内接闭合图形的面积大于所述晶圆20外形的内接正方形30的面积；所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等。
需要说明的是，第一，本领域技术人员应该明白，晶圆20的外形如图6所示为圆形。按其直径，可分为6寸、8寸、12寸等。
每个晶圆20中包括若干个芯片201。
第二，由晶圆20加工成晶片10，厚度不会发生变化。
由于晶片10的面积必然小于晶圆20的面积，因此，当将晶圆20加工为晶片10时，晶圆20的除晶片10所在区域的芯片201会被切割掉，从而得到所需形状的晶片10。
第三，当将晶圆20加工为其外形的内接正方形30时，设晶圆20的半径为r，晶圆20的利用率只能达到2r2/πr2＝63％。本发明的晶片10面积由于大于所述内接正方形30的面积，因此，本发明晶圆20的利用率势必大于63％，芯片201的浪费也会少一些。
第四，当晶片10的外形为六边形，且六边形的边两两平行相对设置、长度相等时，如图7和图8所示，将本发明的晶片10无交叠紧密排布于第一面板级衬底40上，在不考虑第一面板级衬底40的边缘的情况下，晶片10之间可无缝排布于第一面板级衬底40上，因而第一面板级衬底40的利用率很高。
当晶片10的外形为大于六边形的偶数边形，且大于六边形的偶数边形的边两两平行相对设置、长度相等时，如图9所示，将本发明的晶片10无交叠紧密排布于第一面板级衬底40上，在不考虑第一面板级衬底40的边缘的情况下，任意相邻四个晶片10之间具有空隙，但是参考图12所示的任意相邻四个晶圆20(通过该晶圆20得到图9中的晶片10)之间的空隙，任意相邻四个晶片10之间的空隙面积更小，因而第一面板级衬底40的利用率也较高。其中，图9以八边形为例进行示意。
当晶片10的外形包括四条及以上偶数条直线边，且偶数条直线边两两平行相对设置、长度相等、相邻的两条边之间具有弧形角时，如图10所示，将本发明的晶片10无交叠紧密排布于第一面板级衬底40上，在不考虑第一面板级衬底40的边缘的情况下，任意相邻四个晶片10之间具有空隙，但是参考图12所示的任意相邻四个晶圆20(通过该晶圆20得到图10中的晶片10)之间的空隙，任意相邻四个晶片10之间的空隙面积更小，因而第一面板级衬底40的利用率也较高。图10以四条边为例进行示意。
当晶片10的外形包括两条平行相对设置且等长的直线边，两条相对设置的弧线边时，如图11所示，将本发明的晶片10无交叠紧密排布于第一面板级衬底40上，在不考虑第一面板级衬底40的边缘的情况下，任意相邻四个晶片10之间具有空隙，但是参考图12所示的任意相邻四个晶圆20(通过该晶圆20得到图11中的晶片10)之间的空隙，任意相邻四个晶片10之间的空隙面积更小，因而第一面板级衬底40的利用率也较高。
其中，不管本发明的晶片10是任何形状，在第一面板级衬底40的边缘都会存在空隙，但是第一面板级衬底40的尺寸越大，相应的面板级衬底40的边缘处的空隙所占比例越小。
当然，对于晶圆20，其在面板级衬底40的边缘也是存在空隙的。
第五，附图1-5的晶片10形状仅为示意，可综合考虑芯片201成本以及第一面板级衬底40的成本，以最低化的成本来设定晶圆20利用率以及第一面板级衬底40利用率，从而选取合适外形形状的晶片10。
本发明实施例提供一种晶片10，通过将晶圆20加工成其外形的内接闭合图形形状而得到，其中，通过使内接闭合图形的面积大于所述晶圆20外形的内接正方形30的面积，可使晶圆20的利用率不至于太低(可达到63％以上)，通过使所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等，可保证将晶片10排布于第一面板级衬底40上时，第一面板级衬底40的利用率高于将晶圆20排布于第一面板级衬底40上时的利用率。综上，本发明可兼容晶圆20以及面板级衬底的利用率，从而降低成本。
可选的，如图1-3所示，晶片10的外形为晶圆20外形的内接多边形。
通过将晶片10的形状加工为内接多边形，在保证晶圆20利用率的基础上，更有利用提高第一面板级衬底40的利用率。
进一步优选的，如图2所示，晶片10的外形为晶圆20外形的内接正六边形。
其中，设晶圆20的半径为r，晶圆20外形的内接正六边形的面积为基于此，晶圆20的利用率可达到
此外，当将晶片10无交叠紧密排布于第一面板级衬底40上(如图8所示)，在不考虑第一面板级衬底40的边缘的情况下，第一面板级衬底40的利用率可达到100％。
本发明实施例通过将晶片10外形加工为晶圆20外形的内接正六边形，可获得晶圆20利用率和第一面板级衬底40利用率的最大化。
可选的，如图4所示，所述内接闭合图形还包括位于相邻的两条直线之间的弧形角，且所述弧形角由晶圆20外形的一部分线段得到。
即，如图4所示，在将晶圆20加工为晶片10时，仅将图4中实线的直线以外的晶圆20部分切割掉，从而形成包括弧形角的晶片10。
本发明实施例使得由晶圆20加工为晶片10的工艺更简单。
进一步优选的，如图4所示，所述内接闭合图形为四边等长、四角为等度弧形的闭合图形。
其中，设晶圆20的半径为r，圆心到各直线边的距离为x，在此情况下，晶圆20外形的内接闭合图形的面积为：
基于此，
当将晶片10无交叠紧密排布于第一面板级衬底40上(如图10所示)，
对于x的值，可根据所需的晶圆20的利用率和第一面板级衬底40的利用率，进行合理选择。
本发明实施例通过将晶片10的形状加工为四边等长、四角为等度弧形的闭合图形，更有利于提高晶圆20的利用率，同时第一面板级衬底40虽然不能达到100％，但第一面板级衬底40的利用率也很高。
本发明实施例还提供一种芯片的封装方法，如图7-11所示，包括将上述的多个晶片10固定于第一面板级衬底40上，同时在每个芯片201上形成封装用结构；其中，多个晶片10无交叠紧密排布于面板级衬底40上。
第一面板级衬底40为面板行业所用的大型衬底，例如1100mm×1300mm的衬底、2200mm×2500mm的衬底等。
可通过粘胶层将晶片10固定于第一面板级衬底40上。粘胶层的材料例如可以是双面胶，或者为UV粘合胶等。
需要说明的是，由于形成封装层时，芯片201之间必须有间距，因此，将晶片10固定于第一面板级衬底40，以同时大面积形成封装用结构，应为形成封装层之间的一个工艺过程。
本发明实施例通过将晶片10固定于第一面板级衬底40上，可在面板领域的产线进行形成封装用结构的工艺，因而可提高产出规模以及产出效率，而且降低了传统半导体行业封装的成本。
可选的，如图13a所示，所述封装用结构包括重布线层(Re-Distribution Layers，简称RDLs)50；基于此，在每个芯片201上形成封装用结构之后，所述芯片的封装方法还包括：通过切割形成各独立的芯片201和与芯片201连接的重布线层50(如图13b所示)，以将芯片201和与芯片201连接的重布线层50重新排布于第二面板级衬底上，对芯片201进行封装，形成封装层。
其中，第二面板级衬底与第一面板级衬底40的尺寸优选相同。
当每个晶片10包括N个芯片201，且第一面板级衬底40上设置了M个晶片10时，通过切割后，可得到M×N个独立的芯片201；其中，M、N为正整数。当然，与每个芯片201连接的重布线层50，也通过切割其周围的介质层而使用于与不同芯片201连接的重布线层50之间分离。
当通过切割得到M×N个独立的芯片201后，可对每个芯片201进行测试，挑选出合格的芯片201重新排布于第二面板级衬底上，以形成保护芯片201的封装层。
可选的，如图14a所示，所述封装用结构包括支柱601以及焊料帽602；基于此，在每个芯片201上形成封装用结构之后，所述芯片的封装方法还包括：通过切割形成各独立的芯片201以及与芯片201电连接的支柱601和焊料帽602(如图14b所示)，以通过焊料帽602与重布线层连接后对芯片201进行封装，形成封装层。
其中，针对各芯片201的重布线层已经形成在第二面板级衬底上，且为保证在每个芯片201周围都形成封装层，针对各芯片201的重布线层之间应具有间隔。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (8)

1.一种晶片，其特征在于，由晶圆加工得到，所述晶圆包括若干芯片，所述晶片的外形为所述晶圆外形的内接闭合图形；
其中，所述内接闭合图形的面积大于所述晶圆外形的内接正方形的面积；
所述内接闭合图形包括偶数条直线，所述偶数条直线两两平行相对设置，且相对的两条平行直线的长度相等；
所述晶片排布于第一面板级衬底上。
2.根据权利要求1所述的晶片，其特征在于，所述晶片的外形为所述晶圆外形的内接多边形。
3.根据权利要求2所述的晶片，其特征在于，所述晶片的外形为所述晶圆外形的内接正六边形。
4.根据权利要求1所述的晶片，其特征在于，所述内接闭合图形还包括位于相邻的两条直线之间的弧形角，且所述弧形角由所述晶圆外形的一部分线段得到。
5.根据权利要求4所述的晶片，其特征在于，所述内接闭合图形为四边等长、四角为等度弧形的闭合图形。
6.一种芯片的封装方法，其特征在于，包括：将多个权利要求1-5任一项所述的晶片固定于所述第一面板级衬底上，同时在每个芯片上形成封装用结构；
其中，多个所述晶片无交叠紧密排布于所述第一面板级衬底上。
7.根据权利要求6所述的封装方法，其特征在于，所述封装用结构包括重布线层；
在每个芯片上形成封装用结构之后，所述芯片的封装方法还包括：
通过切割形成各独立的所述芯片和与所述芯片连接的所述重布线层，以将所述芯片和与所述芯片连接的所述重布线层重新排布于第二面板级衬底上，对所述芯片进行封装，形成封装层。
8.根据权利要求6所述的封装方法，其特征在于，所述封装用结构包括支柱以及焊料帽；
在每个芯片上形成封装用结构之后，所述芯片的封装方法还包括：通过切割形成各独立的所述芯片以及与所述芯片电连接的所述支柱和所述焊料帽，以通过所述焊料帽与重布线层连接后对所述芯片进行封装，形成封装层。
CN201710536380.4A 2017-07-03 2017-07-03 一种晶片及芯片的封装方法 Active CN107331623B (zh)

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