US20130040425A1 - Spiral staircase shaped stacked semiconductor package and method for manufacturing the same - Google Patents

Spiral staircase shaped stacked semiconductor package and method for manufacturing the same Download PDF

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Publication number
US20130040425A1
US20130040425A1 US13/633,425 US201213633425A US2013040425A1 US 20130040425 A1 US20130040425 A1 US 20130040425A1 US 201213633425 A US201213633425 A US 201213633425A US 2013040425 A1 US2013040425 A1 US 2013040425A1
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United States
Prior art keywords
electrodes
semiconductor chips
chip selection
pads
semiconductor
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Abandoned
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US13/633,425
Inventor
Da Un NAH
Jae Myun Kim
Tae Hoon Kim
Jung Tae JEONG
Bok Gyu MIN
Ki Bum Kim
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication date
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Priority to US13/633,425 priority Critical patent/US20130040425A1/en
Publication of US20130040425A1 publication Critical patent/US20130040425A1/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a stack package, and more particularly, to a stack package which allows a certain semiconductor chip to be easily selected among stacked semiconductor chips and a method for manufacturing the same.
  • a stack package in which a plurality of memory chips are stacked on each other so as to increase data storage capacity, has been developed in a variety of types.
  • another stack package in which memory chips and system chips are stacked together so as to not only increase data storage capacity but also improve a data processing speed, has also been developed in a variety of types.
  • Embodiments of the present invention are directed to a stack package in which the stack structure of through-electrodes and semiconductor chips is changed such that a certain semiconductor chip can be easily selected among stacked semiconductor chips.
  • embodiments of the present invention are directed to a method for manufacturing the stack package.
  • a stack package comprises a semiconductor chip module including at least two semiconductor chips which have chip selection pads and through-electrodes and are stacked such that the chip selection pads are exposed and the through-electrodes are electrically connected with one another; a substrate having the semiconductor chip module mounted thereto and connection pads; and connection members electrically connecting the respective chip selection pads and the respective connection pads with each other.
  • the respective semiconductor chips may be disposed in a state in which they are sequentially rotated by predetermined angles about centers of the respective semiconductor chips in such a way as to define the shape reminiscent of a spiral staircase so that the chip selection pads of the respective stacked semiconductor chips are exposed.
  • the chip selection pad may be disposed adjacent to any one corner of four corners when each semiconductor chip has the shape of a quadrangular plate.
  • the chip selection pads may be disposed adjacent to two corners of four corners which are opposite in a diagonal direction when each semiconductor chip has the shape of a quadrangular plate.
  • the chip selection pads may be disposed adjacent to two adjoining corners of four corners when each semiconductor chip has the shape of a quadrangular plate.
  • the through-electrodes may be disposed in a symmetrical matrix shaped pattern on each semiconductor chip.
  • the through-electrodes may have a shape possessing a sectional area gradually decreasing from one ends thereof, on which the chip selection pads are formed, to the other ends thereof, which face away from the one ends.
  • the chip selection pad may have a first sectional area, and the through-electrode may have a second sectional area that is greater than the first sectional area.
  • the respective chip selection pads and the respective connection pads corresponding to the chip selection pads may be separated by the same distance.
  • connection members may comprise bonding wires.
  • the stack package may further comprise additional through-electrodes passing through the chip selection pads; and extensions extending from the connection pads corresponding to the additional through-electrodes to portions facing the additional through-electrodes such that the additional-through electrodes and the connection pads can be electrically connected with each other by the connection members.
  • connection members may comprise conductive members which have a spherical shape or a column shape.
  • a method for manufacturing a stack package comprises the steps of preparing semiconductor chips, each semiconductor chip possessing an upper surface and a lower surface facing away from the upper surface and having at least one chip selection pad which is disposed adjacent to at least one corner of corners of the semiconductor chip and through-electrodes which pass through the upper surface and the lower surface; forming a semiconductor chip module by stacking at least two semiconductor chips such that chip selection pads of the semiconductor chips are exposed and through-electrodes of the semiconductor chips are electrically connected with each other; and mounting the semiconductor chip module onto a substrate which has connection pads.
  • the step of mounting the semiconductor chip module onto the substrate may comprise the step of bonding the respective chip selection pads of the respective stacked semiconductor chips and the connection pads of the substrate, corresponding to the chip selection pads, by means of conductive wires.
  • FIG. 1 is a plan view illustrating a semiconductor chip of a stack package in accordance with an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1 .
  • FIG. 3 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • FIG. 4 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • FIGS. 5 and 6 are a plan view and a cross-sectional view illustrating the stack package in accordance with the embodiment of the present invention.
  • FIG. 7 is a plan view illustrating the stack package in accordance with another embodiment of the present invention.
  • FIG. 8 is a plan view illustrating a stack package in accordance with another embodiment of the present invention.
  • FIG. 1 is a plan view illustrating a semiconductor chip of a stack package in accordance with an embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1 .
  • a semiconductor chip 110 includes a chip selection pad 120 and through-electrodes 130 .
  • the semiconductor chip 110 has, for example, the shape of a quadrangular plate.
  • the semiconductor chip 110 has an upper surface 111 , a lower surface 112 which faces away from the upper surface 111 , and side surfaces 113 .
  • the semiconductor chip 110 having the shape of a quadrangular plate possesses four corners.
  • the semiconductor chip 110 has a circuit unit 114 which includes a data storage section (not shown) for storing data and a data processing section (not shown) for processing data.
  • the chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 .
  • the chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 adjacent to any one of the four corners.
  • the chip selection pad 120 is electrically connected with the circuit unit 114 .
  • the chip selection pad 120 which is disposed adjacent to the corner on the upper surface 111 of the semiconductor chip 110 has a first sectional area.
  • the through-electrodes 130 pass through the upper surface 111 and the lower surface 112 , facing away from the upper surface 111 , of the semiconductor chip 110 .
  • the through-electrodes 130 may have a circular or elliptical cross sectional shape when viewed from above. Unlike this, the through-electrodes 130 may have a curved sectional shape. Examples of materials which can be used to form the through-electrodes 130 include copper, copper alloy, and aluminum.
  • one or more through-electrodes 130 can be disposed through the semiconductor chip 110 in the form of a symmetrical matrix shaped pattern.
  • Each through-electrode 130 may have a second sectional area that is greater than the first sectional area of the chip selection pad 120 .
  • the through-electrodes 130 may have a shape which has a sectional area gradually decreasing from one ends thereof to the other ends thereof.
  • the through-electrodes 130 may have the shape of a truncated cone.
  • FIG. 3 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • the semiconductor chip shown in FIG. 3 is substantially the same as the semiconductor chip described above with reference to FIG. 1 , except the number and the disposal of chip selection pads. Therefore, repeated description for the same component parts will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • a semiconductor chip 110 includes chip selection pads 122 and 124 , and through-electrodes 130 .
  • the chip selection pads 122 and 124 include a first chip selection pad 122 and a second chip selection pad 124 .
  • the first chip selection pad 122 is disposed adjacent to the upper left corner in FIG. 3
  • the second chip selection pad 124 is disposed adjacent to the lower right corner in FIG. 3 , which is positioned in a diagonal direction with respect to the first chip selection pad 122 .
  • the first chip selection pad 122 is disposed adjacent to the upper right corner in FIG. 3
  • the second chip selection pad 124 is disposed adjacent to the lower left corner in FIG. 3 , which is positioned in a diagonal direction with respect to the first chip selection pad 122 .
  • FIG. 4 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • the semiconductor chip shown in FIG. 4 is substantially the same as the semiconductor chip described above with reference to FIG. 1 , except the number and the disposal of chip selection pads. Therefore, repeated description for the same component parts will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • a semiconductor chip 110 includes chip selection pads 122 and 124 and through-electrodes 130 .
  • the chip selection pads 122 and 124 include a first chip selection pad 122 and a second chip selection pad 124 which are respectively disposed adjacent to two adjoining corners.
  • the first chip selection pad 122 is disposed adjacent to the upper left corner in FIG. 4
  • the second chip selection pad 124 is disposed adjacent to the lower left corner in FIG. 4 , which adjoins the first chip selection pad 122 .
  • the second chip selection pad 124 can be disposed adjacent to the upper right corner in FIG. 4 .
  • FIGS. 5 and 6 are a plan view and a cross-sectional view illustrating the stack package in accordance with the embodiment of the present invention.
  • a stack package 500 includes a semiconductor chip module 140 , a substrate 150 , and connection members 160 .
  • the semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110 .
  • Each of the stacked semiconductor chips 110 includes a chip selection pad 120 and through-electrodes 130 .
  • the chip selection pad 120 is disposed adjacent to any one of corners on the upper surface of each semiconductor chip 110 .
  • the respective semiconductor chips 110 are stacked in such a manner that the chip selection pads 120 are exposed.
  • the through-electrodes 130 which pass through the respective semiconductor chips 110 are electrically connected with one another.
  • the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110 . Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • the semiconductor chip module 140 which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the chip selection pads 120 exposed from the respective semiconductor chips 110 , is mounted to the upper surface of the substrate 150 .
  • Connection pads 152 are formed on the upper surface of the substrate 150 .
  • the connection pads 152 are disposed on the upper surface of the substrate 150 , for example, in a number corresponding to the number of the chip selection pads 120 .
  • the connection pads 152 can be disposed on the substrate 150 , for example, in the form of a symmetrical matrix shaped pattern.
  • connection members 160 electrically connect the chip selection pads 120 disposed on the respective semiconductor chips 110 and the connection pads 152 of the substrate 150 .
  • the connection members 160 may comprise, for example, bonding wires.
  • FIG. 7 is a plan view illustrating the stack package in accordance with another embodiment of the present invention. Repeated description for the same component parts as those shown in FIG. 5 will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • a semiconductor package 700 includes a semiconductor chip module 140 , a substrate 150 , and connection members 160 .
  • the semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110 .
  • Each of the stacked semiconductor chips 110 includes first and second chip selection pads 122 and 124 , and through-electrodes 130 .
  • the first chip selection pad 122 is disposed adjacent to any one of the corners on the upper surface of each semiconductor chip 110
  • the second chip selection pad 124 is disposed adjacent to another corner of the corners on the upper surface of each semiconductor chip 110 , which is positioned in a diagonal direction with respect to the first chip selection pad 122 .
  • the respective semiconductor chips 110 having the first and second chip selection pads 122 and 124 are stacked in such a manner that the first and second chip selection pads 122 and 124 are exposed.
  • the through-electrodes 130 which pass through the respective semiconductor chips 110 are also electrically connected to one another.
  • the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110 . Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • the semiconductor chip module 140 which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the first and second chip selection pads 122 and 124 exposed from the respective semiconductor chips 110 , is mounted to the upper surface of the substrate 150 .
  • First and second connection pads 154 and 156 are formed on the upper surface of the substrate 150 .
  • the first and second connection pads 154 and 156 are disposed on the upper surface of the substrate 150 , for example, adjacent to the first and second chip selection pads 122 and 124 .
  • connection members 160 electrically connect the first and second chip selection pads 122 and 124 disposed on the respective semiconductor chips 110 and the first and second connection pads 154 and 156 of the substrate 150 .
  • the connection members 160 may comprise, for example, bonding wires.
  • chip selection pads are formed adjacent to one or two corners of each semiconductor chip 110 , unlike this, it can be envisaged that chip selection pads can be formed adjacent to respective corners on the upper surface of each semiconductor chip 110 and through this, an increased number of semiconductor chips 110 can be stacked on the substrate 150 .
  • FIG. 8 is a plan view illustrating a stack package in accordance with another embodiment of the present invention.
  • the stack package shown in FIG. 8 is substantially the same as the stack package described above with reference to FIG. 5 , except additional through-electrodes of semiconductor chips, connection pads and connection members. Therefore, repeated description for the same component parts as those shown in FIG. 5 will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • a stack package 800 includes a semiconductor chip module 140 , a substrate 150 , and connection members 170 .
  • the semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110 .
  • Each of the stacked semiconductor chips 110 includes a chip selection pad 120 , through-electrodes 130 , and an additional through-electrode 125 .
  • the chip selection pad 120 is disposed adjacent to any one of corners on the upper surface of each semiconductor chip 110 .
  • the respective semiconductor chips 110 are stacked in such a manner that the chip selection pads 120 are exposed.
  • the through-electrodes 130 pass through the respective semiconductor chips 110 and are electrically connected with one another.
  • the additional through-electrode 125 passes through the chip selection pad 120 and a portion of each semiconductor chip 110 which corresponds to the chip selection pad 120 .
  • the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110 . Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • the semiconductor chip module 140 which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the chip selection pads 120 exposed from the respective semiconductor chips 110 , is mounted to the upper surface of the substrate 150 .
  • Connection pads 152 are formed on the upper surface of the substrate 150 .
  • the connection pads 152 are disposed on the upper surface of the substrate 150 , for example, in a number corresponding to the number of the chip selection pads 120 .
  • connection pads 152 have extensions 158 which extend to portions facing the additional through-electrodes 125 of the respective chip selection pads 120 .
  • connection members 170 are interposed between the additional through-electrodes 125 disposed in respective semiconductor chips 110 and the extensions 158 facing the additional through-electrodes 125 .
  • the additional through-electrodes 125 and the connection pads 152 are electrically connected with each other by the connection members 170 .
  • the connection members 170 may be conductive members having, for example, a spherical shape or a column shape.
  • the additional through-electrodes 125 may be formed to pass through the portion of the semiconductor chips 110 which are away from the chip selection pads 120 .
  • the connection members 170 may be a conductive pattern, that is, re-distribution layer formed on the upper surface 111 of the semiconductor chips 110 to connect between the chip selection pad and the additional through-electrode 125 .
  • the semiconductor chip 110 including the chip selection pad 120 and the through-electrodes 130 is manufactured through a semiconductor chip manufacturing process and a through-electrode forming process well known in the art.
  • the semiconductor chip 110 has the shape of a quadrangular plate.
  • the semiconductor chip 110 has the circuit unit 114 which includes a data storage section (not shown) for storing data and a data processing section (not shown) for processing data.
  • the chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 .
  • the chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 adjacent to any one of the four corners.
  • the chip selection pad 120 is electrically connected with the circuit unit 114 .
  • the through-electrodes 130 pass through the upper surface 111 and the lower surface 112 , facing away from the upper surface 111 , of the semiconductor chip 110 .
  • the through-electrodes 130 may be formed to have a circular or elliptical cross sectional shape when viewed from above. Unlike this, the through-electrodes 130 may be formed to have a curved sectional shape. Examples of a material which can be used to form the through-electrodes 130 include copper, a copper alloy, and aluminum.
  • the semiconductor chip 110 including the chip selection pad 120 and the through-electrodes 130 is manufactured, as shown in FIG. 5 , at least two, for example, four, semiconductor chips 110 are stacked in the shape of a spiral staircase in such a manner that chip selection pads 120 are exposed and the through-electrodes 130 are electrically connected with one another. In this way, the semiconductor chip module 140 is prepared.
  • the semiconductor chip module 140 is mounted onto the substrate 150 which is formed with the connection pads 152 .
  • the chip selection pads 120 of the respective semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the connection members 160 such as conductive wires, by which the stack package 500 is manufactured.
  • the chip selection pads 120 of the semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the conductive wires.
  • the additional through-electrodes 125 are formed in the semiconductor chips 110 to pass through the chip selection pads 120
  • the extensions 156 are formed on the substrate 150 to extend from the connection pads 152 to the positions of the additional through-electrodes 125
  • the connection members 160 are interposed between the additional through-electrodes 125 and the extensions 156 such that the chip selection pads 120 of the semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the additional through-electrodes 125 and the extensions 156 .
  • the stack package according to the present invention provides advantages in that, in the state in which a plurality of semiconductor chips are stacked, a certain semiconductor chip can be easily selected among the stacked semiconductor chips.

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Abstract

A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application claims priority to Korean patent application number 10-2009-0107588 filed on Nov. 9, 2009, which is incorporated herein by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a stack package, and more particularly, to a stack package which allows a certain semiconductor chip to be easily selected among stacked semiconductor chips and a method for manufacturing the same.
  • These days, semiconductor chips capable of storing and processing huge amounts of data within a relatively short period of time and semiconductor packages having the semiconductor chips have been developed.
  • Recently, a stack package, in which a plurality of memory chips are stacked on each other so as to increase data storage capacity, has been developed in a variety of types. In addition, another stack package, in which memory chips and system chips are stacked together so as to not only increase data storage capacity but also improve a data processing speed, has also been developed in a variety of types.
  • However, in the case of the conventional stack packages, since respective semiconductor chips are stacked in such a way as to completely overlap with one another, it is difficult to select respective semiconductor chips and apply and output data to and from the selected semiconductor chips.
    • BRIEF SUMMARY OF THE INVENTION
  • Embodiments of the present invention are directed to a stack package in which the stack structure of through-electrodes and semiconductor chips is changed such that a certain semiconductor chip can be easily selected among stacked semiconductor chips.
  • Also, embodiments of the present invention are directed to a method for manufacturing the stack package.
  • In one embodiment of the present invention, a stack package comprises a semiconductor chip module including at least two semiconductor chips which have chip selection pads and through-electrodes and are stacked such that the chip selection pads are exposed and the through-electrodes are electrically connected with one another; a substrate having the semiconductor chip module mounted thereto and connection pads; and connection members electrically connecting the respective chip selection pads and the respective connection pads with each other.
  • The respective semiconductor chips may be disposed in a state in which they are sequentially rotated by predetermined angles about centers of the respective semiconductor chips in such a way as to define the shape reminiscent of a spiral staircase so that the chip selection pads of the respective stacked semiconductor chips are exposed.
  • The chip selection pad may be disposed adjacent to any one corner of four corners when each semiconductor chip has the shape of a quadrangular plate.
  • The chip selection pads may be disposed adjacent to two corners of four corners which are opposite in a diagonal direction when each semiconductor chip has the shape of a quadrangular plate.
  • The chip selection pads may be disposed adjacent to two adjoining corners of four corners when each semiconductor chip has the shape of a quadrangular plate.
  • The through-electrodes may be disposed in a symmetrical matrix shaped pattern on each semiconductor chip.
  • The through-electrodes may have a shape possessing a sectional area gradually decreasing from one ends thereof, on which the chip selection pads are formed, to the other ends thereof, which face away from the one ends.
  • The chip selection pad may have a first sectional area, and the through-electrode may have a second sectional area that is greater than the first sectional area.
  • The respective chip selection pads and the respective connection pads corresponding to the chip selection pads may be separated by the same distance.
  • The connection members may comprise bonding wires.
  • The stack package may further comprise additional through-electrodes passing through the chip selection pads; and extensions extending from the connection pads corresponding to the additional through-electrodes to portions facing the additional through-electrodes such that the additional-through electrodes and the connection pads can be electrically connected with each other by the connection members.
  • The connection members may comprise conductive members which have a spherical shape or a column shape.
  • In another embodiment of the present invention, a method for manufacturing a stack package comprises the steps of preparing semiconductor chips, each semiconductor chip possessing an upper surface and a lower surface facing away from the upper surface and having at least one chip selection pad which is disposed adjacent to at least one corner of corners of the semiconductor chip and through-electrodes which pass through the upper surface and the lower surface; forming a semiconductor chip module by stacking at least two semiconductor chips such that chip selection pads of the semiconductor chips are exposed and through-electrodes of the semiconductor chips are electrically connected with each other; and mounting the semiconductor chip module onto a substrate which has connection pads.
  • The step of mounting the semiconductor chip module onto the substrate may comprise the step of bonding the respective chip selection pads of the respective stacked semiconductor chips and the connection pads of the substrate, corresponding to the chip selection pads, by means of conductive wires.
  • The step of preparing the semiconductor chips may further comprise the step of forming additional through-electrodes which pass through the chip selection pads; and the step of mounting the semiconductor chip module onto the substrate may comprise the step of electrically connecting the additional through-electrodes with extensions which are formed to extend from the connection pads of the substrate to portions facing the additional through-electrodes, by means of conductive members which has a spherical shape or a column shape.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plan view illustrating a semiconductor chip of a stack package in accordance with an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1.
  • FIG. 3 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • FIG. 4 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention.
  • FIGS. 5 and 6 are a plan view and a cross-sectional view illustrating the stack package in accordance with the embodiment of the present invention.
  • FIG. 7 is a plan view illustrating the stack package in accordance with another embodiment of the present invention.
  • FIG. 8 is a plan view illustrating a stack package in accordance with another embodiment of the present invention.
    •  DESCRIPTION OF SPECIFIC EMBODIMENTS
  • Hereafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
  • It is to be understood herein that the drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly depict certain features of the invention.
  • FIG. 1 is a plan view illustrating a semiconductor chip of a stack package in accordance with an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1.
  • Referring to FIGS. 1 and 2, a semiconductor chip 110 includes a chip selection pad 120 and through-electrodes 130.
  • The semiconductor chip 110 has, for example, the shape of a quadrangular plate. The semiconductor chip 110 has an upper surface 111, a lower surface 112 which faces away from the upper surface 111, and side surfaces 113. The semiconductor chip 110 having the shape of a quadrangular plate possesses four corners. The semiconductor chip 110 has a circuit unit 114 which includes a data storage section (not shown) for storing data and a data processing section (not shown) for processing data.
  • The chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110. The chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 adjacent to any one of the four corners. The chip selection pad 120 is electrically connected with the circuit unit 114. The chip selection pad 120 which is disposed adjacent to the corner on the upper surface 111 of the semiconductor chip 110 has a first sectional area.
  • The through-electrodes 130 pass through the upper surface 111 and the lower surface 112, facing away from the upper surface 111, of the semiconductor chip 110. In the embodiment, the through-electrodes 130 may have a circular or elliptical cross sectional shape when viewed from above. Unlike this, the through-electrodes 130 may have a curved sectional shape. Examples of materials which can be used to form the through-electrodes 130 include copper, copper alloy, and aluminum.
  • In the embodiment, one or more through-electrodes 130 can be disposed through the semiconductor chip 110 in the form of a symmetrical matrix shaped pattern. Each through-electrode 130 may have a second sectional area that is greater than the first sectional area of the chip selection pad 120.
  • While it is illustrated and described in the embodiment that the through-electrodes 130 have a column-like shape, unlike this, the through-electrodes 130 may have a shape which has a sectional area gradually decreasing from one ends thereof to the other ends thereof. For example, the through-electrodes 130 may have the shape of a truncated cone.
  • FIG. 3 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention. The semiconductor chip shown in FIG. 3 is substantially the same as the semiconductor chip described above with reference to FIG. 1, except the number and the disposal of chip selection pads. Therefore, repeated description for the same component parts will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • Referring to FIG. 3, a semiconductor chip 110 includes chip selection pads 122 and 124, and through-electrodes 130.
  • In the embodiment, the chip selection pads 122 and 124 include a first chip selection pad 122 and a second chip selection pad 124. For example, the first chip selection pad 122 is disposed adjacent to the upper left corner in FIG. 3, and the second chip selection pad 124 is disposed adjacent to the lower right corner in FIG. 3, which is positioned in a diagonal direction with respect to the first chip selection pad 122. Unlike this, it can be envisaged that the first chip selection pad 122 is disposed adjacent to the upper right corner in FIG. 3, and the second chip selection pad 124 is disposed adjacent to the lower left corner in FIG. 3, which is positioned in a diagonal direction with respect to the first chip selection pad 122.
  • FIG. 4 is a plan view illustrating a semiconductor chip of a stack package in accordance with another embodiment of the present invention. The semiconductor chip shown in FIG. 4 is substantially the same as the semiconductor chip described above with reference to FIG. 1, except the number and the disposal of chip selection pads. Therefore, repeated description for the same component parts will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • Referring to FIG. 4, a semiconductor chip 110 includes chip selection pads 122 and 124 and through-electrodes 130.
  • In the embodiment, the chip selection pads 122 and 124 include a first chip selection pad 122 and a second chip selection pad 124 which are respectively disposed adjacent to two adjoining corners. For example, the first chip selection pad 122 is disposed adjacent to the upper left corner in FIG. 4, and the second chip selection pad 124 is disposed adjacent to the lower left corner in FIG. 4, which adjoins the first chip selection pad 122. Unlike this, it can be envisaged that the second chip selection pad 124 can be disposed adjacent to the upper right corner in FIG. 4.
  • FIGS. 5 and 6 are a plan view and a cross-sectional view illustrating the stack package in accordance with the embodiment of the present invention.
  • Referring to FIGS. 5 and 6, a stack package 500 includes a semiconductor chip module 140, a substrate 150, and connection members 160.
  • The semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110. Each of the stacked semiconductor chips 110 includes a chip selection pad 120 and through-electrodes 130.
  • The chip selection pad 120 is disposed adjacent to any one of corners on the upper surface of each semiconductor chip 110. The respective semiconductor chips 110 are stacked in such a manner that the chip selection pads 120 are exposed. The through-electrodes 130 which pass through the respective semiconductor chips 110 are electrically connected with one another.
  • In the embodiment, in order to ensure that the chip selection pads 120 are exposed from the four stacked semiconductor chips 110, the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110. Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • The semiconductor chip module 140, which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the chip selection pads 120 exposed from the respective semiconductor chips 110, is mounted to the upper surface of the substrate 150.
  • Connection pads 152 are formed on the upper surface of the substrate 150. In the embodiment, the connection pads 152 are disposed on the upper surface of the substrate 150, for example, in a number corresponding to the number of the chip selection pads 120. In the embodiment, it is preferred that the chip selection pads 120 and the connection pads 152 respectively corresponding to the chip selection pads 120 be separated by the same distance. In the embodiment, the connection pads 152 can be disposed on the substrate 150, for example, in the form of a symmetrical matrix shaped pattern.
  • The connection members 160 electrically connect the chip selection pads 120 disposed on the respective semiconductor chips 110 and the connection pads 152 of the substrate 150. In the embodiment, the connection members 160 may comprise, for example, bonding wires.
  • FIG. 7 is a plan view illustrating the stack package in accordance with another embodiment of the present invention. Repeated description for the same component parts as those shown in FIG. 5 will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • Referring to FIG. 7, a semiconductor package 700 includes a semiconductor chip module 140, a substrate 150, and connection members 160.
  • The semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110. Each of the stacked semiconductor chips 110 includes first and second chip selection pads 122 and 124, and through-electrodes 130.
  • The first chip selection pad 122 is disposed adjacent to any one of the corners on the upper surface of each semiconductor chip 110, and the second chip selection pad 124 is disposed adjacent to another corner of the corners on the upper surface of each semiconductor chip 110, which is positioned in a diagonal direction with respect to the first chip selection pad 122.
  • The respective semiconductor chips 110 having the first and second chip selection pads 122 and 124 are stacked in such a manner that the first and second chip selection pads 122 and 124 are exposed. The through-electrodes 130 which pass through the respective semiconductor chips 110 are also electrically connected to one another.
  • In the embodiment, in order to ensure that the first and second chip selection pads 122 and 124 are exposed from the four stacked semiconductor chips 110, the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110. Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • The semiconductor chip module 140, which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the first and second chip selection pads 122 and 124 exposed from the respective semiconductor chips 110, is mounted to the upper surface of the substrate 150. First and second connection pads 154 and 156 are formed on the upper surface of the substrate 150. In the embodiment, the first and second connection pads 154 and 156 are disposed on the upper surface of the substrate 150, for example, adjacent to the first and second chip selection pads 122 and 124.
  • The connection members 160 electrically connect the first and second chip selection pads 122 and 124 disposed on the respective semiconductor chips 110 and the first and second connection pads 154 and 156 of the substrate 150. In the embodiment, the connection members 160 may comprise, for example, bonding wires.
  • While it was described above that one or two chip selection pads are formed adjacent to one or two corners of each semiconductor chip 110, unlike this, it can be envisaged that chip selection pads can be formed adjacent to respective corners on the upper surface of each semiconductor chip 110 and through this, an increased number of semiconductor chips 110 can be stacked on the substrate 150.
  • FIG. 8 is a plan view illustrating a stack package in accordance with another embodiment of the present invention. The stack package shown in FIG. 8 is substantially the same as the stack package described above with reference to FIG. 5, except additional through-electrodes of semiconductor chips, connection pads and connection members. Therefore, repeated description for the same component parts as those shown in FIG. 5 will be omitted herein, and the same technical terms and the same reference numerals will be used to refer to the same component parts.
  • Referring to FIG. 8, a stack package 800 includes a semiconductor chip module 140, a substrate 150, and connection members 170.
  • The semiconductor chip module 140 includes at least two, for example, four, stacked semiconductor chips 110. Each of the stacked semiconductor chips 110 includes a chip selection pad 120, through-electrodes 130, and an additional through-electrode 125.
  • The chip selection pad 120 is disposed adjacent to any one of corners on the upper surface of each semiconductor chip 110. The respective semiconductor chips 110 are stacked in such a manner that the chip selection pads 120 are exposed. The through-electrodes 130 pass through the respective semiconductor chips 110 and are electrically connected with one another. The additional through-electrode 125 passes through the chip selection pad 120 and a portion of each semiconductor chip 110 which corresponds to the chip selection pad 120.
  • In the embodiment, in order to ensure that the chip selection pads 120 are exposed from the four stacked semiconductor chips 110, the respective semiconductor chips 110 are sequentially rotated by predetermined angles about the rotation centers of the respective semiconductor chips 110. Due to this fact, the stacked semiconductor chips 110 are disposed in such a way as to define the substantial shape of a spiral staircase when viewed from the top.
  • The semiconductor chip module 140, which has the semiconductor chips 110 disposed in the substantial shape of a spiral staircase and the chip selection pads 120 exposed from the respective semiconductor chips 110, is mounted to the upper surface of the substrate 150.
  • Connection pads 152 are formed on the upper surface of the substrate 150. In the embodiment, the connection pads 152 are disposed on the upper surface of the substrate 150, for example, in a number corresponding to the number of the chip selection pads 120.
  • The respective connection pads 152 have extensions 158 which extend to portions facing the additional through-electrodes 125 of the respective chip selection pads 120.
  • The connection members 170 are interposed between the additional through-electrodes 125 disposed in respective semiconductor chips 110 and the extensions 158 facing the additional through-electrodes 125. The additional through-electrodes 125 and the connection pads 152 are electrically connected with each other by the connection members 170. In the embodiment, the connection members 170 may be conductive members having, for example, a spherical shape or a column shape.
  • While, not shown in a drawing, the additional through-electrodes 125 may be formed to pass through the portion of the semiconductor chips 110 which are away from the chip selection pads 120. This case, the connection members 170 may be a conductive pattern, that is, re-distribution layer formed on the upper surface 111 of the semiconductor chips 110 to connect between the chip selection pad and the additional through-electrode 125.
  • Hereinafter, a method for manufacturing a stack package in accordance with another embodiment of the present invention will be described with reference to the attached drawings.
  • First, referring to FIGS. 1 and 2, the semiconductor chip 110 including the chip selection pad 120 and the through-electrodes 130 is manufactured through a semiconductor chip manufacturing process and a through-electrode forming process well known in the art.
  • The semiconductor chip 110 has the shape of a quadrangular plate. The semiconductor chip 110 has the circuit unit 114 which includes a data storage section (not shown) for storing data and a data processing section (not shown) for processing data.
  • The chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110. The chip selection pad 120 is disposed on the upper surface 111 of the semiconductor chip 110 adjacent to any one of the four corners. The chip selection pad 120 is electrically connected with the circuit unit 114.
  • The through-electrodes 130 pass through the upper surface 111 and the lower surface 112, facing away from the upper surface 111, of the semiconductor chip 110. In the embodiment, the through-electrodes 130 may be formed to have a circular or elliptical cross sectional shape when viewed from above. Unlike this, the through-electrodes 130 may be formed to have a curved sectional shape. Examples of a material which can be used to form the through-electrodes 130 include copper, a copper alloy, and aluminum.
  • After the semiconductor chip 110 including the chip selection pad 120 and the through-electrodes 130 is manufactured, as shown in FIG. 5, at least two, for example, four, semiconductor chips 110 are stacked in the shape of a spiral staircase in such a manner that chip selection pads 120 are exposed and the through-electrodes 130 are electrically connected with one another. In this way, the semiconductor chip module 140 is prepared.
  • After the semiconductor chip module 140 is prepared, the semiconductor chip module 140 is mounted onto the substrate 150 which is formed with the connection pads 152.
  • After the semiconductor chip module 140 is mounted onto the substrate 150, the chip selection pads 120 of the respective semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the connection members 160 such as conductive wires, by which the stack package 500 is manufactured.
  • It was illustrated and described in the embodiment that the chip selection pads 120 of the semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the conductive wires. However, as shown in FIG. 8, it can be contemplated that the additional through-electrodes 125 are formed in the semiconductor chips 110 to pass through the chip selection pads 120, the extensions 156 are formed on the substrate 150 to extend from the connection pads 152 to the positions of the additional through-electrodes 125, and the connection members 160 are interposed between the additional through-electrodes 125 and the extensions 156 such that the chip selection pads 120 of the semiconductor chips 110 and the connection pads 152 of the substrate 150 are electrically connected with each other by means of the additional through-electrodes 125 and the extensions 156.
  • As is apparent from the above description, the stack package according to the present invention provides advantages in that, in the state in which a plurality of semiconductor chips are stacked, a certain semiconductor chip can be easily selected among the stacked semiconductor chips.
  • Although specific embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.

Claims (3)

1. A method for manufacturing a stack package, comprising the steps of:
preparing semiconductor chips, each semiconductor chip having an upper surface and a lower surface facing away from the upper surface and having at least one chip selection pad disposed adjacent to at least one corner of each corresponding semiconductor chip and having through-electrodes which pass through the upper surface and the lower surface of each corresponding semiconductor chip;
forming a semiconductor chip module by stacking at least two semiconductor chips together such that chip selection pads of the semiconductor chips are exposed and so that the through-electrodes of the stacked semiconductor chips are electrically connected respectively to each other; and
mounting the semiconductor chip module onto a substrate which has connection pads.
2. The method according to claim 1, wherein the step of mounting the semiconductor chip module onto the substrate comprises the step of:
bonding together, using conductive wires, chip selection pads of the stacked semiconductor chips to respective connection pads of the substrate.
3. The method according to claim 1,
wherein the step of preparing the semiconductor chips further comprises the step of:
forming additional through-electrodes which pass through the chip selection pads; and
wherein the step of mounting the semiconductor chip module onto the substrate comprises the step of:
electrically connecting together, using conductive members, the additional through-electrodes to extensions which extend from the connection pads of the substrate to portions facing the additional through-electrodes, in which of the conductive members have spherical or column shapes.
US13/633,425 2009-11-09 2012-10-02 Spiral staircase shaped stacked semiconductor package and method for manufacturing the same Abandoned US20130040425A1 (en)

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KR1020090107588A KR20110050964A (en) 2009-11-09 2009-11-09 Semiconductor package and method of the same
US12/819,279 US8304879B2 (en) 2009-11-09 2010-06-21 Spiral staircase shaped stacked semiconductor package and method for manufacturing the same
US13/633,425 US20130040425A1 (en) 2009-11-09 2012-10-02 Spiral staircase shaped stacked semiconductor package and method for manufacturing the same

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JP5979565B2 (en) * 2012-04-11 2016-08-24 パナソニックＩｐマネジメント株式会社 Semiconductor device
WO2018106266A1 (en) * 2016-12-11 2018-06-14 Intel Corporation Microelectronic die stack having at least one rotated microelectronic die
KR102534734B1 (en) * 2018-09-03 2023-05-19 삼성전자 주식회사 Semiconductor package
CN112768443B (en) * 2021-04-08 2021-06-25 甬矽电子(宁波)股份有限公司 Multilayer stack packaging structure and preparation method thereof

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US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US7183643B2 (en) * 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7989940B2 (en) * 2003-12-19 2011-08-02 Tessera, Inc. System and method for increasing the number of IO-s on a ball grid package by wire bond stacking of same size packages through apertures
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US8304879B2 (en) 2012-11-06
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