CN102760665B - 无基板半导体封装结构及其制造方法 - Google Patents

无基板半导体封装结构及其制造方法 Download PDF

Info

Publication number
CN102760665B
CN102760665B CN201110158996.5A CN201110158996A CN102760665B CN 102760665 B CN102760665 B CN 102760665B CN 201110158996 A CN201110158996 A CN 201110158996A CN 102760665 B CN102760665 B CN 102760665B
Authority
CN
China
Prior art keywords
chip
conductive trace
substrate
electrically connected
encapsulating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110158996.5A
Other languages
English (en)
Other versions
CN102760665A (zh
Inventor
卓恩民
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
ADL Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ADL Engineering Inc filed Critical ADL Engineering Inc
Publication of CN102760665A publication Critical patent/CN102760665A/zh
Application granted granted Critical
Publication of CN102760665B publication Critical patent/CN102760665B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明利用多芯片先堆栈封装再与重新布线层结合，其中下层芯片的主动面朝下直接与重新布线层电性连接，而上层芯片透过设置于下层芯片周围的导电迹线与重新布线层电性连接。

Description

无基板半导体封装结构及其制造方法
技术领域
本发明有关一种半导体封装技术，特别是一种无基板半导体封装结构及其制造方法。
背景技术
于半导体封装工艺中，由于电子产品需求朝向高功能化、讯号传输高速化及电路组件高密度化发展，且电子产品不断强调轻薄短小，使得封装密度随之不断提高，亦不断缩小封装尺寸与改良封装技术。如何于有限的封装空间中容纳数目庞大的电子组件一直是此技术领域相当重要的课题。
发明内容
本发明目的之一是提供一种无基板半导体封装结构及其制造方法，利用多芯片先堆栈封装再与重新布线层结合，其中下层芯片的主动面朝下直接与重新布线层电性连接，而上层芯片透过设置于下层芯片周围的导电迹线与与重新布线层电性连接。
本发明目的之一是提供一种无基板半导体封装结构的制造方法，包括下列步骤：提供一基板；形成一导电迹线于基板上，其中导电迹线环绕于一第一芯片承载区域的周围；设置一第一芯片于基板的第一芯片承载区域上，其中第一芯片的主动面朝下与基板接触；设置一第二芯片于第一芯片的上方并与导电迹线电性连接；形成一封装胶体覆盖第一芯片、第二芯片、导电迹线与基板的上表面；移除基板，其中封装胶体的下表面暴露出导电迹线的下表面与第一芯片的主动面；设置一重新布线层(redistributionlayer)于封装胶体的下表面，其中第一芯片与导电迹线分别与重新布线层直接接触并电性连接；以及设置多个导电焊球于重新布线层的下表面并与重新布线层电性连接。
本发明目的之一是提供一种无基板半导体封装结构，包括：一多芯片堆栈结 构，包含：一第一芯片，主动面朝下设置；一导电迹线，设置于第一芯片周围；一第二芯片，设置于第一芯片的上方并与导电迹线电性连接；以及一封装胶体覆盖第一芯片、第二芯片与导电迹线，并使该多芯片堆栈结构的下表面露出该导电迹线的下表面与该第一芯片的下表面；一重新布线层，设置于该多芯片堆栈结构的下表面，并与该导电迹线的下表面及该第一芯片直接接触并电性连接；以及多个导电焊球，设置于重新布线层的下表面并与重新布线层电性连接。
以下藉由具体实施例配合所附的图式详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1A、图1B、图1C、图1D、图1E、图1F与图1G为本发明实施例的剖面示视图。
图2A与图2B为本发明不同实施例的剖面示视图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H与图3I为本发明实施例的剖面示视图。
图4为本发明不同实施例的剖面示视图。
具体实施方式
其详细说明如下，所述较佳实施例仅做一说明非用以限定本发明。
图1A至图1G为本发明一实施例的无基板半导体封装结构的制造方法的结构剖面示意图。于本实施例中，无基板半导体封装结构的制造方法包括下列步骤。请参考图1A，首先，提供一基板110。之后，如图1B所示，于基板110上形成一导电迹线(conductivetrace)120。此基板110的材质可为绝缘材料。
接续上述说明，此导电迹线120可利用电镀、蚀刻或转印方式所制成。此外，导电迹线120环绕设置于基板110上的一第一芯片承载区域112的周围。接着，请参照图1C，将一第一芯片130设置于基板110的第一芯片承载区域112上。特别的是，第一芯片130的主动面朝下与基板110接触。
接着，请参照图1D，设置一第二芯片132于第一芯片130上方并与导电迹线120电性连接。于本实施例中，第二芯片132的主动面朝上迭置于第一芯片130上并以打线方式利用多条导线(图上未标)与导电迹线120电性连接。第一芯片130与第二芯片132间可利用黏着层(图上未标)加以黏着固定。
请继续参照图1E，形成一封装胶体140覆盖第一芯片130、第二芯片132、导电迹线120以及基板110的上表面。之后，于本实施例中，设置一支撑基材150于封装胶体140的上表面。于图1A至图1I所揭露为使用支撑基材150的实施例。可理解的是，于一实施例中，可省略支撑基材的使用。
接着，移除基板110，如图1F所示。于封装胶体140的下表面暴露出导电迹线120的下表面与第一芯片130的主动面。请参照图1G，设置一重新布线层160(redistributionlayer，RDL)于封装胶体140的下表面。第一芯片130与导电迹线120分别与重新布线层160电性连接。之后，如图1G所示，设置多个导电焊球170于重新布线层160的下表面并与其电性连接。
于不同实施例中，如图2A与图2B所示，第二芯片132可有不同的设置方式，例如可将第二芯片132的主动面朝下并以覆晶(flip-chip)方式与导电迹线120电性连接。其中，第二芯片132可利用一黏着层(图上未标)迭置于第一芯片130上，如图2B所示，或第二芯片132悬空迭置于第一芯片130上方，如图2A所示。第二芯片132可利用导电焊球172或凸块(bump)与导电迹线120电性连接。
请参照图3A，于一实施例中，本发明制造方法更包括提供一载具100用以承载基板110。基板110则设置于载具100上供后续工艺使用，如图3A至图3G所示。此载具100可为一玻璃基板。基板110可为塑料材质或是具可挠性(flexible)的板材，有助于芯片封装完成后的移除作业。
于一实施例中，请参照图3A至图3F，形成导电迹线120包括下列步骤。于本实施例中，采用电镀方式制作导电迹线120。首先，如图3B所示，形成一金属层120'于基板110上。此金属层120'可利用金属气相沉积制作或是此金属层120'可为一金属薄膜并以压合方式设置于基板110上。除单层结构之外，金属层120'亦可为复合膜层。接着，形成一第一图案化光阻层122'于金属层120'上用以定义出导电迹线120的图案。之后，电镀形成导电迹线120于金属层120'上。
于一实施例中，如图3C所示，在电镀形成导电迹线120后，可直接移除第一图案化光阻层122'以及进一步移除于第一芯片承载区域112上的金属层120'至暴露出基板110的上表面。可以理解的是，除导电迹线120下方的金属层120’外，其余金属层120’在不影响电性下可选择性移除至暴露出基板110的上表面。
于另一实施例中，请参照图3D至图3F，在形成导电迹线120后与移除第一图案化光阻层122'前，可进一步于导电迹线120的多个导电接点126'上形成一金属最终表面处理层122。首先，形成一第二图案化光阻层124'于第一图案化光阻层122'与导电迹线120上。第二图案化光阻层124'暴露出导电迹线120的多个导电接点126'且导电接点126'用以让导电迹线120与第二芯片132(如图1E所示)电性连接。
接着，如图3D与图3E所示，于导电迹线120的导电接点126'上形成一金属最终表面处理层122。此金属最终表面处理层122可有助于第二芯片132(如图1E所示)与导电迹线120的电性连接，如图3G所示。继续，同时移除第一图案化光阻层122'与第二图案化光阻层124'。之后，移除于第一芯片承载区域112上的金属层120'至暴露出基板110的上表面。除导电迹线120下方的金属层120’外，其余金属层120’在不影响电性下可选择性移除至暴露出基板110的上表面。移除金属层120’可藉由蚀刻方式，利用金属最终表面处理层122为屏蔽来蚀刻移除基板110的上表面的金属层120’。可以理解的是，移除金属层120’同时亦会移除掉部分导电迹线120，图上并未显示。
继续参照图3G、图3H与图3I，将一第一芯片130设置于基板110的第一芯片承载区域112上。特别的是，第一芯片130的主动面朝下与基板110接触，而导电迹线120环绕设置于基板110上的一第一芯片承载区域112的周围。
接着，设置一第二芯片132于第一芯片130上方并与导电迹线120电性连接。于本实施例中，第二芯片132的主动面朝上迭置于第一芯片130上并以打线方式利用多条导线(图上未标)与导电迹线120电性连接。第一芯片130与第二芯片132间可利用黏着层(图上未标)加以黏着固定。继续，形成一封装胶体140覆盖第一芯片130、第二芯片132、导电迹线120以及基板110的上表面。之后，设置一支撑基材150于封装胶体140的上表面，如图3G所示。
接着，移除载具100与基板110，如图3H所示。于封装胶体140的下表面暴露出导电迹线120的下表面与第一芯片130的主动面。请参照图3I，设置一重新布线层160于封装胶体140的下表面。第一芯片130与导电迹线120分别与重新布线层160电性连接。之后，设置多个导电焊球170于重新布线层160的下表面并与其电性连接。
于上述实施例中，支撑基材150除了可作为移除基板110或载具100时的支撑外，支撑基材150可依需要保留或进行移除。
除了上述说明电镀形成导电迹线的方法外，本发明亦可于基板上形成一金属层后，对金属层进行蚀刻以形成所需的导电迹线，图上未示。类似的，此金属层除可利用金属气相沉积制作外。此金属层亦可为一金属薄膜并以压合方式设置于基板上。
于本发明中，设置于下层芯片周围的导电迹线并不限定为单层结构。如图4所示，导电迹线120亦可为导电层121与导电层123所构成。可理解的是，多层结构的导电迹线120可藉由进行重复类似前述单层结构制作的电镀、化学气相沉积或蚀刻等工艺所达成。
利用上述实施例的制作方法所形成的结构如图1G、图2A、图2B与图3I所示。本发明的无基板半导体封装结构包括：一重新布线层160；一第一芯片130，主动面朝下设置并与重新布线层160电性连接；一导电迹线120，设置于第一芯片130周围并与重新布线层160电性连接；一第二芯片132，设置于第一芯片130的上方并与导电迹线120电性连接，其中第二芯片132的主动面可朝上迭置于第一芯片130上以打线方式与导电迹线120电性连接(如图1G所示)；或是第二芯片132的主动面可朝下以覆晶方式与导电迹线120电性连接(如图2A与图2B所示)；一封装胶体140覆盖第一芯片130、第二芯片132、导电迹线120与重新布线层160的上表面；以及多个导电焊球170，设置于重新布线层160的下表面并与重新布线层160电性连接。
请参照图3I与图4，于本发明中，第一芯片130与第二芯片132的主动面具有多个对外电性接点(图上未标)用以与重新布线层160或导电迹线120电性连接。重新布线层160的上下表面亦有多个电性接点(图上未标)。重新布线层160的上表面的对内电性接点与第一芯片130主动面多个对外电性接点与导电迹线120电性连接，而重新布线层160的下表面的对外电性接点则与供外部导电焊球170电性连接。
于不同实施例中，于第一芯片130与第二芯片132间可设置黏着层(图上未标)固定，如图1G、图2B与图3I所示。于一实施例中，第二芯片132亦可悬空设置于第一芯片130的上方。
于不同实施例中，一支撑基材150可设置于封装胶体140的上方，如图1G与3I。此支撑基材150除了可供半导体封装结构于制作时提供支撑外，亦可用以加强半导体封装结构的结构强度。于一实施例中，若支撑基材150使用的为具有EMI遮蔽效果的材料时。此支撑基材150即可作为半导体封装结构中对EMI的屏障。支撑基材150的结构并不限于平板状覆盖于封装胶体140上。支撑基材150亦可具有图案化设计以获得较佳的EMI屏障效果。于本发明中，是否使用支撑基材可依使用者的需要进行选择。
根据上述说明，本发明的特征在于芯片堆栈前于下层芯片周围制作导电迹线，此导电迹线供上层芯片与重新布线层电性连接用。导电迹线的制作可用多种方式，如直接转印、电镀或蚀刻等。导电迹线除了可为单层结构外亦可为多层结构，可因应上层芯片需要提供不同变化。
综合上述说明，本发明的无基板半导体封装结构及其制造方法，利用多芯片先堆栈封装再与重新布线层结合，其中下层芯片的主动面朝下直接与重新布线层电性连接，而上层芯片透过设置于下层芯片周围的导电迹线与与重新布线层电性连接。
以上所述的实施例仅是为说明本发明的技术思想及特点，其目的在使熟习此项技艺的人士能够了解本发明的内容并据以实施，当不能以之限定本发明的专利范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的专利范围内。

Claims (14)

1.一种无基板半导体封装结构的制造方法，其特征在于，包含下列步骤：
提供一基板；
形成一导电迹线于所述基板上，其中所述导电迹线环绕于一第一芯片承载区域的周围；
设置一第一芯片于所述基板的所述第一芯片承载区域上，其中所述第一芯片的主动面朝下与所述基板接触；
设置一第二芯片于所述第一芯片的上方并与所述导电迹线电性连接；
形成一封装胶体覆盖所述第一芯片、所述第二芯片、所述导电迹线与所述基板的上表面；
移除所述基板，其中所述封装胶体的下表面暴露出所述导电迹线的下表面与所述第一芯片的主动面；
设置一重新布线层于所述封装胶体的下表面，其中所述第一芯片与所述导电迹线分别与所述重新布线层直接接触并电性连接；以及
设置多个导电焊球于所述重新布线层的下表面并与所述重新布线层电性连接。
2.如权利要求1所述的无基板半导体封装结构的制造方法，其特征在于，更包含一载具用以承载所述基板。
3.如权利要求1所述的无基板半导体封装结构的制造方法，其特征在于，形成所述导电迹线的步骤包含：
形成一金属层于所述基板上；
形成一第一图案化光阻层于所述金属层上定义出所述导电迹线的图案；
电镀形成所述导电迹线于所述金属层上；
移除所述第一图案化光阻层；以及
移除所述第一芯片承载区域的所述金属层至暴露出所述基板的上表面。
4.如权利要求3所述的无基板半导体封装结构的制造方法，其特征在于，于移除所述第一图案化光阻层步骤前更包含：
形成一第二图案化光阻层于所述第一图案化光阻层与所述导电迹在线，其中所述第二图案化光阻层暴露出所述导电迹线的多个导电接点且所述多个导电接点用以让所述导电迹线与所述第二芯片电性连接；
形成一金属最终表面处理层于所述导电迹线的所述多个导电接点上；以及
同时移除所述第一图案化光阻层与所述第二图案化光阻层。
5.如权利要求3所述的无基板半导体封装结构的制造方法，其特征在于，所述金属层为一金属薄膜，以压合方式设置于所述基板上。
6.如权利要求1所述的无基板半导体封装结构的制造方法，其特征在于，形成所述导电迹线的步骤包含：
形成一金属层于所述基板上；以及
对所述金属层进行蚀刻以形成所述导电迹线。
7.如权利要求6所述的无基板半导体封装结构的制造方法，其特征在于，所述金属层为一金属薄膜，以压合方式设置于所述基板上。
8.如权利要求1所述的无基板半导体封装结构的制造方法，其特征在于，于移除所述基板步骤前更包含设置一支撑基材于所述封装胶体的上表面。
9.如权利要求1所述的无基板半导体封装结构的制造方法，其特征在于，所述第二芯片的主动面朝上迭置于所述第一芯片上以打线方式与所述导电迹线电性连接；或是所述第二芯片的主动面朝下以覆晶方式与所述导电迹线电性连接。
10.一种无基板半导体封装结构，其特征在于，包含：
一多芯片堆栈结构，包含：
一第一芯片，主动面朝下设置；
一导电迹线，设置于所述第一芯片周围；
一第二芯片，设置于所述第一芯片的上方并与所述导电迹线电性连接；
以及
一封装胶体覆盖所述第一芯片、所述第二芯片与所述导电迹线，并使该多芯片堆栈结构的下表面露出该导电迹线的下表面与该第一芯片的下表面；
一重新布线层，设置于该多芯片堆栈结构的下表面，并与该导电迹线的下表面及该第一芯片直接接触并电性连接；以及
多个导电焊球，设置于所述重新布线层的下表面并与所述重新布线层电性连接。
11.如权利要求10所述的无基板半导体封装结构，其特征在于，一黏着层设置所述第一芯片与所述第二芯片间。
12.如权利要求10所述的无基板半导体封装结构，其特征在于，所述第二芯片的主动面朝上迭置于所述第一芯片上以打线方式与所述导电迹线电性连接；或是所述第二芯片的主动面朝下以覆晶方式与所述导电迹线电性连接。
13.如权利要求10所述的无基板半导体封装结构，其特征在于，一支撑基材设置于所述封装胶体的上表面。
14.如权利要求13所述的无基板半导体封装结构，其特征在于，所述支撑基材的材质为EMI遮蔽材料。
CN201110158996.5A 2011-04-26 2011-05-31 无基板半导体封装结构及其制造方法 Active CN102760665B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100114430A TWI510155B (zh) 2011-04-26 2011-04-26 半導體封裝結構及其製造方法
TW100114430 2011-04-26

Publications (2)

Publication Number Publication Date
CN102760665A CN102760665A (zh) 2012-10-31
CN102760665B true CN102760665B (zh) 2015-12-16

Family

ID=47055069

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110158996.5A Active CN102760665B (zh) 2011-04-26 2011-05-31 无基板半导体封装结构及其制造方法

Country Status (2)

Country Link
CN (1) CN102760665B (zh)
TW (1) TWI510155B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580079B (zh) * 2013-12-26 2017-04-21 新世紀光電股份有限公司 發光二極體封裝結構及發光二極體模組
US9401287B2 (en) * 2014-02-07 2016-07-26 Altera Corporation Methods for packaging integrated circuits
CN106128965A (zh) * 2016-07-27 2016-11-16 桂林电子科技大学 一种无基板封装器件的制作方法
CN110875404A (zh) * 2018-08-30 2020-03-10 芜湖聚飞光电科技有限公司 一种引线框架、支架及其制作方法、发光器件、发光装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2591772Y (zh) * 2002-12-26 2003-12-10 威盛电子股份有限公司 芯片封装结构
CN101315923A (zh) * 2007-06-01 2008-12-03 南茂科技股份有限公司 芯片堆栈封装结构
CN101364586A (zh) * 2007-08-10 2009-02-11 全懋精密科技股份有限公司 封装基板结构及其制作方法
CN101515574A (zh) * 2008-02-18 2009-08-26 旭德科技股份有限公司 芯片封装载板、芯片封装体及其制造方法
CN101958253A (zh) * 2009-07-14 2011-01-26 日月光半导体制造股份有限公司 封装工艺及封装结构

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4319892B2 (ja) * 2003-11-07 2009-08-26 株式会社巴川製紙所 半導体装置製造用接着シート及び半導体装置の製造方法
TWI377662B (en) * 2008-12-24 2012-11-21 Powertech Technology Inc Multiple flip-chip package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2591772Y (zh) * 2002-12-26 2003-12-10 威盛电子股份有限公司 芯片封装结构
CN101315923A (zh) * 2007-06-01 2008-12-03 南茂科技股份有限公司 芯片堆栈封装结构
CN101364586A (zh) * 2007-08-10 2009-02-11 全懋精密科技股份有限公司 封装基板结构及其制作方法
CN101515574A (zh) * 2008-02-18 2009-08-26 旭德科技股份有限公司 芯片封装载板、芯片封装体及其制造方法
CN101958253A (zh) * 2009-07-14 2011-01-26 日月光半导体制造股份有限公司 封装工艺及封装结构

Also Published As

Publication number Publication date
TWI510155B (zh) 2015-11-21
TW201244572A (en) 2012-11-01
CN102760665A (zh) 2012-10-31

Similar Documents

Publication Publication Date Title
US20220375985A1 (en) Electronic device package and fabricating method thereof
CN103681367B (zh) 封装方法和封装器件
CN102386104B (zh) 四边扁平无接脚封装方法
US8222080B2 (en) Fabrication method of package structure
JP2012253392A (ja) モールド再構成ウェハーを利用したスタックパッケージ及びその製造方法
CN102456636B (zh) 嵌入式芯片的封装件的制造方法
TW200919687A (en) Methods and apparatus for EMI shielding in multi-chip modules
CN103943641B (zh) 半导体晶片封装体及其制造方法
US20090278242A1 (en) Stacked type chip package structure
CN203085525U (zh) 可用于堆叠的集成电路
CN102386105B (zh) 四边扁平无接脚封装方法及其制成的结构
CN102760665B (zh) 无基板半导体封装结构及其制造方法
CN103779351B (zh) 三维封装结构及其制造方法
TW200910472A (en) Electronic device wafer level scale packages and fabrication methods thereof
CN101477980B (zh) 具有减小尺寸的堆叠晶片水平封装
CN105489565A (zh) 嵌埋元件的封装结构及其制法
CN102779767B (zh) 半导体封装结构及其制造方法
CN106898625A (zh) 图像传感器芯片的封装结构及封装方法
CN113675101A (zh) 用于芯片封装的方法和芯片颗粒
CN202473869U (zh) 一种柱状凸点封装结构
CN109817530A (zh) 封装组件制造方法
CN102779809B (zh) 晶片封装体及其形成方法
JP2017103447A (ja) 半導体パッケージ基板及びその製造方法
CN105405826A (zh) 一种铜柱凸块封装结构及其制作方法
KR101195462B1 (ko) 반도체 패키지 및 이의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address

Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee after: Quncheng Energy Co.,Ltd.

Address before: Taiwan County, Hsinchu, China Hukou Zhongxing village, Guangfu Road, No. 5, building 65

Patentee before: ADL Engineering Inc.

CP03 Change of name, title or address
TR01 Transfer of patent right

Effective date of registration: 20240115

Address after: No. 8, Lixing 6th Road, Hsinchu City, Science Industrial Park, Hsinchu City, Taiwan, China, China

Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd.

Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee before: Quncheng Energy Co.,Ltd.

TR01 Transfer of patent right