CN103943641B - 半导体晶片封装体及其制造方法 - Google Patents

半导体晶片封装体及其制造方法 Download PDF

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Publication number
CN103943641B
CN103943641B CN201410022765.5A CN201410022765A CN103943641B CN 103943641 B CN103943641 B CN 103943641B CN 201410022765 A CN201410022765 A CN 201410022765A CN 103943641 B CN103943641 B CN 103943641B
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hole
semiconductor wafer
semiconductor chip
conductive layer
insulating barrier
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CN103943641A (zh
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孙唯伦
张恕铭
黄玉龙
何彦仕
刘沧宇
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种半导体晶片封装体及其制造方法。上述半导体晶片封装体包含半导体晶片、多个孔洞、绝缘层、导电层以及封装层，其中，所述孔洞自半导体晶片的下表面朝上表面延伸，包含至少一个第一孔洞以及至少一个第二孔洞，而绝缘层自半导体晶片的下表面朝上表面延伸，部分的绝缘层位于所述孔洞之中。其中，绝缘层覆盖各第一孔洞的全部孔壁但仅覆盖各第二孔洞的一部分孔壁，导电层位于绝缘层之下且填满所述孔洞，而封装层位于导电层之下。本发明具有较小的半导体晶片封装体尺寸且接地贯孔的制作无须以独立的微影蚀刻制程制作，具有更低的制造成本。

Description

半导体晶片封装体及其制造方法
技术领域
本发明是有关于一种封装体及其制造方法，特别是有关于一种半导体晶片封装体及其制造方法。
背景技术
近年来，集成电路元件均已广泛地应用于例如数字相机(digital camera)、数字摄录象机(digital video recorder))和手机(mobile phone)等的消费电子元件和携带型电子元件中。随着上述各种电子元件及携带式电子元件愈来愈普及与轻巧化，使得应用于其中的半导体晶片封装体的尺寸也愈来愈缩小，也因为各种类型的集成电路制程的微小化以及多功能性整合晶片的趋势发展，使半导体晶片封装体内部各元件彼此连结的密度愈来愈高，走线之间越来越紧密，彼此的耦合现象也越趋严重，使得信号在传输时经常会有电磁干扰的问题，是故接地贯孔(ground via)的设置是当前半导体晶片封装为解决上述问题所经常采用的手段之一，然而目前接地贯孔(ground via)的制作多以另开光罩，以其独立的微影蚀刻制程方式制作，使整体半导体晶片封装体的制作成本提高。
发明内容
本发明的一态样是提供半导体晶片封装体，具有较小的半导体晶片封装体尺寸且接地贯孔的制作无须以独立的微影蚀刻制程制作，具有更低的制造成本。
本发明一实施例提供一种半导体晶片封装体，该半导体晶片封装体包含半导体晶片、多个孔洞以及导电层。半导体晶片具有上表面及下表面，且具有设置于上表面的至少一感应元件、以及电性连接于感应元件的至少一连接垫结构。连接垫结构自半导体晶片的上表面朝下表面延伸。孔洞自半导体晶片的下表面朝上表面延伸，包含至少一个第一孔洞以及至少一个第二孔洞。第一孔洞接触连接垫结构且露出连接垫结构的一部分。第二孔洞不接触该连接垫结构。导电层自半导体晶片的下表面朝上表面延伸，部分的导电层位于孔洞之中。其中，位于第一孔洞内的导电层通过连接垫结构电性连接感应元件。
在本发明的一实施方式中，第一孔洞以及第二孔洞自半导体晶片的下表面朝上表面延伸的深度约略相同。
在本发明的一实施方式中，第二孔洞具有不大于15微米的孔径。
在本发明的一实施方式中，感应元件是感光元件。
在本发明的一实施方式中，感光元件的受光表面至封装层的底表面的最短距离不大于100微米。
在本发明的一实施方式中，进一步包含一绝缘层，该绝缘层自半导体晶片的下表面朝上表面延伸，部分的绝缘层位于孔洞之中，其中，绝缘层覆盖各第一孔洞的全部孔壁但仅覆盖各第二孔洞的一部分孔壁。
在本发明的一实施方式中，导电层位于绝缘层下。
在本发明的一实施方式中，半导体晶片的上表面上不具有任何的承载基板。
本发明的另一态样是提供半导体晶片封装体的制造方法，包含：提供基底，基底定义有多个半导体晶片区，半导体晶片区分别形成至少一半导体晶片，半导体晶片具有上表面及下表面，每一半导体晶片形成有设置于上表面的感应元件以及电性连接感应元件的连接垫结构，且基底上具有设置于各半导体晶片的上表面以及感应元件之上的第一粘着层、以及设置于第一粘着层之上的承载基板；于半导体晶片中形成多个孔洞，所述孔洞自半导体晶片的下表面朝上表面延伸，且包含至少一个第一孔洞以及至少一个第二孔洞，第一孔洞接触连接垫结构且露出连接垫结构的一部分，第二孔洞不接触连接垫结构；以及于各半导体晶片的下表面下形成导电层，该导电层自各半导体晶片的下表面朝上表面延伸，部分的导电层位于孔洞之中。其中位于第一孔洞内的导电层通过连接垫结构电性连接感应元件。
在本发明的一实施方式中，于形成导电层的步骤后，进一步包含沿各半导体晶片区之间的多条交界线由各半导体晶片的下表面朝上表面预切割，使各半导体晶片之间具有多条切割道；于各半导体晶片的下表面之下形成至少一外部导电连结，该外部导电连结电性连接导电层；以及沿各切割道切割，移除沿各该切割道的部分的第一粘着层，使各半导体晶片分离，但各半导体晶片仍通过位于各半导体晶片上的第一粘着层附着于承载基板之下。
在本发明的一实施方式中，于沿各切割道切割的步骤后，进一步包含贴附薄膜框载体以连接各半导体晶片的各外部导电连结，并移除位于各半导体晶片上的承载基板，以形成半导体晶片封装体。
在本发明的一实施方式中，第一孔洞以及第二孔洞于同一制程步骤中同时形成。
在本发明的一实施方式中，第一孔洞以及第二孔洞自半导体晶片的下表面朝上表面延伸的深度约略相同。
在本发明的一实施方式中，在移除位于各半导体晶片上的承载基板的步骤后，还包含于各半导体晶片上的第一粘着层之上贴附第二粘着层，再移除薄膜框载体。
在本发明的一实施方式中，第二孔洞具有不大于15微米的一孔径。
在本发明的一实施方式中，形成封装层的步骤包括：以微影蚀刻的方式，使封装层形成对应于导电层的图案。
在本发明的一实施方式中，感应元件是感光元件。
在本发明的一实施方式中，感光元件的受光表面至封装层的底表面的最短距离不大于100微米。
在本发明的一实施方式中，进一步包含于各半导体晶片的下表面下形成一绝缘层，并于绝缘层下形成导电层。
在本发明的一实施方式中，绝缘层自各半导体晶片的下表面朝上表面延伸，部分的绝缘层位于所述孔洞之中，其中，绝缘层完整覆盖第一孔洞的孔壁且绝缘层仅部分覆盖第二孔洞的孔壁。
附图说明
本发明的上述和其他态样、特征及其他优点参照说明书内容并配合附加图式得到更清楚的了解，其中：
图1绘示本发明一实施方式的半导体晶片封装体的俯视图。
图2绘示本发明一实施方式的半导体晶片封装体的剖面图。
图3至8绘示本发明一实施方式的影像感测元件封装体的制造方法的制程阶段剖面示意图。
附图中符号的简单说明如下：
100：半导体晶片封装体 102：半导体晶片
102a：感应元件 102b：连接垫结构
104：孔洞 104a：第一孔洞
104b：第二孔洞 106：绝缘层
108：导电层 110：封装层
112：焊球 114：第一粘着层
116：承载基板 118：切割道
120：薄膜框载体 122：第二粘着层。
具体实施方式
为了使本揭示内容的叙述更加详尽与完备，下文针对了本发明的实施态样与具体实施例提出了说明性的描述；但这并非实施或运用本发明具体实施例的唯一形式。以下所揭露的各实施方式及实施例，在有益的情形下可相互组合或取代，也可在一实施方式或一实施例中附加其他的实施方式或实施例，而无须进一步的记载或说明。
在以下描述中，将详细叙述许多特定细节以使读者能够充分理解以下的实施方式及/或实施例。然而，可在没有所述特定细节的情况下实践本发明的实施方式及/或实施例。在其他情况下，为简化图式，熟知的结构与装置仅示意性地绘示于图中。
图1绘示本发明一实施例的半导体晶片封装体100的俯视图，而图2绘示本发明该实施方式的半导体晶片封装体100沿图1的AA’剖线的剖面图。请同时参照图1以及图2，半导体晶片封装体100包含半导体晶片102、多个孔洞104、绝缘层106、导电层108以及封装层110。
请继续参照图2，半导体晶片102具有至少一感应元件102a以及至少一连接垫结构102b。在本实施例中，感应元件102a位于半导体晶片102的上表面，其中，感应元件102a例如可以是互补式金属氧化物半导体元件(complementary metal-oxide semiconductordevice)或电荷耦合元件(charge-coupled device)等光电感测元件，但不以此为限。此外，半导体晶片102还包含有至少一连接垫结构102b，其电性连接感应元件102a且连接垫结构102b自该半导体晶片102的上表面朝半导体晶片102的下表面延伸。如图2所示，连接垫结构102b可有一部分和感应元件102a同样位于半导体晶片102的上表面，使该部分的连接垫结构102b与感应元件102a之间具有电性连接，另一部分的连接垫结构102b可以是内连线结构(interconnection structure)，由半导体晶片102的上表面朝半导体晶片102的下表面延伸连接至位于半导体晶片102的内部的另一部分的连接垫结构102b，使位于半导体晶片102的上表面的感应元件102a和半导体晶片102内部通过连接垫结构102b而具有电性导通，但不以此方式为限。
请继续参照图2，半导体晶片封装体100包含自上述的半导体晶片102的下表面朝半导体晶片102的上表面延伸的多个孔洞104，其中多个孔洞104包含两种孔洞，即至少一个第一孔洞104a以及至少一个第二孔洞104b，值得注意的是，第一孔洞104a以及第二孔洞104b各自的孔径、于半导体晶片封装体100中的位置、以及其发挥的作用均不相同。明确来说，第一孔洞104a自上述的半导体晶片102的下表面朝半导体晶片102的上表面延伸至接触位于半导体晶片102内部的连接垫结构102b，并且使半导体晶片102内部的连接垫结构102b的一部分露出，换言之，第一孔洞104a直通硅晶穿孔(Through-Silicon Via,TSV)，待后续导电层108填入、半导体晶片封装体100封装完成后，作为半导体晶片102的下表面至半导体晶片102的上表面的感应元件102a的垂直电性导通路径，在本发明的一实施例中，第一孔洞104a的孔径约为60微米。第二孔洞104b亦自上述的半导体晶片102的下表面朝半导体晶片102的上表面延伸，然第二孔洞104b不接触位于半导体晶片102内部的连接垫结构102b，换言之，第二孔洞104b实质上是接地贯孔(ground via)，近来因集成电路制程微小化，使得走线之间越来越紧密，彼此的耦合现象也越趋严重，使得信号在传输时容易产生电磁干扰等影响信号完整性的问题，接地贯孔的设置是当前半导体晶片封装为解决上述问题所经常采用的手段之一，在本发明的一实施例中，第二孔洞104b的孔径约为15微米，而第一孔洞104a以及第二孔洞104b自半导体晶片102的下表面朝上表面延伸的深度约略相同。请继续参照图2，于半导体晶片102的下表面覆盖有一绝缘层106，所使用的材料可以是氧化硅(siliconoxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)或其它合适的绝缘材料，绝缘层106除覆盖半导体晶片102的下表面，尚自半导体晶片102的下表面的多个孔洞104(包含第一孔洞104a以及第二孔洞104b)的开口，朝半导体晶片102的上表面延伸，使部分绝缘层106位于各第一孔洞104a以及各第二孔洞104b与半导体晶片102接触的孔壁上，值得注意的是，绝缘层106完整覆盖于各第一孔洞104a与半导体晶片102接触的孔壁上；而绝缘层106仅覆盖于各第二孔洞104b与半导体晶片102接触的部分孔壁上。在绝缘层106下方具有一导电层108，其所使用的材料例如是铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料，导电层108具有特殊的图案(pattern)，即在上述导电材料沉积后，会再以微影蚀刻的方式案图化，于绝缘层106下方仅留下对应于第一、第二孔洞以及半导体晶片102下表面的金属走线设计等位置上的导电层108，导电层108位于绝缘层106下方且亦自该半导体晶片102的下表面朝上表面延伸，使部分的导电层108位于各第一孔洞104a以及各第二孔洞104b中，并将各第一孔洞104a以及各第二孔洞104b中填满。值得注意的是，位于各第一孔洞104a中的导电层108因接触原来位于半导体晶片102内部的连接垫结构102b的露出部分，故可通过连接垫结构102b电性导通感应元件102a，但又因绝缘层106完整覆盖于各第一孔洞104a与半导体晶片102接触的孔壁上，故位于各第一孔洞104a中的导电层108与半导体晶片102内部之间被绝缘层106完全隔离而无接触；而位于各第二孔洞104b的导电层108则因为绝缘层106仅覆盖于各第二孔洞104b与半导体晶片102接触的一部分孔壁上，故位于各第二孔洞104b的导电层108即可通过接触绝缘层106未覆盖于各第二孔洞104b与半导体晶片102接触的另一部分孔壁上，而与半导体晶片102内部接触形成接地(grounded)，即前述的接地贯孔(ground via)。如图2所示，封装层110形成于导电层108下方，其中，封装层110所使用的材料可以是于半导体晶片封装技术中所常用的绿漆(solder mask)，封装层110具有开口以露出部分导电层108，使露出的部分导电层108和后续形成的焊球112接触而具有电性导通，封装层110可以避免焊球112彼此接触而短路，同时亦具有保护导电层108的功能。在本发明的一实施例中，感应元件102a是感光元件，其中感光元件的受光表面至封装层110的底表面的最短距离不大于100微米。在本发明的一实施例中，封装材料在涂布或沉积形成后，进一步以微影蚀刻的方式将其案图化，使封装层110仅留下对应于第一孔洞周边以及半导体晶片102下表面的金属走线等位置上的封装层110，具体言之，封装层110仅需留下必要的部分而非全面覆盖，如此一来可减少半导体晶片102在后续制程中，因封装层110热变形所可能带来的晶片弯曲(die warpage)现象。最后，至少一焊球112设置于封装层110的下方，并通过前述封装层110的开口接触露出部分的导体层108，使露出的部分导体层108和焊球112接触而具有电性导通，焊球112所使用的材料例如可以是锡(Sn)、或其他适合焊接的导电材料。
图3至图8是制作如图2所示的半导体晶片封装体100的制作方法示意图。
请先参照图3所绘制的局部图，图3示意本发明的一实施例的制作方法的第一步骤，本步骤提供一具有多个半导体晶片102的基底，在基底上贴附一第一粘着层114，在第一粘着层114上贴附一承载基板116，并由各半导体晶片102的下表面朝上表面形成多个孔洞104。详细说明如下：提供一基底，基底例如可以是硅晶圆或其他半导体材料，并于基底上定义多个半导体晶片区，在各半导体晶片区分别形成至少一半导体晶片102，为方便说明，图3所绘制的是基底的局部，即基底具有多个半导体晶片102，各半导体晶片102分别具有一上表面及一下表面，且各半导体晶片102包含感应元件102a以及连接垫结构102b，其中，感应元件102a位于各半导体晶片102的上表面，连接垫结构102b电性连接感应元件102a，且自半导体晶片102的上表面朝下表面延伸。接着，于具有多个半导体晶片102的基底上，形成第一粘着层114，即使得基底上各半导体晶片102的上表面以及位于各半导体晶片102的上表面的各感应元件102a均贴附于第一粘着层114的下方。设置承载基板116于第一粘着层114之上，其中，第一粘着层114的作用是使各半导体晶片102粘着于承载基板116下方，以及保护各半导体晶片102及位于其上表面的各感应元件102a，所使用的材料可以是UV胶带，但不限于此。而承载基板116使各半导体晶片102在后续分割制程中，稳定附着于承载基板116下方而不致移位造成错误切割，并且提供切割制程中必要的承载力。接着，在同一道制程中在各半导体晶片102的下表面朝上表面形成多个孔洞104，其中，多个孔洞104包含至少一个第一孔洞104a以及至少一个第二孔洞104b，形成各第一孔洞104a以及各第二孔洞104b的方式例如可以是微影蚀刻，但不以此为限。值得注意的是，于上述制程中同时形成的各第一孔洞104a以及各第二孔洞104b除两者自该半导体晶片102的下表面朝上表面延伸的深度约略相同之外，第一孔洞104a以及第二孔洞104b于孔径、于半导体晶片封装体100中的位置、以及其发挥的作用均不相同。在本发明的一实施例中，第一孔洞104a的孔径约为60微米，而第二孔洞104b的孔径约为15微米，第二孔洞104b的孔径较第一孔洞104a的孔径为小，同时制作各第一孔洞104以及各第二孔洞104b的方式可以微影蚀刻制程，或是其他可以控制并同时形成不同孔径大小的制程技艺。明确来说，第一孔洞104a自上述的半导体晶片102的下表面朝半导体晶片102的上表面延伸至接触位于半导体晶片102内部的连接垫结构102b，并且使半导体晶片102内部的连接垫结构102b的一部分露出，然而第二孔洞104b不接触位于半导体晶片102内部的连接垫结构102b，换言之，第二孔洞104b实质上是接地贯孔(groundvia)。
请继续参照图4，图4示意本发明的一实施例的制作方法的第二步骤，本步骤形成绝缘层106以及导电层108，其中绝缘层106形成于各半导体晶片102的下表面且自各该半导体晶片102的该下表面朝该上表面延伸，使部分的该绝缘层106形成于各第一孔洞104a于半导体晶片102内部的孔壁上；以及各第二孔洞104b于半导体晶片102内部的孔壁上，形成绝缘层106的方式例如可以是以化学沉积法，沉积例如是氧化硅(silicon oxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)或其它合适的绝缘材料。其中值得注意的是，形成的绝缘层106必须完整覆盖于各第一孔洞104a与半导体晶片102接触的孔壁上；而绝缘层106则必须仅覆盖于各第二孔洞104b与半导体晶片102接触的一部分孔壁上而不可完整覆盖，这是在薄膜沉积制程上有其填洞能力(gap-fill capability)能力的限制，针对不同孔洞的孔洞深度(trench depth)以及孔径(opening)大小，以及两者的比例，即孔洞深宽比(aspect ratio)，一般而言，使薄膜沉积于孔径越小或深宽比越大的孔洞，需使用越高填洞能力的薄膜制程方能成功，此外，各种材料的沉积以及沉积制程参数都可影响薄膜沉积制程的填洞能力。据此，由于第二孔洞104b的孔径较第一孔洞104a的孔径为小，故选择性地使绝缘层106于第一孔洞104a的孔壁完整覆盖，而于第二孔洞104b的孔壁无法完整覆盖是可以达成的合理目标，于本实施例绝缘层106沉积是以适当的绝缘材料搭配沉积制程参数的调整，执行上述的第一孔洞104a与第二孔洞104b之间的填洞选择。接着，在绝缘层106下方形成一导电层108，可利用例如是溅镀(sputtering)、蒸镀(evaporating)、电镀(electroplating)或无电镀(electroless plating)的方式制作，使用的材料例如是铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料，导电材料沉积后，再以微影蚀刻的方式图案化上述导电材料，使导电层108于绝缘层106下方仅留下对应于第一、第二孔洞以及半导体晶片102下表面的金属走线设计等位置上，通过上述图案化导电材料层的步骤，可重新布局(redistributed process)后续形成的影像感测元件封装体的信号传导路线。导电层108位于绝缘层106下方且亦自该半导体晶片102的下表面朝上表面延伸，使部分的导电层108位于各第一孔洞104a以及各第二孔洞104b中，值得注意的是，导电层108将各第一孔洞104a以及各第二孔洞104b填满，例如是利用填洞能力(gap-fill capability)较佳的金属薄膜制程使不同孔径的各第一孔洞104a以及各第二孔洞104b无选择性地全部填满。使得位于各第一孔洞104a中的导电层108与半导体晶片102内部之间被绝缘层106完全隔离而无接触；而位于各第二孔洞104b的导电层110即可通过接触绝缘层106未覆盖于各第二孔洞104b与半导体晶片102接触的另一部分孔壁上，而与半导体晶片102内部接触形成接地(grounded)。
请接着参照图5，图5示意本发明的一实施例的制作方法的第三步骤，本步骤将基底上各半导体晶片102之间预切割以形成各半导体晶片102之间的切割道118，其中，预切割由各半导体晶片102间的下表面朝上表面执行，预切割可采用例如是干式蚀刻(dry-etching)的方式，但不以此为限。接着形成一封装层110于各半导体晶片102的导电层108之下，其中，封装层110所使用的材料可以是绿漆(solder mask)。在本发明的一实施例中，感应元件102a是感光元件，其中感光元件的受光表面至封装层110的底表面的最短距离不大于100微米。在本发明的一实施例中，封装材料在涂布或沉积形成后，进一步以微影蚀刻的方式将其案图化，使封装层110仅留下对应于第一孔洞周边以及半导体晶片102下表面的金属走线等位置上的封装层110，具体言之，封装层110仅需留下必要的部分而非全面覆盖，如此一来可减少半导体晶片102后续因封装层110热变形所可能带来的晶片弯曲(diewarpage)现象。
请接着参照图6，图6示意本发明的一实施例的制作方法的第四步骤，本步骤形成至少一焊球112于各半导体晶片102的封装层110之下且电性连接导电层108，接着沿各半导体晶片102之间的各切割道118切割，移除沿各切割道118上部分的第一粘着层114，使各半导体晶片102分离，但各半导体晶片102仍通过位于各半导体晶片102上的第一粘着层114附着于该承载基板116之下。
请接着参照图7，图7示意本发明的一实施例的制作方法的第五步骤，本步骤贴附一薄膜框载体120连接各半导体晶片102下方的各焊球112，并移除位于各半导体晶片102上的承载基板116。此外，若为了将各半导体晶片102做适当的卷筒以便利运送，可再参照图8所示，于上述移除位于各半导体晶片102上的承载基板118之后，进一步贴附一第二粘着层122于各半导体晶片102上的第一粘着层114之上，再移除连接各半导体晶片102下方的各焊球112的薄膜框载体120，如此便可配合不同卷筒机台所预设的方向，倒转各半导体晶片102适当的卷筒方向，使卷筒运送的方式更有弹性。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (19)

1.一种半导体晶片封装体，其特征在于，包含：
一半导体晶片，具有一上表面及一下表面，且具有设置于该上表面处的至少一感应元件、以及电性连接于该感应元件的至少一连接垫结构；
多个孔洞，所述孔洞自该半导体晶片的该下表面朝该上表面延伸，且包含：
至少一个第一孔洞，该第一孔洞接触该连接垫结构且露出该连接垫结构的一部分；以及
至少一个第二孔洞，该第二孔洞不接触该连接垫结构；
一绝缘层，位于该半导体晶片的该下表面，且部分的该绝缘层位于所述孔洞之中，其中，该绝缘层覆盖各该第一孔洞的全部孔壁但仅覆盖各该第二孔洞的一部分孔壁；以及
一导电层，自该半导体晶片的该下表面朝该上表面延伸，部分的该导电层位于所述孔洞之中，其中，位于该第一孔洞内的该导电层通过该连接垫结构电性连接该感应元件。
2.根据权利要求1所述的半导体晶片封装体，其特征在于，该第一孔洞以及该第二孔洞自该半导体晶片的该下表面朝该上表面延伸的深度相同。
3.根据权利要求1所述的半导体晶片封装体，其特征在于，该第二孔洞具有不大于15微米的一孔径。
4.根据权利要求1所述的半导体晶片封装体，其特征在于，该感应元件是一感光元件。
5.根据权利要求4所述的半导体晶片封装体，其特征在于，进一步包含一封装层，该封装层形成于该导电层之下，该感光元件的一受光表面至该封装层的一底表面的一最短距离不大于100微米。
6.根据权利要求1所述的半导体晶片封装体，其特征在于，进一步包含至少一焊球，该焊球设置于该半导体晶片封装体的该下表面之下，且电性连接该导电层。
7.根据权利要求1所述的半导体晶片封装体，其特征在于，该导电层位于该绝缘层下。
8.根据权利要求1所述的半导体晶片封装体，其特征在于，该半导体晶片的该上表面上不具有任何的承载基板。
9.一种半导体晶片封装体的制造方法，其特征在于，包含：
提供一基底，该基底定义有多个半导体晶片区，所述半导体晶片区分别形成至少一半导体晶片，各该半导体晶片具有一上表面及一下表面，每一该半导体晶片形成有设置于该上表面处的一感应元件以及电性连接该感应元件的一连接垫结构，且该基底上具有设置于各该半导体晶片的该上表面以及该感应元件之上的一第一粘着层、以及设置于该第一粘着层之上的一承载基板；
于该半导体晶片中形成多个孔洞，所述孔洞自该半导体晶片的该下表面朝该上表面延伸，且包含：
至少一个第一孔洞，该第一孔洞接触该连接垫结构且露出该连接垫结构的一部分；以及
至少一个第二孔洞，该第二孔洞不接触该连接垫结构；
于各该半导体晶片的该下表面下形成一绝缘层，部分的该绝缘层位于所述孔洞之中，其中，该绝缘层完整覆盖该第一孔洞的孔壁且该绝缘层仅部分覆盖该第二孔洞的孔壁；以及
于各该半导体晶片的该下表面下形成一导电层，该导电层自各该半导体晶片的该下表面朝该上表面延伸，部分的该导电层位于所述孔洞之中，其中，位于该第一孔洞内的该导电层通过该连接垫结构电性连接该感应元件。
10.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，于形成该导电层的步骤后，进一步包含：
沿各该半导体晶片区之间的多条交界线由各该半导体晶片的该下表面朝该上表面预切割，使各该半导体晶片之间具有多条切割道；
于各该半导体晶片的该下表面之下形成至少一外部导电连结，该外部导电连结电性连接该导电层；以及
沿各该切割道切割，移除沿各该切割道的部分的该第一粘着层，使各该半导体晶片分离，但各该半导体晶片仍通过位于各该半导体晶片上的该第一粘着层附着于该承载基板之下。
11.根据权利要求10所述的半导体晶片封装体的制造方法，其特征在于，于沿各该切割道切割的步骤后，进一步包含：
贴附一薄膜框载体以连接各该半导体晶片的各该外部导电连结，并移除位于各该半导体晶片上的该承载基板，以形成该半导体晶片封装体。
12.根据权利要求11所述的半导体晶片封装体的制造方法，其特征在于，还包含：在该移除位于各该半导体晶片上的该承载基板的步骤后，于各该半导体晶片上的该第一粘着层之上贴附一第二粘着层，再移除该薄膜框载体。
13.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，该第一孔洞以及该第二孔洞于同一制程步骤中同时形成。
14.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，该第一孔洞以及该第二孔洞自该半导体晶片的该下表面朝该上表面延伸的深度相同。
15.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，该第二孔洞具有不大于15微米的一孔径。
16.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，于形成该导电层的步骤后，进一步包含：于各该半导体晶片的该导电层之下形成一封装层，其中该形成一封装层的步骤包括：以微影蚀刻的方式，使该封装层形成对应于该导电层的图案。
17.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，该感应元件是一感光元件。
18.根据权利要求17所述的半导体晶片封装体的制造方法，其特征在于，于形成该导电层的步骤后，进一步包含：于各该半导体晶片的该导电层之下形成一封装层，其中该感光元件的一受光表面至该封装层的一底表面的一最短距离不大于100微米。
19.根据权利要求9所述的半导体晶片封装体的制造方法，其特征在于，该导电层形成在该绝缘层下方。
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