CN107275240A - 一种芯片封装方法及芯片封装结构 - Google Patents

一种芯片封装方法及芯片封装结构 Download PDF

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Publication number
CN107275240A
CN107275240A CN201710536547.7A CN201710536547A CN107275240A CN 107275240 A CN107275240 A CN 107275240A CN 201710536547 A CN201710536547 A CN 201710536547A CN 107275240 A CN107275240 A CN 107275240A
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China
Prior art keywords
chip
level substrate
panel level
layer
packaging method
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CN201710536547.7A
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English (en)
Inventor
曲连杰
邱云
王丹
赵合彬
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201710536547.7A priority Critical patent/CN107275240A/zh
Publication of CN107275240A publication Critical patent/CN107275240A/zh
Priority to US15/951,267 priority patent/US10283376B2/en
Pending legal-status Critical Current

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Abstract

本发明的实施例提供一种芯片封装方法及芯片封装结构，涉及半导体技术领域，可提高封装效率以及产出效率。一种芯片封装方法，包括：将多个晶片固定于第一面板级衬底上，所述晶片包括多个芯片；在所述晶片上形成针对每个所述芯片的重布线层；通过切割形成各独立的所述芯片以及与所述芯片连接的所述重布线层；将所述芯片和与其连接的所述重布线层固定于二面板级衬底上；对所述芯片进行封装，形成封装层。

Description

一种芯片封装方法及芯片封装结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种芯片封装方法及芯片封装结构。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化以及高可靠性方向发展，而集成电路封装直接影响着集成电路、电子模块乃至整机性能，在集成电路晶片逐步缩小、集成度不断提高的情况下，对集成电路封装提出了越来越高的要求。
传统的半导体行业的芯片封装主要包括如下过程：将晶片上的芯片进行切割，分割成各独立的芯片，将合格的芯片重新按规则排布在衬底上，之后进行封装、形成重布线层(Re-Distribution Layers，简称RDLs)和焊球的工艺。
然而由于半导体行业采用的衬底尺寸较小，一般为6寸、8寸、12寸，使得封装后的产出规模受到限制。
发明内容
本发明的实施例提供一种芯片封装方法及芯片封装结构，可提高封装效率以及产出效率。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供一种芯片封装方法，包括：将多个晶片固定于第一面板级衬底上，所述晶片包括多个芯片；在所述晶片上形成针对每个所述芯片的重布线层；通过切割形成各独立的所述芯片以及与所述芯片连接的所述重布线层；将所述芯片和与其连接的所述重布线层固定于二面板级衬底上；对所述芯片进行封装，形成封装层。
可选的，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层靠近所述第二面板级衬底；基于此，对所述芯片进行封装后，所述芯片封装方法还包括：将所述第二面板级衬底去除；使所述封装层固定于第三面板级衬底上，并在所述重布线层一侧形成焊球。
可选的，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层靠近所述第二面板级衬底；基于此，对所述芯片进行封装后，所述芯片封装方法还包括：对所述封装层切割，形成各独立的芯片封装体；针对每个所述芯片封装体，形成焊球。
可选的，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层远离所述第二面板级衬底；基于此，对所述芯片进行封装后，所述芯片封装方法还包括：对所述封装层进行开封，露出所述重布线层与焊球接触的接触部分；形成所述焊球。
优选的，在形成所述重布线层之后，通过切割形成各独立的所述芯片以及与所述芯片连接的所述重布线层之前，所述方法还包括：去除所述第一面板级衬底。
优选的，所述晶片的形状为规则多边形；多个所述晶片无缝排布于所述第一面板级衬底上。
进一步的，所述晶片的形状为矩形或正六边形。
优选的，所述第二面板级衬底为钢化玻璃衬底。
基于上述，优选的，所述第一面板级衬底和所述第二面板级衬底的尺寸相同。
进一步的，在所述封装层固定于第三面板级衬底的情况下，所述第三面板级衬底与所述第一面板级衬底和所述第二面板级衬底的尺寸相同。
另一方面，提供一种芯片封装结构，可通过上述的任一种芯片封装方法制备得到。
本发明实施例提供一种芯片封装方法及芯片封装结构，通过先将多个晶片固定于第一面板级衬底上，可在面板领域的产线进行大面积曝光，从而刻蚀形成针对每个芯片的重布线层，而且可保证重布线层中金属线的精度，之后通过切割得到各独立的芯片以及与芯片连接的重布线层，并将芯片以及与芯片连接的重布线层重新排布于第二面板级衬底上，可实现同时对排布于第二面板级衬底上的芯片的封装。由于整个封装过程都在面板领域的产线进行，因而可实现大规模的封装，提高了封装效率以及产出效率，而且降低了传统半导体行业封装的成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的一种芯片封装方法的流程示意图一；
图2a为本发明提供的将多个晶片固定于第一面板级衬底上的示意图一；
图2b为图2a中AA′向剖视示意图；
图3为形成重布线层后的示意图；
图4为在图3基础上切割后形成各独立的芯片以及与芯片连接的重布线层的示意图；
图5为在图4基础上将芯片和与其连接的重布线层固定于第二面板级衬底上的示意图一；
图6为在图4基础上将芯片和与其连接的重布线层固定于第二面板级衬底上的示意图二；
图7为在图5基础上形成封装层后的示意图；
图8为在图6基础上形成封装层后的示意图；
图9为本发明提供的一种芯片封装方法的流程示意图二；
图10为在图7基础上去除第二面板级衬底后的示意图；
图11为在图10基础上使封装层固定于第三面板级衬底且形成焊球后的示意图；
图12为本发明提供的一种以球栅阵列排布的焊球的俯视示意图；
图13为在图11基础上去除第三面板级衬底后的示意图；
图14为本发明提供的一种芯片封装方法的流程示意图三；
图15为在图8基础上对封装层进行开封后的示意图；
图16为在图15基础上形成焊球后的示意图；
图17为在图16基础上去除第二面板级衬底后的示意图；
图18为本发明提供的将多个晶片固定于第一面板级衬底上的示意图二。
附图标记:
10-第一面板级衬底；20-晶片；201-芯片；301-第一粘胶层；302-第二粘胶层；303-第三粘胶层；40-重布线层；50-第二面板级衬底；60-封装层；70-第三面板级衬底；80-焊球。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种芯片封装方法，如图1所示，包括：
S10、如图2a和图2b所示，将多个晶片20固定于第一面板级衬底10上，晶片20包括多个芯片201。
其中，晶片20可通过第一粘胶层301固定于第一面板级衬底10上。晶片20例如可以为硅晶片。
第一面板级衬底10为面板行业所用的大型衬底，例如1100mm×1300mm的衬底、2200mm×2500mm的衬底等。
芯片201可以包括已经在半导体衬底上制造的半导体器件或集成电路。例如，芯片201可包括包含硅或者其他半导体材料的衬底、位于衬底上的绝缘层、导电部件(包括诸如金属焊盘、插塞、通孔或者导线)以及位于导电部件上方的接触焊盘。
S11、如图3所示，在晶片20上形成针对每个芯片201的重布线层(Re-DistributionLayers，简称RDLs)40。
重布线层40与芯片201上的接触焊盘形成电连接。重布线层40可形成在介电层中，包括铜，铜合金等材质的金属线，具体可通过薄膜沉积，曝光显影，刻蚀等工艺步骤形成。
其中，由于每个晶片20上，芯片201之间是相互独立的，因而，在形成重布线层40时，针对每个芯片201的重布线层40之间也应该是相互独立、绝缘的，具体可通过介质层进行隔离，以保证芯片201之间的绝缘性。
重布线层40，实现对芯片201引线的逐级放大，从而实现芯片201引线的纳米量级到微米量级的转化，当芯片201引脚达到微米量级时，就可以和其他器件精度对接。
S12、如图4所示，通过切割形成各独立的芯片201以及与芯片201连接的重布线层40。
当每个晶片20包括N个芯片201，且第一面板级衬底10上设置了M个晶片20时，通过切割后，可得到M×N个独立的芯片201；其中，M、N为正整数。当然，与每个芯片201连接的重布线层40，也通过切割其周围的介质层而使用于与不同芯片201连接的重布线层40之间分离。
S13、如图5或图6所示，将芯片201和与其连接的重布线层40固定于第二面板级衬底50上。
当通过切割得到M×N个独立的芯片201后，可对每个芯片201进行测试，挑选出合格的芯片201重新排布于第二面板级衬底50上。
其中，与第一面板级衬底10类似，第二面板级衬底50也为面板行业所用的大型衬底。
可通过第二粘胶层302，将芯片201和与其连接的重布线层40固定于第二面板级衬底50上。
需要说明的是，将芯片201和与其连接的重布线层40固定于第二面板级衬底50上时，可以是重布线层40靠近第二面板级衬底50，也可以是芯片201靠近第二面板级衬底50。
S14、如图7或图8所示，对芯片201进行封装，形成封装层60。
封装层60用于保护芯片201。
需要说明的是，本领域技术人员应该明白，在对芯片201封装后，为实现与其他器件的对接，还需形成焊球，在此不再具体说明。
本发明实施例提供一种芯片封装方法，通过先将多个晶片20固定于第一面板级衬底10上，可在面板领域的产线进行大面积曝光，从而刻蚀形成针对每个芯片的重布线层40，而且可保证重布线层40中金属线的精度，之后通过切割得到各独立的芯片201以及与芯片201连接的重布线层40，并将芯片201以及与芯片201连接的重布线层40重新排布于第二面板级衬底50上，可实现同时对排布于第二面板级衬底50上的芯片201的封装。由于整个封装过程都在面板领域的产线进行，因而可实现大规模的封装，提高了封装效率以及产出效率，而且降低了传统半导体行业封装的成本。
实施例一、提供一种芯片封装方法，如图9所示，包括：
S20、如图2a和图2b所示，将多个晶片20固定于第一面板级衬底10上，晶片20包括多个芯片201。
其中，晶片20通过第一粘胶层301固定于第一面板级衬底10上。
S21、如图3所示，在晶片20上形成针对每个芯片201的重布线层40。
S22、如图4所示，通过切割形成各独立的芯片201以及与芯片201连接的重布线层40。
为避免切割时损伤第一面板级衬底10，以重复利用第一面板级衬底10，可在S21之后，在S22之前，先将第一面板级衬底10去除。
其中，可根据第一粘胶层301的材料选择合适的方法，使第一粘结层301与芯片201分离，以去除第一面板级衬底10。
第一粘胶层301的材料例如可以是双面胶，在此情况下，可通过加热使双面胶降低粘性，以实现其与芯片201的分离，以去除第一面板级衬底10。或者，第一粘胶层301的材料例如可以是UV粘合胶，在此情况下，可通过UV光照使UV粘合胶降低粘性，以实现其与芯片201的分离，以去除第一面板级衬底10。
S23、如图5所示，将芯片201和与其连接的重布线层40固定于第二面板级衬底50上，并使重布线层40靠近第二面板级衬底50。
其中，芯片201和与其连接的重布线层40通过第二粘胶层302固定于第二面板级衬底50上。
固定于第二面板级衬底50上的芯片201应为测试后合格的芯片201。
S24、如图7所示，对芯片201进行封装，形成封装层60。
由于环氧树脂模塑料(Epoxy Molding Compound，简称EMC)的密封性较好，塑封容易，因此，封装层60的材料优选为EMC。
其中，EMC是以环氧树脂为基体树脂，以酚醛树脂为固化剂，再加上一些填料，如填充剂、阻燃剂、着色剂、偶联剂等微量组分，在热和固化剂的作用下环氧树脂的环氧基开环与酚醛树脂发生化学反应，产生交联固化作用使之成为热固性塑料。
S25、如图10所示，将第二面板级衬底50去除。
去除第二面板级衬底50的方法，与去除第一面板级衬底10的方法类似，在此不再赘述。
S26、如图11所示，使封装层60固定于第三面板级衬底70上，并在重布线层40一侧形成焊球80。
即，在去除第二面板级衬底50后，将芯片201、重布线层40以及封装层60整体进行翻转，使封装层60面向第三面板级衬底70，而固定于第三面板级衬底70上。
封装层60通过第三粘胶层303固定于第三面板级衬底70上。
其中，如图12所示，焊球80以球栅阵列(Ball Grid Array，简称BGA)方式排列。
焊球80为金属材料，包括锡、铅、铜、银、金、铋等金属或其合金。形成焊球80的方法包括印刷、植球、激光烧结、电镀、化学镀、溅射等方法。
S27、如图13所示，去除第三面板级衬底70。
去除第三面板级衬底70的方法，与去除第一面板级衬底10的方法类似，在此不再赘述。
其中，可在去除第三面板级衬底70之后，对封装层60进行切割，得到各独立的封装后的芯片。也可在先对封装层60进行切割，得到各独立的封装后的芯片，再去除第三面板级衬底70。
本发明实施例通过将多个芯片201和与各芯片201连接的重布线层40固定于第二面板级衬底50上，对多个芯片201同时进行封装，之后，将封装后的多个芯片201固定于第三面板级衬底70，可进行大面积焊球80的制作。
实施例二、提供一种芯片封装方法，与实施例一的不同在于，在S20-S24之后，先对封装层60进行切割，形成各独立的芯片封装体；其中，芯片封装体包括一个芯片201、与该芯片201连接的重布线层40、以及用于封装该芯片201的封装层60。之后，针对每个芯片封装体，形成焊球80。
其中，可通过捡拾机对每个芯片封装体进行焊点焊接，形成焊球80。
实施例三，提供一种芯片封装方法，如图14所示，包括：
S30、如图2a和图2b所示，将多个晶片20固定于第一面板级衬底10上，晶片20包括多个芯片201。
其中，晶片20通过第一粘胶层301固定于第一面板级衬底10上。
S31、如图3所示，在晶片20上形成针对每个芯片201的重布线层40。
S32、如图4所示，通过切割形成各独立的芯片201以及与芯片201连接的重布线层40。
为避免切割时损伤第一面板级衬底10，以重复利用第一面板级衬底10，可在S31之后，在S32之前，先将第一面板级衬底10去除。
其中，可根据第一粘胶层301的材料选择合适的方法，使第一粘结层301与芯片201分离，以去除第一面板级衬底10。
第一粘胶层301的材料例如可以是双面胶，在此情况下，可通过加热使双面胶降低粘性，以实现其与芯片201的分离，以去除第一面板级衬底10。或者，第一粘胶层301的材料例如可以是UV粘合胶，在此情况下，可通过UV光照使UV粘合胶降低粘性，以实现其与芯片201的分离，以去除第一面板级衬底10。
S33、如图6所示，将芯片201和与其连接的重布线层40固定于第二面板级衬底50上，并使重布线层40远离第二面板级衬底50。
其中，芯片201和与其连接的重布线层40通过第二粘胶层302固定于第二面板级衬底50上。
固定于第二面板级衬底50上的芯片201应为测试后合格的芯片201。
S34、如图8所示，对芯片201进行封装，形成封装层60。
封装层60的材料优选为EMC。
S35、如图15所示，对封装层60进行开封，露出重布线层40与焊球80接触的接触部分。
S36、如图16所示，形成焊球80。
S37、如图17所示，将第二面板级衬底50去除。
去除第二面板级衬底50的方法，与去除第一面板级衬底10的方法类似，在此不再赘述。
其中，可在去除第二面板级衬底50之后，对封装层60进行切割，得到各独立的封装后的芯片。也可在先对封装层60进行切割，得到各独立的封装后的芯片，再去除第二面板级衬底50。
在上述基础上，优选的，晶片20的形状为规则多边形；多个晶片20无缝排布于第一面板级衬底10上。
这样，在第一面板级衬底10上可尽量多的放置晶片20，以提高第一面板级衬底10的利用率，从而进一步的提高产出效率。
进一步优选的，如图18所示，晶片20的形状为矩形或正六边形。这样可进一步提高第一面板级衬底10的利用率。
优选的，第二面板级衬底50为钢化玻璃衬底。
由于封装层60的应力非常大，而钢化玻璃的抗弯曲性，抗冲击性和多层工艺的耐受性较强，因此，采用钢化玻璃衬底作为第二面板级衬底50，可避免第二面板级衬底50由于无法承受较大的应力而导致弯曲甚至破裂的问题。
优选的，第一面板级衬底10和第二面板级衬底50的尺寸相同。
进一步的，第三面板级衬底70与第一面板级衬底10和第二面板级衬底50的尺寸相同。
这样，在实际工艺过程中，可进行共用，从而降低成本。
本发明实施例还提供一种芯片封装结构(如图13和图17所示)，可通过上述任一种的芯片封装方法制备得到。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

1.一种芯片封装方法，其特征在于，包括：
将多个晶片固定于第一面板级衬底上，所述晶片包括多个芯片；
在所述晶片上形成针对每个所述芯片的重布线层；
通过切割形成各独立的所述芯片以及与所述芯片连接的所述重布线层；
将所述芯片和与其连接的所述重布线层固定于第二面板级衬底上；
对所述芯片进行封装，形成封装层。
2.根据权利要求1所述的芯片封装方法，其特征在于，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层靠近所述第二面板级衬底；
对所述芯片进行封装后，所述芯片封装方法还包括：
将所述第二面板级衬底去除；
使所述封装层固定于第三面板级衬底上，并在所述重布线层一侧形成焊球。
3.根据权利要求1所述的芯片封装方法，其特征在于，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层靠近所述第二面板级衬底；
对所述芯片进行封装后，所述芯片封装方法还包括：
对所述封装层切割，形成各独立的芯片封装体；
针对每个所述芯片封装体，形成焊球。
4.根据权利要求1所述的芯片封装方法，其特征在于，所述芯片和与其连接的所述重布线层固定于所述第二面板级衬底上时，所述重布线层远离所述第二面板级衬底；
对所述芯片进行封装后，所述芯片封装方法还包括：
对所述封装层进行开封，露出所述重布线层与焊球接触的接触部分；
形成所述焊球。
5.根据权利要求1所述的芯片封装方法，其特征在于，在形成所述重布线层之后，通过切割形成各独立的所述芯片以及与所述芯片连接的所述重布线层之前，所述方法还包括：
去除所述第一面板级衬底。
6.根据权利要求1所述的芯片封装方法，其特征在于，所述晶片的形状为规则多边形；
多个所述晶片无缝排布于所述第一面板级衬底上。
7.根据权利要求6所述的芯片封装方法，其特征在于，所述晶片的形状为矩形或正六边形。
8.根据权利要求1所述的芯片封装方法，其特征在于，所述第二面板级衬底为钢化玻璃衬底。
9.根据权利要求1-8任一项所述的芯片封装方法，其特征在于，所述第一面板级衬底和所述第二面板级衬底的尺寸相同。
10.根据权利要求9所述的芯片封装方法，其特征在于，在所述封装层固定于第三面板级衬底的情况下，所述第三面板级衬底与所述第一面板级衬底和所述第二面板级衬底的尺寸相同。
11.一种芯片封装结构，其特征在于，通过权利要求1-10任一项所述的芯片封装方法制备得到。
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