TWI578490B - 製造堆疊封裝式半導體封裝的方法 - Google Patents

製造堆疊封裝式半導體封裝的方法 Download PDF

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TWI578490B
TWI578490B TW104126969A TW104126969A TWI578490B TW I578490 B TWI578490 B TW I578490B TW 104126969 A TW104126969 A TW 104126969A TW 104126969 A TW104126969 A TW 104126969A TW I578490 B TWI578490 B TW I578490B
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individual
package
package substrate
semiconductor die
semiconductor
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TW104126969A
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TW201608695A (zh
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金東進
金錦漢
茶水旺
李吉弘
金俊東
高永範
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艾馬克科技公司
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Description

製造堆疊封裝式半導體封裝的方法
本發明關於製造堆疊封裝式半導體封裝的方法。
目前形成多樣的半導體裝置(舉例而言包括堆疊封裝式封裝)的方法是不適當的，舉例而言導致低產出。透過習用的傳統做法與本案參考圖式而由其餘所列的揭示做比較，則熟於此技藝者將明白此種習用傳統做法的進一步限制和缺點。
本揭示的多樣方面提供製造半導體封裝(舉例而言為堆疊封裝式半導體封裝)的方法。舉非限制性範例來說，本揭示的多樣方面提供製造堆疊封裝式半導體封裝或其部分的高產出方法。
100‧‧‧下半導體封裝
102‧‧‧印刷電路板
104‧‧‧半導體晶粒(或晶片)
106‧‧‧導電凸塊
108‧‧‧堆疊結構
109‧‧‧互連結構
110‧‧‧包封材料
112‧‧‧貫穿模製通孔
114‧‧‧切鋸線
115‧‧‧第一介電層
116‧‧‧導線
117‧‧‧第二介電層
120‧‧‧單獨板
122‧‧‧堆疊端子
124‧‧‧單離化線
130‧‧‧載體
200‧‧‧插置物
202‧‧‧導電襯墊
204‧‧‧通孔
206‧‧‧焊地
208‧‧‧連接結構
300‧‧‧上半導體封裝
300A~300F‧‧‧製造半導體封裝的方法步驟
302‧‧‧輸入和輸出端子
圖1~2是依據本揭示的多樣方面而顯示範例性堆疊封裝式封裝及其製程的圖解。
圖3是依據本揭示的多樣方面而顯示一系列截面圖的圖解，其示範製造半導體封裝的範例性方法。
圖4是依據本揭示的多樣方面之範例性半導體封裝的截面圖。
圖5是依據本揭示的多樣方面之範例性半導體封裝的截面圖。
以下討論藉由提供範例而呈現了本揭示的多樣方面。此種範例是非限制性的，因此本揭示之多樣方面的範圍不應該必然受限於所提供之範例的任何特殊特徵。於以下討論，「舉例而言」、「例如」、「範例性」等詞是非限制性的，並且一般而言與「舉例來說而無限制」、「舉例而言且無限制」和類似者同義。
如在此所用，「和/或」意謂由「和/或」結合所列的項目當中任一或更多者。舉例來說，「x和/或y」意謂三元素組{(x)、(y)、(x，y)}當中的任一元素。換言之，「x和/或y」意謂「x和y當中一或二者」。舉另一例來說，「x、y和/或z」意謂七元素組{(x)、(y)、(z)、(x，y)、(x，z)、(y，z)、(x，y，z)}當中的任一元素。換言之，「x、y和/或z」意謂「x、y和z當中一或更多者」。
在此所用的辭彙只是為了描述特殊的範例，並且不打算限制本揭示。如在此所用，單數形式打算也包括複數形式，除非上下文明確另有所指。將進一步了解「包括」、「包含」、「含有」、「具有」、「擁有」、「有」和類似的詞當用於本說明書時指定存在了所述的特色、事物、步驟、操作、元素和/或元件，但不排除存在或添加了一或更多個其他的特色、事物、步驟、操作、元素、元件和/或其群組。
將了解雖然第一、第二……等詞可以在此用於描述多樣的元件，但是這些元件不應該受限於這些詞。這些詞只是用來區分某一元件與 另一元件。因此，舉例而言，以下討論的第一元件、第一構件或第一區段或可稱為第二元件、第二元件或第二區段，而不偏離本揭示的教導。類似而言，多樣的空間用語(譬如「上」、「下」、「側」和類似者)可以用於以相對方式來區分某一元件與另一元件。然而，應該了解元件可以採取不同的方式來指向；舉例而言半導體裝置可以轉向側邊，如此則其「頂面」面向水平方向並且其「側面」面向垂直方向，而不偏離本揭示的教導。附帶而言，「在……之上」一詞將在本文件中用於意謂「在……之上」和「直接在……之上」(例如沒有中介層)二者。
於圖式，多樣的尺度(例如層厚度、寬度……)可以為了清楚示範而有所誇大。附帶而言，多樣範例的討論都利用相同的參考數字來指稱相同的元件。
本揭示的多樣方面提供製造半導體裝置封裝(例如所謂的堆疊封裝(package-on-package，PoP)式封裝)的方法和所得的半導體裝置封裝，其可以增加封裝的製造產出。
本揭示一般而言但非專門關於製造堆疊封裝(PoP)式半導體裝置封裝的方法。舉例而言，本揭示的多樣方面關於製造新穎之PoP封裝的方法，其中藉由僅選擇判定為良好的(例如已知良好的)板(例如封裝基板、插置物……)和半導體晶粒(或晶片)而製造下封裝；之後舉例而言，插置物可以形成在上面。於多樣的實施例(舉例而言為利用預先形成之插置物的實施例)，在將插置物併入封裝裡之前，插置物也可以被判定為良好的。
多樣之電子裝置的趨勢(舉例而言譬如減重、迷你化、高速操作、多功能化、高效能)強調用於電子裝置的半導體裝置要有高可靠度。 因此，已經發展了以下所舉幾例之半導體封裝的多樣結構：舉例而言，譬如晶圓級晶片尺度封裝、多晶片堆疊封裝(其中多個晶片或晶粒附接到插置物並且安裝在板上)、堆疊封裝(PoP)式封裝(其中二或更多個封裝安裝在彼此之上而其間有插置物)。
扇入PoP式封裝的範例性封裝組態和製程提供於圖1~2。尤其，圖1~2是依據本揭示的多樣方面而顯示範例性堆疊封裝式封裝及其製程的圖解。封裝舉例而言可以包括扇入式封裝。
首先，為了製造下半導體封裝100，提供了長條形印刷電路板102(或一般而言為印刷電路板陣列)，其中在橫向和/或縱向上等距離的(或間隔的)形成多個半導體封裝製造區域。半導體晶粒104舉例而言可以經由導電凸塊106(或其他導電結構)而堆疊和附接到條狀板102之個別半導體封裝製造區域的中央部分上以能夠做電訊號交換。雖然僅顯示個別的單一晶粒104(或晶片)附接到個別的板102，但是可以附接多個晶粒和/或被動電構件。
其次，堆疊結構108(例如導電球、導電柱、導電凸塊、用於提供對堆疊構件之電連接的一般互連結構……)熔接到導電圖案，其形成於每個半導體晶粒104(或一群電子裝置)的周邊區域，該區域在此也可以稱為條狀板102的邊框區域。堆疊結構108舉例而言可以作為用於與插置物200電連接的手段。
然後，可以實施在板102的上表面上包封或形成包封材料110(例如模製一種模製化合物樹脂)的步驟，以包封半導體晶粒104和堆疊結構108，舉例而言以保護之。為了提升每個半導體晶粒104所產生的熱向 外輻射，包封材料110的上表面和半導體晶粒104的上表面可以界定相同的平面，使得半導體晶粒104的上表面從包封材料110向外暴露。
在包封之後，可以經由雷射處理或其他燒蝕方法而實施形成貫穿模製通孔(through mold via，TMV)112或一般而言為穿過包封材料110之通孔的步驟，該等通孔在包封材料110的上表面中具有預定的深度。舉例而言，可以決定貫穿模製通孔112的深度以顯露堆疊結構108。
其次，實施將插置物200導電堆疊在如上所述製造之下半導體封裝100的貫穿模製通孔112上的步驟。
插置物200舉例而言可以是一般的印刷電路板(printed circuit board，PCB)，或者其所具有之結構中的電路接線(舉例而言譬如再接線)可以形成在相同於半導體晶粒之矽材料上。舉例而言，利用製造線後端晶圓製程而可以完全或部分形成插置物200。插置物200舉例而言可以作為將下半導體封裝100和上半導體封裝300彼此導電連接的介質。尤其，圖1~2所示的範例性插置物200所包括的結構中之再接線形成在所要的方向，以在所要的位置形成導電襯墊202而連接上半導體封裝300。
舉例而言，插置物200可以建構的方式使得要連接到上半導體封裝300的輸入和輸出端子302(例如經由導電互連結構來為之，其舉例而言為導電球、引線、導電凸塊、柱……)的導電襯墊202從插置物200的上表面暴露出來，並且經由通孔204和/或再接線(未示範)而連接到導電襯墊202的焊地206(例如球焊地或用於耦合到任何各式各樣之互連結構的焊地)形成在插置物200的下表面。
連接結構208(例如導電球、導電凸塊、導電柱……)熔接到 插置物200的焊地206。隨著連接結構208堆疊和熔接到下半導體封裝100之貫穿模製通孔112中的堆疊結構108上，便完成了插置物200相對於下半導體封裝100的電連接和堆疊。
其次，隨著上半導體封裝300的輸入和輸出端子302熔接到插置物200的導電襯墊202上，便完成了上半導體封裝300的堆疊。
於替代性範例，不是將上半導體封裝300堆疊在插置物200的導電襯墊202上，而是多個半導體晶粒(或晶片)可以堆疊和附接到導電襯墊202上。
其次，在要連接到例如電子器件(或裝置)之主機板的互連結構109(例如導電球、焊球、導電柱、導電凸塊……)熔接到暴露在下半導體封裝100的板102之下表面的個別焊地之後，板102和插置物200接受沿著切鋸線114或在其間的切鋸，而完成了單獨的PoP式封裝，其範例示範於圖2。
如圖1~2所示的扇入PoP式封裝和/或其製造方法舉例而言可以包括多樣的改善機會。舉例而言，預先形成的條狀板可能包括有缺陷的單獨板。舉例而言，即使標註了條狀板之有缺陷的單獨板並且不利用之，它們在製程期間仍消耗有價值的地產並且可以接受多樣的大量製程(例如大量模製)，因此浪費資源。
據此，本揭示的多樣方面提供製造半導體裝置封裝(例如PoP式封裝)之可靠且有效率的方法和/或藉此所製造的封裝。範例性方法舉例而言可以包括：選擇單獨良好品質的板(或其他基板)，舉例而言藉由檢視來為之；將單獨良好品質的板(或在此改稱為已知良好的板)附接到載體；以及 對單獨良好品質的板進行一系列的PoP製程，舉例而言包括晶粒(或晶片)附接過程、包封過程、包封劑薄化過程、插置物形成過程，藉此避免和/或減少PoP封裝的缺陷。
依據本揭示的多樣方面，製造半導體裝置封裝(例如PoP式封裝)的範例性方法可以包括：對包括多個單獨板的條狀板進行缺陷檢視並且從條狀板運用已知良好的板，而僅提供良好品質的單獨板；將已知良好的板以預定的間隔(或規律或一致的間隔)附接到具有預定區域的載體；經由導電結構而將判別為良好品質的(或已知良好的)半導體晶粒附接到每個單獨已知良好的板以能夠做電訊號交換；將堆疊端子附接到每個單獨已知良好的板對應於半導體晶粒之周邊區域的邊框區域；將具有預定厚度的模製化合物樹脂模製(或另外形成包封劑)在載體的上表面上，以包封每個單獨已知良好的板以及已知良好的半導體晶粒和堆疊端子；研磨或另外薄化模製化合物樹脂的上表面，直到暴露出堆疊端子的上表面為止；在模製化合物樹脂的上表面上形成插置物，該插置物導電連接到堆疊端子；以及在移除載體之後，將輸入和輸出端子附接到每個單獨板的焊地。
本方法舉例而言可以進一步包括：在將上半導體封裝堆疊在插置物上之後，沿著個別單獨已知良好的板之間的切鋸線進行切鋸。
形成插置物舉例而言可以包括：將用於插置物的印刷電路板(PCB)導電連接到堆疊端子，並且將PCB堆疊在模製化合物樹脂的上表面上。也舉例而言，形成插置物可以包括：形成再接線(或導線)，如此以延伸到模製化合物樹脂之上表面上所想要的位置，該再接線導電連接到堆疊端子。
載體舉例而言可以使用可再使用的玻璃或矽而形成預定的厚度。也舉例而言，堆疊端子可以包括焊球或銅釘栓凸塊。
現在轉到圖3，此種圖是顯示一系列截面圖的圖解，其依據本揭示的多樣方面而示範製造半導體封裝的範例性方法。圖3所示的範例性方法(或其任何部分)和/或範例性封裝結構(或其構件)舉例而言可以與圖1~2所示和在此討論的範例性方法和封裝來分享任何或所有的特徵。
首先，可以對條狀板(例如印刷電路板陣列)或其他的基板集合進行缺陷檢視，而不論其連接與否。此種板舉例而言可以利用作為半導體裝置封裝的封裝基板。雖然以下討論大致將基板稱為「板」(board)，但是應該了解本揭示的範圍不限於印刷線路板。舉例而言，本揭示也思及利用任何各式各樣的基板，例如它可以利用作為半導體裝置的封裝基板和/或作為半導體裝置的插置物。同時，雖然以下討論大致將此種板的連接陣列稱為條狀板，但是應該了解本揭示的範圍不限於連接板的陣列。舉例而言，本揭示也思及任何各式各樣的互連基板集合(例如呈方形或矩形的連接陣列、呈晶圓形狀的連接陣列……)和/或在測試之前已經單離化的基板。
缺陷檢視可以採取任何各式各樣的方式來進行，在此提供了其非限制性範例。舉例而言，無論構成條狀板的單獨板分別是良好或有缺陷的，都可以使用譬如習用的視覺系統、電測試系統、X光檢視系統……的測試設備來測試條狀板的電路設計區域而加以判別或判定。
在對條狀板(舉例而言包括用於半導體封裝的單獨板)進行缺陷檢視之後，將條狀板單離化(例如切鋸、沖切、折斷……)成為單獨板，如此則僅提供良好品質的單獨板120給堆疊封裝(PoP)製程。
如截面圖300A所示，具有預定面積的載體130則提供作為用於本揭示之PoP製程的支持件。載體130可以包括任何各式各樣的特徵，在此提供了其非限制性範例。舉例而言，載體130可以包括任何各式各樣的幾何組態(例如方形、矩形、圓形……)和/或厚度。同時，舉例而言，載體130可以包括任何各式各樣的材料(例如玻璃、矽或其他半導體材料、金屬……)，舉例而言，載體130可以由某種材料所形成和操持，使得載體130可以在它與工作產物分開之後(例如在它與完成或幾乎完成的封裝或電構件模組分開之後)再次使用。
黏著劑舉例而言可以施加到載體130。黏著劑舉例而言可以包括任何各式各樣的特徵，在此提供了其非限制性範例。黏著劑舉例而言可以包括雙面膠帶、黏著膏、黏著噴霧……。黏著劑舉例而言可以包括提供了方便移除黏著劑的特徵(例如打斷黏著劑與載體130、板120、包封材料110……之間的結合)，使得載體130在使用之後可以不破壞的與工作產物分開。
已知良好的單獨板120然後可以利用黏著劑而安裝到載體130。舉例而言，可以利用自動拾放設備而將板120放置在黏著劑上的精確位置(例如呈一維陣列、二維陣列……)。安裝了載體的板120舉例而言可以採取規律的間隔來放置，而板120之間沒有多於必需的空間以減少浪費(例如材料浪費、製造時間浪費……)。舉例而言，安裝了載體的板120可以安裝到載體130，使得在完成的封裝之間只有足夠的未使用空間，以允許有用於分開完成或幾乎完成的封裝之單離化裝置(例如切鋸機、沖切機、雷射……)的寬度。
在已知良好的板120安裝到載體之後，將半導體晶粒104(或晶片)和/或其他電構件附接到板120。舉例而言，一或更多個個別的半導體晶粒104可以電和機械附接到每個板120。半導體晶粒104和/或其他電構件舉例而言可以已經預先測試過(例如利用電測試、目視檢測、X光檢視……)，並且判定為良好品質的(在此另稱為「已知良好的」)。半導體晶粒104舉例而言可以利用任何各式各樣的互連結構106(例如導電凸塊、導電柱、晶圓級凸塊、導電球、焊料、環氧樹脂……)而附接到板120以與板120之個別的焊地連接。
舉例來說，在互連結構106舉例而言使用習用的鍍覆過程而整合連接到半導體晶粒104之個別的結合襯墊之後，互連結構106熔接到在個別單獨板120之中央區域的個別暴露之導電圖案(其例如在板120之建構成附接到互連結構106的中央區域或其他區域)。藉此，舉例而言判別為良好品質的半導體晶粒104便導電附接到舉例而言也判別為良好品質的個別單獨板120。
於範例性實施例，在半導體晶粒104做測試之後(其呈晶圓形式和/或從晶圓單離化之後)，半導體晶粒104可以藉由僅選擇判別為良好品質者而加以判定。
於多樣的範例性實施例，堆疊端子122可以形成於每個單獨板120對應於半導體晶粒104之周邊區域的邊框區域，其舉例而言用於導電堆疊上半導體封裝或插置物。堆疊端子122舉例而言可以包括任何各式各樣的特徵。舉例而言、堆疊端子122可以包括導電球、焊球、銅核焊球、金屬釘栓凸塊、銅釘栓凸塊、導線、導電柱、銅柱……。堆疊端子122可 以採取任何各式各樣的方式而形成，在此提供了其非限制性範例。舉例而言，堆疊端子122可以藉由將預先形成的導電結構(例如導電球、焊球、導線……)附接到板120而形成。也舉例而言，堆疊端子122可以累積在板120上(例如藉由鍍覆、印刷、沉積……來為之)。
形成在每個單獨板120上的堆疊端子122可以具有等於或大於半導體晶粒104之上表面的高度。這舉例而言可以彈性的允許堆疊端子122在包封劑薄化過程之後暴露出來，同時允許半導體晶粒104(或其頂面)從包封劑暴露出來或者替代而言被包封劑所覆蓋。
其次，如圖解300B所示，可以進行包封。舉例而言，包封材料110可以形成在載體130、板120、半導體晶粒104和/或堆疊端子122上。包封材料110舉例而言可以包圍板120、半導體晶粒104和/或堆疊端子122之所有或部分的側面。雖然圖3顯示包封材料110形成在堆疊端子122的頂面上和在半導體晶粒104的頂面上，但是任何此種頂面不須要被包封覆蓋(例如利用膜輔助或晶粒密封的模製技術)。
包封可以採取任何各式各樣的方式來進行，在此提供了其非限制性範例。舉例而言，包封可以包括利用壓縮模製(例如利用液體、粉末和/或膜)或真空模製。也舉例而言，包封可以包括利用轉移模製過程(例如晶圓級轉移模製過程)。包封材料舉例而言可以包括任何各式各樣的特徵。舉例而言，例如環氧基模製化合物(epoxy mold compound，EMC)、環氧樹脂模製化合物……的包封材料可以包括比較高的模數，舉例而言以提供在後續過程(舉例而言在移除載體130之後)的結構支持。替代而言，舉例來說，包封材料可以包括比較低的模數，以當晶圓可撓性是有利時在後續過程中 提供此種可撓性。
包封過程舉例而言也可以在半導體晶粒104和板120之間提供底填物。然而，注意此種底填舉例而言也可以利用異於包封過程所用的材料而在包封過程之前進行。於底填是與包封過程分開進行的範例性情境，此種底填可以採取任何各式各樣的方式來進行(例如毛細管底填、在附接半導體晶粒104期間利用預先施加的底填物……)。
如圖解300C所示，在包封之後，包封材料110的上表面可加以薄化(例如若想要暴露堆疊端子122和/或半導體晶粒104在包封期間所覆蓋的頂面)。舉例而言，包封材料110可加以薄化(例如藉由研磨……來為之)以暴露堆疊端子122的上表面。也舉例而言，包封材料110可加以薄化以暴露至少半導體晶粒104的頂面。於堆疊端子122和/或半導體晶粒104已經如所想要的暴露之範例性實施例，則可以略過薄化過程。
舉例而言，於範例性實施例，僅有堆疊端子122的上表面從包封材料110暴露出來(例如提供與上半導體封裝、構件、插置物……做堆疊連接)。替代而言，於另一範例性實施例，堆疊端子122的上表面和半導體晶粒104的上表面從包封材料110暴露出來(例如除了提供堆疊連接以外，還提升來自半導體晶粒104的熱傳)。
此時，便可以完成了下半導體封裝100在載體130上的製造。
在下半導體封裝100形成在載體130上之後，插置物200可以形成在半導體封裝100上(例如在多個半導體封裝100的每一者上)，而導電連接到堆疊端子122。舉例而言，插置物200可以形成在包封材料110的上表面上。
插置物200可以採取任何各式各樣的方式而形成，在此提供了其非限制性範例。舉例而言，於範例性實施例，預先形成的插置物200(例如插置印刷電路板(PCB)、在製造線後端過程從矽晶圓所形成的插置物……)可以堆疊在包封材料110的上表面，並且電連接到堆疊端子(例如藉由焊接、導電黏著附接……來為之)。舉例而言，堆疊端子122可以導電附接(例如焊接、黏結、熔接……)到在預先形成的插置物之下表面的焊地。
於另一範例性實施例，插置物200可以建造在下半導體封裝100上。舉例而言，導線(其在此也可以稱為再接線或再分布線)可以導電連接到堆疊端子122，並且安排成延伸到包封材料110之上表面上所要的位置。
舉例而言，如圖3的圖解300D所示範，形成插置物200可以包括將第一介電層115施加到包封材料110的表面。第一介電層115也可以稱為鈍化層，其可以包括任何各式各樣的材料，在此提供了其非限制性範例。舉例而言，第一介電層115可以包括有機介電材料，例如雙馬來醯亞胺三【口井】(BT)、酚樹脂、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯并【口咢】唑(PBO)、環氧樹脂和其等同者及其化合物……。也舉例而言，第一介電層115可以包括無機介電材料，例如氧化矽、氮化矽……。第一介電層115可以採取任何各式各樣的方式而形成，在此提供了其非限制性範例，舉例而言，第一介電層115可以藉由化學氣相沉積(chemical vapor deposition，CVD)……而形成。注意於半導體晶粒104的頂面從包封材料110暴露出來的情境，第一介電層115可以形成在此種頂面上(例如直接在其上、在中介氧化層上……)。
舉例而言可以移除部分的第一介電層115，以暴露堆疊端子 122的上表面以供後續連接到導線。此種移除可以採取任何各式各樣的方式來進行，舉例而言使用光阻和蝕刻過程。注意於替代性實施例，第一介電層115可以形成為具有孔洞而藉此暴露堆疊端子122。
插置物200的導線116然後可以形成在第一介電層115上並且電連接到堆疊端子122。導線116舉例而言可以側向往內而朝向個別封裝的中央區域(例如在個別的半導體晶粒104上而呈扇入組態)以及/或者往外而朝向個別封裝的周邊(例如呈扇出組態)。導線116可以採取任何各式各樣的方式而形成，在此提供了其非限制性範例。舉例而言，導線116可以藉由濺鍍和/或電鍍而形成。
形成插置物200舉例而言也可以包括在導線116和/或第一介電層115上形成第二介電層117。導線116的末端(舉例而言為遠離導線116在堆疊端子122的末端)可以從第二介電層117暴露出來，其舉例而言作為襯墊位置以供後續連接於頂部封裝的互連結構。第二介電層117也可以在此稱為鈍化層，其可以與第一介電層116分享任何或所有的材料特徵以及/或者可以藉由相同或不同的過程而形成。
如圖解300E所示，載體130然後舉例而言可以從包封材料110和板120的底面移除。此種移除可以採取任何各式各樣的方式而進行，在此提供了其非限制性範例。舉例而言，視載體130和對此黏著的物體(例如板120、包封材料110……)之間的黏著性而定，可以利用任何各式各樣的溫度、化學和/或物理技術來分開載體130與包封材料110和板120。舉例而言，可以利用非破壞性技術以打斷載體130和包封材料110和板120之間的黏結而不損傷載體130，這會允許再次使用載體130。
在載體130與個別單獨板120的下表面和包封材料110的下表面分開之後，互連結構109(例如導電球、焊球、導電柱或樁、導電凸塊……)可以附接到板120之下表面上的焊地。
附帶而言，在上半導體封裝300堆疊在插置物200上之後(或在此種堆疊之前)，所得的結構可以沿著單離化線124或在單離化線124之間加以單離化。舉例而言，此種單離化可以藉由任何各式各樣的技術而進行，例如切鋸、沖切、切割、折斷……。舉例而言，在進行此種單離化之後，單離化之封裝的側面可以包括板120、包封材料110和/或插置物200(例如任何或所有的介電層和/或其導電層)之共平面的側面。
舉例而言，切鋸可以切割穿過包封材料110以及/或者也可以切割穿過一或更多層的插置物200以及/或者也可以切割穿過板120的周緣。板120、包封材料110、插置物200之側面是共平面的範例性組態則顯示在圖4。注意板120在單離化期間不須加以切鋸，舉例而言所導致的結構在單離化之後是板120的側面被包封材料110所覆蓋，並且包封材料110和/或插置物200的側面共平面。包封材料110和插置物200的側面共平面並且板120的側面被包封材料110所覆蓋的範例性組態則顯示在圖3的底部。
圖4和5是截面圖，其示範依據本揭示的多樣方面所製造之半導體裝置封裝的範例性形式(例如PoP式封裝)。圖4和5所示範的範例性半導體裝置封裝可以與在此所示和所討論的其他封裝分享任何或所有的特徵。
舉例而言，如圖4所示範，當堆疊端子122附接到從每個單獨板120對應於半導體晶粒104之周邊區域的邊框區域所暴露出來的導電圖 案時，堆疊端子122可以使用銅釘栓凸塊來附接。
也舉例而言，如圖5所示範，不形成插置物，上半導體封裝300可以改為直接導電堆疊和連接到穿過包封材料110所暴露的堆疊端子122上。舉例而言，當採用一般的球柵陣列半導體封裝作為上半導體封裝300時，隨著附接到上半導體封裝300之下表面的輸入和輸出端子302直接導電連接到堆疊端子122，上半導體封裝300可以堆疊在下半導體封裝100上而無插置物，如在此所討論，依據本揭示的多樣方面，於僅利用良好品質的單獨板(舉例而言如從條狀板所單離化)的實施例，可以使用載體作為支持手段(其舉例來說用於單獨板和晶粒的附接過程)而進行一系列的封裝製程。以此方式，則有可能減少和/或避免產生當條狀板之有缺陷的單獨板用於製造時所造成之有缺陷的封裝。
如從在此的敘述所明白，本揭示的多樣方面提供許多優點。第一，舉例而言，隨著對條狀板進行缺陷檢視而選擇良好品質的單獨板而非有缺陷的板，並且僅有良好品質的單獨板用於封裝製造，則有可能減少和/或消除完成之封裝因為有缺陷的板所具有的缺陷。第二，隨著使用具有預定厚度的載體來支持單獨板而可以成群的(舉例而言像是條狀板)以製造多個封裝，則有可能維持想要的製造產出。第三，由於具有預定厚度的載體支持和穩固的維持個別的單獨板，故有可能減少和/或避免板的彎翹，此彎翹可能發生在一系列的封裝製程，舉例而言譬如對條狀板所進行的晶粒附接和模製過程。
總而言之，本揭示的多樣方面提供製造半導體裝置封裝(舉 例而言為堆疊封裝(PoP)式封裝)的方法。舉非限制性範例來說，本揭示的多樣方面提供增加半導體裝置封裝的製造產出和/或減少其彎翹的方法。雖然前面已經參考特定的方面和範例來描述，不過熟於此技藝者將了解可以做出多樣的改變並且可以用等同者來取代，而不偏離本揭示的範圍。附帶而言，可以做出許多修改以使特殊的狀況或材料適於本揭示的教導，而不偏離其範圍。因此，本揭示不打算受限於揭示之(多個)特殊的範例，本揭示而是將包括落於所附請求項範圍裡的所有範例。
100‧‧‧下半導體封裝
102‧‧‧印刷電路板
104‧‧‧半導體晶粒(或晶片)
106‧‧‧導電凸塊
108‧‧‧堆疊結構
109‧‧‧互連結構
110‧‧‧包封材料
112‧‧‧貫穿模製通孔
114‧‧‧切鋸線
200‧‧‧插置物
202‧‧‧導電襯墊
204‧‧‧通孔
206‧‧‧焊地
208‧‧‧連接結構

Claims (20)

  1. 一種製造半導體封裝的方法，該方法包括：將已知良好的封裝基板陣列附接到載體；將個別已知良好的半導體晶粒附接到該封裝基板陣列之每個封裝基板的個別頂面；形成個別的堆疊端子，其附接到該封裝基板陣列之每個封裝基板的個別周邊區域而在該個別附接之半導體晶粒的佔地區域外面；以包封材料包封該封裝基板陣列、該等半導體晶粒、該等堆疊端子；將該包封材料薄化以暴露該等堆疊端子之每一者的個別上端；在該包封材料的上表面上形成用於該封裝基板陣列之每個封裝基板的個別插置物並且電連接到該個別的堆疊端子；從該載體移除該等包封的封裝基板、半導體晶粒、堆疊端子；以及將個別的互連結構附接到在該個別半導體晶粒的相對側上之該等包封之封裝基板的每一者。
  2. 如申請專利範圍第1項的方法，其包括：在附接該等個別的互連結構之後，將該等包封的封裝基板單離化。
  3. 如申請專利範圍第1項的方法，其中該等封裝基板的每一者包括印刷電路板。
  4. 如申請專利範圍第1項的方法，其中形成該個別的插置物包括：將預先形成的插置物堆疊在該包封材料上，並且將該預先形成的個別插置物電連接到該個別的堆疊端子。
  5. 如申請專利範圍第1項的方法，其中形成該個別的插置物包括：在 該包封材料上形成個別的導線並且電連接到該個別的堆疊端子。
  6. 如申請專利範圍第5項的方法，其中形成該個別的插置物包括：在該個別的導線上形成介電層，其暴露該個別導線直接在該個別半導體晶粒之上的末端。
  7. 如申請專利範圍第1項的方法，其中該載體包括玻璃和矽中之一或更多者。
  8. 如申請專利範圍第1項的方法，其中該個別的堆疊端子包括焊球或銅釘栓凸塊。
  9. 如申請專利範圍第1項的方法，其中薄化該包封材料包括：將該包封材料薄化得足以暴露該等半導體晶粒。
  10. 如申請專利範圍第1項的方法，其中該封裝基板陣列是二維陣列。
  11. 如申請專利範圍第1項的方法，其中該等堆疊端子的個別頂面和該包封材料的頂面共平面。
  12. 如申請專利範圍第1項的方法，其中該等堆疊端子的個別頂面、該包封材料的頂面、該等半導體晶粒的個別頂面共平面。
  13. 一種製造半導體封裝的方法，該方法包括：將已知良好的封裝基板陣列附接到載體，該等封裝基板之每一者的個別底面則附接到該載體的頂面；對於該等封裝基板的每一者：將已知良好的半導體晶粒附接到該封裝基板的頂面；以及將堆疊端子附接到該封裝基板而在該半導體晶粒的周邊外面；以包封材料來包封該封裝基板陣列、該等半導體晶粒、該等堆疊端子； 以及將該包封的封裝結構單離化。
  14. 如申請專利範圍第13項的方法，其包括：在該單離化之前，先在該包封材料的上表面上形成用於該等封裝基板之每一者的個別插置物，該個別的插置物電連接到個別的堆疊端子。
  15. 如申請專利範圍第13項的方法，其中形成個別的插置物包括：直接在個別的半導體晶粒之上形成至少部分的該個別的插置物。
  16. 一種製造半導體封裝的方法，該方法包括：將第一已知良好的封裝基板之底面附接到載體；在側向相鄰於該第一已知良好的封裝之位置，將第二已知良好的封裝基板之底面附接到該載體；將第一半導體晶粒附接到該第一封裝基板的頂面；將第二半導體晶粒附接到該第二封裝基板的頂面；將第一互連結構附接到該第一封裝基板的該頂面而在該第一半導體晶粒的周邊外面；將第二互連結構附接到該第二封裝基板的該頂面而在該第二半導體晶粒的周邊外面；以包封材料來包封該第一封裝基板、該第一半導體晶粒、該第一互連結構、該第二封裝基板、該第二半導體晶粒、該第二互連結構；在該第一半導體晶粒上和在該包封材料上形成第一插置物，該第一插置物電連接到該第一互連結構；在該第二半導體晶粒上和在該包封材料上形成第二插置物，該第二插 置物電連接到該第二互連結構；從該載體移除該等包封的第一封裝基板、第一半導體晶粒、第一互連結構、第二封裝基板、第二半導體晶粒、第二互連結構；以及將該等包封的第一封裝基板、第一半導體晶粒、第一互連結構與該等包封的第二封裝基板、第二半導體晶粒、第二互連結構分開。
  17. 如申請專利範圍第16項的方法，其包括：在該移除之後和在該分開之前，在該第一封裝基板的底面上和在該第二封裝基板的底面上形成底部互連結構。
  18. 如申請專利範圍第16項的方法，其包括：在該包封之後和在形成該第一插置物之前和在形成該第二插置物之前，將該包封劑薄化以暴露該第一互連結構的第一頂端和該第二互連結構的第二頂端。
  19. 如申請專利範圍第16項的方法，其中該分開包括：切割穿過在該第一封裝基板和該第二封裝基板之間的該包封材料。
  20. 如申請專利範圍第16項的方法，其中在該分開之後，該第一插置物、該包封材料、該第一封裝基板的個別側面共平面。
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