TW201526125A - 半導體裝置和在扇出封裝中於半導體晶粒上形成細節距重新分佈層之方法 - Google Patents

半導體裝置和在扇出封裝中於半導體晶粒上形成細節距重新分佈層之方法 Download PDF

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TW201526125A
TW201526125A TW103137166A TW103137166A TW201526125A TW 201526125 A TW201526125 A TW 201526125A TW 103137166 A TW103137166 A TW 103137166A TW 103137166 A TW103137166 A TW 103137166A TW 201526125 A TW201526125 A TW 201526125A
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conductor
layer
conductor layer
semiconductor
rdl
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TW103137166A
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TWI626697B (zh
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潘迪Ｃ 瑪莉姆蘇
耀劍 林
崔源璟
沈一權
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史達晶片有限公司
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Abstract

一種半導體裝置具有一包含複數條導體線路的第一導體層。該第一導體層被形成在一基板上方。該些導體線路被形成具有窄節距。一第一半導體晶粒與第二半導體晶粒被設置在該第一導體層上方。一第一囊封體被沉積在該些第一半導體晶粒與第二半導體晶粒上方。該基板被移除。一第二囊封體被沉積在該第一囊封體上方。一增進互連結構被形成在該第一導體層與第二囊封體上方。該增進互連結構包含一第二導體層。一第一被動裝置被設置在該第一囊封體之中。一第二被動裝置被設置在該第二囊封體之中。一垂直互連單元被設置在該第二囊封體之中。一第三導體層被形成在第二囊封體上方並且透過該垂直互連單元被電氣連接至該增進互連結構。

Description

半導體裝置和在扇出封裝中於半導體晶粒上形成細節距重新分佈層之方法
本發明大體上和半導體裝置有關，且更明確地說，本發明係關於半導體裝置和在扇出封裝中於半導體晶粒上形成細節距重新分佈層之方法。
在現代的電子產品中經常發現半導體裝置。半導體裝置會有不同數量與密度的電氣組件。離散式半導體裝置通常含有某一種類型的電氣組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電氣組件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網 路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的結構使得可藉由施加電場或基極電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至半導體材料之中，以便操縱及控制半導體裝置的傳導性。
半導體裝置含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基極電流，電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該些被動式結構與主動式結構會被電氣連接以形成讓半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個半導體晶粒通常相同並且含有藉由電氣連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的半導體晶粒並且封裝該晶粒，用以提供結構性支撐以及環境隔離。本文中所使用的「半導體晶粒(semiconductor die)」一詞兼具單數和複數形式，且據此會表示單一半導體裝置以及多個半導體裝置兩者。
半導體製造的其中一個目標便係生產較小型的半導體裝置。較小型裝置通常會消耗較少的電力，具有較高的效能，並且能夠被更 有效地生產。此外，較小型的半導體裝置還具有較小的覆蓋區，這係較小型末端產品所需要的。藉由改良前端製程能夠達成較小的半導體晶粒尺寸，從而導致具有較小尺寸以及較高密度之主動式組件和被動式組件的半導體晶粒。後端製程可以藉由改良電氣互連及封裝材料而導致具有較小覆蓋區的半導體裝置封裝。
達成較大整合與較小半導體裝置的其中一種方式聚焦在2.5D的封裝技術(也就是，在一裝置裡面的相鄰半導體晶粒之間的電氣互連)以及3D的封裝技術(也就是，垂直堆疊的半導體晶粒或封裝上封裝(Package-on-Package，PoP)半導體裝置之間的電氣互連)。
在扇出嵌入式晶圓級球柵陣列(Fan-out embedded Wafer Level Ball Grid Array，Fo-eWLB)中，相鄰半導體晶粒之間的電氣互連以及半導體晶粒與外部裝置之間的電氣互連係經由增進互連結構來提供。該增進互連結構被形成在該半導體晶粒與一包圍該半導體晶粒的囊封體的上方。該增進互連結構通常包含多個重新分佈層(ReDistribution Layer，RDL)。當形成一具有細節距或窄節距RDL的增進互連結構時，舉例來說，節距為5微米(μm)的RDL，該經囊封的半導體晶粒會被焊接至一暫時性載體，用以防止在形成該增進互連結構期間發生翹曲。在該增進互連結構被形成之後，複數個互連結構(舉例來說，導體凸塊)會被形成在該增進互連結構上方並且皆著該暫時性載體會被移除。焊接(bonding)與焊接脫離(debonding)該暫時性載體至該經囊封的半導體晶粒會增加製造過程的步驟、增加製造時間與成本、以及降低產量。此外，形成具有超細節距RDL(舉例來說，2μm或更小)之增進互連結構的Fo-eWLB非常困難並且牽涉到複雜、需要高度控制、昂貴、 以及耗時的製造步驟。
一裝置裡面的相鄰半導體晶粒之間的電氣互連以及半導體晶粒與外部裝置之間的電氣互連亦能夠藉由在該半導體封裝裡面嵌入一直通矽晶穿孔(Through Silicon Via，TSV)來達成。在一2.5D的TSV封裝中，RDL會被形成在一中介片(interposer)上方並且導體的TSV會被形成貫穿一中介片，用以提供電氣互連。該導體的TSV與RDL會在被設置於該中介片上方的半導體晶粒之間以及在該半導體晶粒與外部裝置之間繞送信號。被形成在一TSV中介片上的RDL可縮小至次微米的尺寸，也就是，奈米範圍；然而，形成一TSV中介片封裝牽涉到複雜、昂貴、以及耗時的製造步驟。此外，TSV中介片的垂直互連還會消耗空間並且增加封裝的總高度。據此，TSV中介片封裝無法符合較小型半導體裝置的X、Y、以及Z的必要條件，也就是，長度、寬度、以及高度。
本技術領域需要一種節省成本的半導體封裝，其包含具有TSV中介片封裝之超窄節距的RDL以及Fo-eWLB封裝的小型外形因子，也就是，較小的X、Y、以及Z尺寸。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一基板；形成一第一導體層於該基板上方；設置一半導體晶粒於該第一導體層上方；設置一第一囊封體於該半導體晶粒上方；移除該基板；設置一第二囊封體於該第一囊封體上方；以及形成一互連結構於該第一導體層與第二囊封體上方。
於另一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一第一導體層；設置一第一半導體晶粒於該第一 導體層上方；設置一第一囊封體於該第一半導體晶粒上方；以及形成一互連結構於面對於該第一半導體晶粒的該第一導體層上方。
於另一實施例中，本發明係一種半導體裝置，其包括一包含複數條第一導體線路的第一導體層。一第一半導體晶粒被設置在該第一導體層的一第一表面上方。一包含複數條第二導體線路的第二導體層被設置在面對於該第一導體層之第一表面的該第一導體層的一第二表面上方。該些第一導體線路的節距小於該些第二導體線路的節距。
於另一實施例中，本發明係一種半導體裝置，其包括一第一導體層以及一被設置在該第一導體層上方的第一半導體晶粒。一互連結構被形成在面對於該第一半導體晶粒的該第一導體層上方。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧訊號線路
56‧‧‧焊線封裝
58‧‧‧覆晶
60‧‧‧球柵陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙直列封裝(DIP)
66‧‧‧平台格柵陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧方形扁平無導線封裝(QFN)
72‧‧‧方形扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導體導線
82‧‧‧焊線
84‧‧‧囊封體
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底層填充材料或環氧樹脂膠黏材料
94‧‧‧焊線
96‧‧‧接觸墊
98‧‧‧接觸墊
100‧‧‧模製化合物或囊封體
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中間載體
108‧‧‧主動區
110‧‧‧凸塊
112‧‧‧凸塊
114‧‧‧訊號線
116‧‧‧模製化合物或囊封體
120‧‧‧半導體晶圓
122‧‧‧基礎基板材料
124‧‧‧半導體晶粒或組件
126‧‧‧切割道
128‧‧‧背表面或非主動表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣層或鈍化層
136‧‧‧探針
138‧‧‧測試探針頭
140‧‧‧電腦測試系統
150‧‧‧導電層或重新分佈層(RDL)
152‧‧‧絕緣層或鈍化層
154‧‧‧圖樣化層或光阻層
156‧‧‧雷射
158‧‧‧開口
160‧‧‧導電層
162‧‧‧導電材料
164‧‧‧導體柱
166‧‧‧凸塊帽部
168‧‧‧互連結構
170‧‧‧鋸片或雷射削切工具
180‧‧‧載體或暫時性基板
182‧‧‧絕緣層或鈍化層
184‧‧‧導電層或重新分佈層(RDL)
186‧‧‧絕緣層或鈍化層
188‧‧‧導電層或重新分佈層(RDL)
190‧‧‧絕緣層或鈍化層
192‧‧‧凸塊
194‧‧‧晶圓級重新分佈層(WL RDL)或增進互連結構
196‧‧‧重組式晶圓
198‧‧‧囊封體或模製化合物
200‧‧‧表面
202‧‧‧底層填充材料
206‧‧‧雷射
208‧‧‧切晶膠帶或支撐載體
210‧‧‧鋸片或雷射削切工具
220‧‧‧晶圓級晶片尺寸封裝(WLCSP)
230‧‧‧載體或暫時性基板
232‧‧‧介面層或雙面膠帶
234‧‧‧重組式晶圓
236‧‧‧囊封體或模製化合物
238‧‧‧表面
239‧‧‧表面
240‧‧‧絕緣層或鈍化層
242‧‧‧導電層或重新分佈層(RDL)
244‧‧‧絕緣層或鈍化層
246‧‧‧導電層或重新分佈層(RDL)
248‧‧‧絕緣層或鈍化層
250‧‧‧增進互連結構
252‧‧‧球體或凸塊
254‧‧‧鋸片或雷射削切工具
260‧‧‧半導體裝置
370‧‧‧載體或暫時性基板
372‧‧‧絕緣層
374‧‧‧導體層
376‧‧‧絕緣層
378‧‧‧導體層
380‧‧‧絕緣層
382‧‧‧凸塊
384‧‧‧WL RDL或增進互連結構
390‧‧‧半導體晶粒
392‧‧‧背表面或非主動表面
394‧‧‧主動表面
396‧‧‧導電層
398‧‧‧絕緣層或鈍化層
400‧‧‧導電層或重新分佈層(RDL)
402‧‧‧絕緣層或鈍化層
403‧‧‧導電層
404‧‧‧導體柱
406‧‧‧凸塊帽部
408‧‧‧互連結構
412‧‧‧半導體組件或被動裝置
414‧‧‧重組式晶圓
416‧‧‧囊封體或模製化合物
418‧‧‧表面
420‧‧‧雷射
422‧‧‧切晶膠帶或支撐載體
424‧‧‧鋸片或雷射削切工具
430‧‧‧晶圓級晶片尺寸封裝(WLCSP)
432‧‧‧載體或暫時性基板
434‧‧‧介面層或雙面膠帶
436‧‧‧半導體組件或被動裝置
438‧‧‧重組式晶圓
440‧‧‧囊封體或模製化合物
442‧‧‧表面
444‧‧‧表面
446‧‧‧絕緣層或鈍化層
448‧‧‧導電層或重新分佈層(RDL)
450‧‧‧絕緣層或鈍化層
452‧‧‧導電層或重新分佈層(RDL)
454‧‧‧絕緣層或鈍化層
456‧‧‧增進互連結構
458‧‧‧球體或凸塊
460‧‧‧鋸片或雷射削切工具
470‧‧‧半導體裝置
480‧‧‧載體或暫時性基板
482‧‧‧介面層或雙面膠帶
484‧‧‧垂直互連單元
486‧‧‧核心基板
488‧‧‧z方向垂直互連線或導體穿孔
490‧‧‧導電層或重新分佈層(RDL)
492‧‧‧導電層或重新分佈層(RDL)
500‧‧‧重組式晶圓
502‧‧‧囊封體或模製化合物
504‧‧‧表面
506‧‧‧表面
510‧‧‧開口
512‧‧‧絕緣層或鈍化層
514‧‧‧導電層或重新分佈層(RDL)
516‧‧‧絕緣層或鈍化層
518‧‧‧導電層或重新分佈層(RDL)
520‧‧‧絕緣層或鈍化層
522‧‧‧增進互連結構
524‧‧‧球體或凸塊
526‧‧‧研磨機
528‧‧‧表面
530‧‧‧開口
532‧‧‧雷射
534‧‧‧鋸片或雷射削切工具
538‧‧‧半導體裝置
540‧‧‧絕緣層或鈍化層
542‧‧‧導電層或重新分佈層(RDL)
544‧‧‧絕緣層或鈍化層
546‧‧‧鋸片或雷射削切工具
550‧‧‧半導體裝置
560‧‧‧半導體裝置
562‧‧‧半導體組件或被動裝置
圖1所示的係一印刷電路板(PCB)，在該PCB的表面鑲嵌著不同類型的封裝；圖2a至2c所示的係被鑲嵌至該PCB的代表性半導體封裝的進一步細節；圖3a至3i所示的係具有藉由切割道分離之複數個半導體晶粒的半導體晶圓；圖4a至4s所示的係形成一包含細節距RDL與增進互連結構的半導體裝置的製程；圖5所示的係包含細節距RDL與增進互連結構的半導體裝置；圖6a至6i所示的係於一半導體裝置裡面形成細節距RDL與嵌入式被 動裝置的製程；圖7所示的係包含細節距RDL與嵌入式被動裝置的半導體裝置；圖8a至8i所示的係於一半導體裝置裡面形成細節距RDL並且嵌入垂直互連單元的製程；圖9所示的係於包含細節距RDL與嵌入式垂直互連單元的半導體裝置；圖10a至10f所示的係形成具有細節距RDL與雙面RDL的半導體裝置的製程；圖11所示的係具有細節距RDL與雙面RDL的半導體裝置；以及圖12所示的係包含細節距RDL、雙面RDL、以及嵌入式被動裝置的半導體裝置。
在下面的說明中參考圖式於一或更多個實施例中說明本發明，於該些圖式中，相同的符號代表相同或雷同的元件。雖然本文以達成本發明之目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及該些申請專利範圍之等效範圍所定義的本發明的精神與範疇內可以併入的替代例、修正例、以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電氣組件和被動式電氣組件，它們會被電氣連接而形成功能性電路。主動式電氣組件(例如電晶體與二極體)能夠控制電流的流動。被動式電氣組件(例如電容器、電感器、以及電阻器)會創造用 以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該些製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會藉由響應於電場或基極電流來動態改變半導體材料傳導性而修正主動式裝置中半導體材料的導電性。電晶體含有不同類型及不同摻雜程度的多個區域，它們會在必要時被排列成用以在施加電場或基極電流下讓該電晶體提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該些層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電氣連接線的一部分。
後端製造係指將已完成的晶圓切割或單體化裁切成個別的晶粒，並且接著封裝該半導體晶粒，以達結構性支撐以及環境隔離的效果。為單體化裁切半導體晶粒，該晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別半導體晶粒便會被鑲嵌至包含接針或接觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸墊接著會被連接至該封裝裡面的接觸墊。該些電氣連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。 一囊封體或是其它模製材料會被沉積在該封裝的上方，用以提供物理性支撐和電氣隔離。接著，已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1圖解電子裝置50，其具有一晶片載體基板或是PCB 52，在PCB 52的一表面上鑲嵌著複數個半導體封裝。電子裝置50會具有某一種類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋的目的，圖1中顯示不同類型的半導體封裝。
電子裝置50能夠係單機型系統，其使用該些半導體封裝來實施一或更多項電氣功能。或者，電子裝置50亦能夠係一較大型系統中的子組件。舉例來說，電子裝置50能夠係蜂巢式電話、個人數位助理(Personal Digital Assistant，PDA)、數位錄像機(Digital Video Camera，DVC)、或是其它電子通信裝置的一部分。或者，電子裝置50能夠係圖形卡、網路介面卡、或是能夠被插入在電腦之中的其它訊號處理卡。該半導體封裝能夠包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻(Radio Frequency，RF)電路、離散式裝置、或是其它半導體晶粒或電氣組件。該些產品要被市場接受，微型化以及減輕重量相當重要。半導體裝置之間的距離必須縮小，以達更高密度的目的。
在圖1中，PCB 52提供一通用基板，用以達到結構性支撐以及電氣互連被鑲嵌在該PCB上的半導體封裝的目的。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該些半導體封裝、被鑲嵌的組件、以及其它外 部系統組件中的每一者之間提供電氣通訊。線路54還提供連接至每一個該些半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載體的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載體附接至該PCB。於其它實施例中，一半導體裝置可以僅有該第一層封裝，其中，該晶粒係以機械方式及電氣方式直接被鑲嵌至該PCB。
為達解釋的目的，圖中在PCB 52上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在PCB 52上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載體(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合的半導體封裝和其它電子組件所組成的任何組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；不過，其它實施例則會需要多個互連封裝。藉由在單一基板上方組合一或更多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該些半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而降低消費者的成本。
圖2a至圖2c所示的係示範性半導體封裝。圖2a所示的係 被鑲嵌在PCB 52上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該些類比電路或數位電路會被施行為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路能夠包含被形成在半導體晶粒74之主動區裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76係由導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))所製成的一或更多層，並且被電氣連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂或是環氧樹脂)被鑲嵌至中間載體78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與PCB 52之間提供電氣互連。囊封體84會被沉積在該封裝的上方，用以藉由防止濕氣和粒子進入封裝並且防止污染晶粒74或焊線82而達到環境保護的目的。
圖2b所示的係被鑲嵌在PCB 52之上的BCC 62的進一步細節。半導體晶粒88係利用底層填充材料或環氧樹脂膠黏材料92被鑲嵌在載體90的上方。焊線94會在接觸墊96與98之間提供第一層封裝互連。模製化合物或囊封體100係被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電氣隔離效果。多個接觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的表面上方，用以防止氧化。接觸墊102會被電氣連接至PCB 52中的一或更多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸墊98和PCB 52的接觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載體106。半導體晶粒58的主動區108含有類比電路或數位電路，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路能夠包含在主動區108裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載體106。
BGA 60會以利用多個凸塊112的BGA樣式第二層封裝，以電氣方式及機械方式被連接至PCB 52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電氣連接至PCB 52中的導體訊號線路54。一模製化合物或囊封體116會被沉積在半導體晶粒58和載體106的上方，用以為該裝置提供物理性支撐以及電氣隔離效果。該覆晶半導體裝置會從半導體晶粒58上的主動式裝置至PCB 52上的傳導軌提供一條短電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改良整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至PCB 52，而沒有中間載體106。
圖3a所示的係半導體晶圓120，其具有基礎基板材料122(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或組件124會被形成在晶圓120上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道126來分離。切割道126提供削切區，以便將半導體晶圓120單體化裁切成個別的半導體晶粒124。於其中一實施例中，半導體晶圓120具有200至300毫米(mm)的寬度或直徑。於另一實施例 中，半導體晶圓120具有100至450mm的寬度或直徑。
圖3b所示的係半導體晶圓120的一部分的剖視圖。每一個半導體晶粒124皆有一背表面或非主動表面128以及含有類比電路或數位電路的主動表面130，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面130裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可以還含有用於RF訊號處理的積體被動式裝置(Integrated Passive Device，IPD)，例如，電感器、電容器、以及電阻器。
一導電層132會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面130的上方。導體層132能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層132的操作如同被電氣連接至主動表面130上之電路的接觸墊。導體層132會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒124的邊緣相隔第一距離處，如圖3b之中所示。或者，導體層132會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。
一絕緣層或鈍化層134係利用PVD、CVD、網印、旋塗、噴塗、燒結、或是熱氧化被形成在主動表面130的上方。絕緣層134含有由下 面所製成的一或更多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)、或是具有絕緣特性及雷同結構特性的其它材料。該絕緣層134覆蓋主動表面130並且提供保護。一部分的絕緣層134會藉由蝕刻、雷射直接燒蝕(Laser Direction Ablation，LDA)、或是其它合宜的製程來移除，用以露出導體層132以進行後續的電氣互連。
半導體晶圓120會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓120上實施檢查。軟體會被使用在半導體晶圓120的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓120的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。
半導體晶粒124裡面的主動式組件和被動式組件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒124係利用一探針136或是其它測試裝置來測試功能與電氣參數，如圖3c中所示。測試探針頭138包含複數個探針136。探針136係被用來電氣接觸每一個半導體晶粒124上的節點或接觸墊132並且提供電氣刺激給該些接觸墊。半導體晶粒124會回應該些電氣刺激，該回應會被電腦測試系統140測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻係數、連續性、可靠度、接面深度、靜電放電(Electro-Static Discharge，ESD)、RF效能、驅動電流、臨界電流、漏電流、以及該組件類型特有的操作參數。半導體晶圓120的檢查與電氣測試可讓通過測試而被指定為已知良品晶粒(Known Good Die，KGD)的半導體晶粒 124使用於半導體封裝中。
在圖3d中，一導電層或RDL 150會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在導體層132與絕緣層134的上方。導體層150能夠係由下面所製成的一或更多層：Al、Ti、TiW、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。一部分的導體層150會被電氣連接至導體層132。其它部分的導體層150則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。
一絕緣層或鈍化層152會利用PVD、CVD、印刷、層疊、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層134以及導體層150的上方。絕緣層152含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層152會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層150。
在圖3e中，一圖樣化層或光阻層154會利用印刷、旋塗、或噴塗被形成在絕緣層152上方。一部分的光阻層154會利用雷射156藉由LDA來移除，用以形成多個已圖樣化的開口158並且露出絕緣層152與導體層150。或者，該部分的光阻層154藉由一蝕刻製程貫穿一已圖樣化光阻層而被移除，用以形成多個已圖樣化的開口158並且露出絕緣層152與導體層150。於其中一實施例中，已圖樣化的開口158具有圓形的剖面面積，其被配置成用以形成具有包含圓形剖面之圓柱體形狀的導體柱。於另一實施例中，已圖樣化的開口158具有矩形的剖面面積，其被配置成用以形成具有包含矩形剖面之立方體形狀的導體柱。
在圖3f中，一導電層160會利用諸如印刷、PVD、CVD、 濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被保形塗敷在開口158裡面的絕緣層152與導體層150的上方。或者，導體層160亦能夠在形成光阻層154之前被形成在絕緣層152與導體層150的上方。導體層160能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ti、Ni、Au、Ag、或是其它合宜的導電材料。於其中一實施例中，導體層160能夠係一包含晶種層、屏障層、以及黏著層的多層堆疊。晶種層能夠係銅化鈦(TiCu)、銅化鈦鎢(TiWCu)、或是氮化鉭銅(TaNCu)。屏障層能夠係Ni、釩化鎳(NiV)、鉑(Pt)、鈀(Pd)、TiW、CrCu、或是其它合宜材料。黏著層能夠為Ti、TiN、TiW、Al、鉻(Cr)、或是其它合宜材料。導體層160會遵循絕緣層152與導體層150的輪廓。導體層160被電氣連接至導體層150。
在圖3g中，一導電材料162會利用蒸發製程、濺鍍製程、電解質電鍍製程、無電極電鍍製程、或是網印製程被沉積在開口158裡面以及導體層160的上方。導體材料162能夠係Cu、Al、鎢(W)、Au、焊料、或是其它合宜的導電材料。於其中一實施例中，導電材料162會藉由電鍍Cu於光阻層154的已圖樣化開口158之中而被沉積。
在圖3h中，光阻層154藉由一蝕刻製程而被移除，用以留下個別的導體柱164。導體柱164會有具有圓形或橢圓形剖面的圓柱體形狀，或者，導體柱164會有具有矩形剖面的立方體形狀。於另一實施例中，導體柱164會以多個堆疊凸塊或短柱凸塊來施行。
在圖3i中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體柱164的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及 它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會被回焊，用以形成圓形的凸塊帽部166。於某些應用中，凸塊帽部166會被二次回焊，以便改良和柱狀體164的電氣接觸效果。或者，該導電凸塊材料會在移除光阻層154之前先被沉積。導體柱164與凸塊帽部166的組合構成一具有不可熔化部分(導體柱164)與可熔化部分(凸塊帽部166)的合成互連結構168。合成互連結構168代表能夠被形成在半導體晶粒124上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、凸塊、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
半導體晶圓120會利用鋸片或雷射削切工具170被單體化裁切貫穿切割道126成為個別的半導體晶粒124。個別的半導體晶粒124皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。
圖4a至4s配合圖1以及2a至2c圖解形成一包含細節距RDL與增進互連結構的半導體裝置的製程。圖4a所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板180的一部分的剖視圖。
一絕緣層或鈍化層182會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在基板180的上方。絕緣層182包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層182經過選擇而對矽蝕刻劑有良好的選擇性並且能夠在基板180的稍後移除期間充當蝕刻阻止層。
一導電層或RDL 184會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層182的上方。導體層184能夠係由下面所製成的一或更多層：Al、Ti、TiW、Cu、Sn、Ni、Au、Ag、或是其它導電材料。一部分的導體層184會相依於稍後鑲嵌的半導體晶粒的設計與功能而為共電或是被電氣隔離。導體層184包含複數條導體線路。導體層184的該些導體線路被形成具有細節距或窄節距。舉例來說，於其中一實施例中，導體層184的該些導體線路具有2μm的節距。
一絕緣層或鈍化層186會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層182與導體層184的上方。絕緣層186包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層186會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層184。
在圖4b中，一導電層或RDL 188會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被保形沉積在絕緣層186與導體層184的上方。導體層188能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層188會被電氣連接至導體層184。其它部分的導體層188則能夠相依於稍後鑲嵌的半導體晶粒的設計與功能而為共電或是被電氣隔離。導體層188包含複數條導體線路。導體層188的該些導體線路被形成具有細節距或窄節距。於其中一實施例中，導體層188的該些導體線路具有2μm的節距。
在圖4c中，一絕緣層或鈍化層190會利用PVD、CVD、印 刷、旋塗、噴塗、層疊、燒結、或是熱氧化被形成在絕緣層186與導體層188的上方。絕緣層190包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、PI、BCB、PBO、WPR、環氧樹脂、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層190係一防焊層。一部分的絕緣層190會藉由蝕刻、LDA、或是其它合宜的製程來移除，用以露出導體層188。
在圖4d中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層188的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層188。於其中一實施例中，該凸塊材料會藉由將該材料加熱至該材料的熔點以上而被回焊，用以形成凸塊192。於某些應用中，凸塊192會被二次回焊，以便改良和導體層188的電氣接觸效果。於其中一實施例中，凸塊192被形成在一UBM層的上方。凸塊192亦能夠被壓縮焊接或熱壓縮焊接至導體層188。凸塊192代表能夠被形成在導體層188上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
絕緣層182、導體層184、絕緣層186、導體層188、絕緣層190、以及凸塊192構成一晶圓級重新分佈層(Wafer Level ReDistribution Layer，WL RDL)或增進互連結構194。WL RDL 194可以包含一IPD，例如，電容器、電感器、或是電阻器。WL RDL 194裡面的導體線路會被形成具有 細節距，舉例來說，2μm的節距，並且可縮小至次微米的尺寸，也就是，奈米範圍。WL RDL 194中的導體線路的窄節距允許在WL RDL 194裡面形成較高密度(也就是，較大數量)的導體線路。提高導體線路的數量會增加WL RDL 194的互連部位的數量以及輸入/輸出(Input/Output，I/O)終端數。需要高I/O數的半導體晶粒能夠被鑲嵌至WL RDL 194。除此之外，有不同I/O需求的半導體晶粒及/或來自多個製造商的晶粒亦能夠被設置在WL RDL 194上。
在圖4e中，圖3i中的半導體晶粒124被設置在WL RDL 194上方。半導體晶粒124的互連結構168會對齊凸塊192。半導體晶粒124會利用拾放操作或是其它合宜的操作被鑲嵌至WL RDL 194。半導體晶粒124為已在鑲嵌半導體晶粒124至WL RDL 194之前經過測試的KGD。
圖4f所示的係半導體晶粒124被鑲嵌至WL RDL 194而形成一重組式晶圓196。凸塊帽部166會被回焊，以便以冶金方式及電氣方式將半導體晶粒124連接至WL RDL 194。於某些應用中，凸塊帽部166會被二次回焊，以便改善和凸塊192的電氣接觸效果。互連結構168亦能夠被壓縮焊接或熱壓縮焊接至凸塊192。WL RDL 194會根據半導體晶粒124的設計與功能在半導體晶粒之間繞送電氣信號。
在圖4g中，一囊封體或模製化合物198會利用焊膏印刷(paste printing)塗敷機、壓縮模製(compressive molding)塗敷機、轉印模製(transfer molding)塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124以及WL RDL 194的上方。囊封體198能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的 環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體198係非導體、提供物理性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體198還保護半導體晶粒124，避免因曝露於光中而受損。於其中一實施例中，一部分的囊封體198會在後續的背研磨步驟中從囊封體198的表面200處被移除。該背研磨操作會平坦化囊封體198的該表面並且縮減重組式晶圓196的總厚度。
如圖4g中所示，囊封體198會在半導體晶粒124與WL RDL 194之間流動，並且圍繞互連結構168。於其中一實施例中，一底層填充材料202(例如，環氧樹脂)會被沉積在半導體晶粒124與WL RDL 194之間，如圖4h中所示。底層填充材料202能夠藉由毛細管底層填充製程被沉積。或者，在附著半導體晶粒124之前，一非導體膏或是非導體膜會先被塗敷至WL RDL 194。
接續圖4g，載體180會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除。移除載體180會留下WL RDL 194被附著至半導體晶粒124並且露出絕緣層182，如圖4i中所示。
在圖4j中，一部分的絕緣層182會利用雷射206藉由LDA來移除，用以露出導體層184。或者，一部分的絕緣層182會藉由曝光與顯影製程、藉由蝕刻、或是其它合宜的製程而被移除，用以露出導體層184。
於其中一實施例中，一部分的載體180會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，並且一薄層載體180會殘留在絕緣層182的上方，如圖4k中所示。 該殘留的薄層載體180的一部分以及一部分的絕緣層182接著會利用雷射206藉由LDA來移除，用以露出導體層184。
接續圖4j，一切晶膠帶或支撐載體208會被塗敷在絕緣層182的上方，如圖4l中所示。重組式晶圓196接著會利用鋸片或雷射削切工具210被單體化裁切貫穿囊封體198與WL RDL 194而成為個別的晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package，WLCSP)220，其包含半導體晶粒124以及細節距WL RDL 194。切晶膠帶208會在單體化裁切期間支撐重組式晶圓196。
在圖4m中，圖4l中的WLCSP 220會被設置在一載體或暫時性基板230的上方，該載體或暫時性基板230含有犧牲基礎材料，例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料。一介面層或雙面膠帶232會被形成在載體230的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
載體230能夠為一可容納多個WLCSP 220的圓形或矩形鑲板(大於300mm)。載體230的表面積可以大於半導體晶圓120及/或重組式晶圓196的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒/封裝能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。
為進一步降低製造成本，載體230的大小會不相依於半導體晶粒124與WLCSP 220的大小或是晶圓120與重組式晶圓196的大小來選擇。也就是，載體230具有固定或是標準化大小，其能夠容納分別從一或 更多個晶圓120及重組式晶圓196處單體化裁切出來的各種大小半導體晶粒124與WLCSP 220。於其中一實施例中，載體230為直徑330mm的圓形。於另一實施例中，載體230為寬度560mm以及長度600mm的矩形。多個WLCSP 220被放置在該標準化載體230上方，WLCSP包含多個半導體晶粒124，舉例來說，該些半導體晶粒124有10mm乘10mm的面積。或者，多個WLCSP 220被放置在該相同的標準化載體230上方，WLCSP 220包含多個半導體晶粒124，舉例來說，半導體晶粒124有20mm乘20mm的面積。據此，標準化載體230能夠應付任何大小的半導體晶粒或WLCSP，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒或封裝大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體230藉由減少或消弭以晶粒或封裝大小或是進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒或封裝便能夠施行靈活的製造線。
圖4n所示的係多個WLCSP 220被鑲嵌至載體230，用以形成一重組式晶圓234。一囊封體或模製化合物236會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在WLCSP 220與載體230的上方。囊封體236能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體236係非導體、提供物理性支撐、並且為該半導體裝置提供環境保護，避免受到外部 元素與污染物的破壞。囊封體236還保護半導體晶粒124，避免因曝露於光中而受損。於其中一實施例中，一部分的囊封體236會在後續的背研磨步驟中從囊封體236的表面238處被移除。該背研磨操作會平坦化囊封體236的該表面並且縮減半導體裝置的總厚度。面對於背側表面238的囊封體236的一表面239被設置在載體230與介面層232上方，俾使得囊封體236的表面239共面於WLCSP 220的絕緣層182。
在圖4o中，載體230與介面層232會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，用以露出囊封體236的表面239以及WLCSP 220的絕緣層182。
在圖4p中，重組式晶圓234被倒置，並且一絕緣層或鈍化層240會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在囊封體236的表面239以及絕緣層182的上方。絕緣層240包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層240會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層184。於其中一實施例中，該部分的絕緣層182以及該部分的絕緣層240會同時被移除，也就是，在單一製造步驟中被移除，用以露出導體層184。
一導電層或RDL 242會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層240與導體層184的上方。導體層242能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層242會被電氣連接至導 體層184。其它部分的導體層242則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。導體層242包含複數條導體線路。導體層242的該些導體線路被形成具有寬於WL RDL 194裡面的導體線路的節距。於其中一實施例中，導體層242的該些導體線路具有15μm或更大的節距。
在圖4q中，一絕緣層或鈍化層244會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層240以及導體層242的上方。絕緣層244包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層244會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層242。
一導電層或RDL 246會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層244與導體層242的上方。導體層246能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層246會被電氣連接至導體層242。其它部分的導體層246則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。導體層246包含複數條導體線路。導體層246的該些導體線路被形成具有寬於WL RDL 194中的導體層184與188的導體線路的節距。於其中一實施例中，導體層246的該些導體線路具有15μm或更大的節距。
在圖4r中，一絕緣層或鈍化層248會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層244以及導體層246 的上方。絕緣層248包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層248係一防焊層。一部分的絕緣層248會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層246。
絕緣層240、導體層242、絕緣層244、導體層246、以及絕緣層248的組合構成一被形成在WLCSP 220與囊封體236上方的增進互連結構250。增進互連結構250裡面所包含的絕緣層與導體層的數量相依於該電路繞送設計的複雜度並且隨著該電路繞送設計的複雜度而改變。據此，增進互連結構250能夠包含任何數量的絕緣層與導體層，用以促成相對於半導體晶粒124的電氣互連。增進互連結構250裡面的導體線路的寬鬆設計規則以及較大節距允許在增進互連結構250的製作中所使用的材料與製造技術有較大的靈活性並且降低製造成本。
在圖4s中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層246的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層246。於其中一實施例中，該凸塊材料會藉由將該材料加熱至該材料的熔點以上而被回焊，用以形成球體或凸塊252。於某些應用中，凸塊252會被二次回焊，以便改良和導體層246的電氣接觸效果。於其中一實施例中，凸塊252被形成在一UBM層的上方。凸塊252亦能夠 被壓縮焊接或熱壓縮焊接至導體層246。凸塊252代表能夠被形成在導體層246上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。重組式晶圓234的雷射標記能夠在凸塊成形之前或之後被實施，用以達到對齊、單體化裁切、及/或封裝辨識的目的。
圖4s進一步顯示重組式晶圓234利用鋸片或雷射削切工具254被單體化裁切貫穿增進互連結構250與囊封體236而成為個別的半導體裝置260，其包含半導體晶粒124、WL RDL 194、以及增進互連結構250。
圖5所示的係在單體化裁切之後的半導體裝置260。半導體晶粒124經由WL RDL 194以及增進互連結構250被電氣連接至凸塊252，用以連接至外部裝置，舉例來說，PCB。WL RDL 194在半導體晶粒124之間以及半導體晶粒124與增進互連結構250之間繞送電氣信號。增進互連結構250在WLCSP 220與外部裝置之間繞送電氣信號。形成兩個分開的增進互連結構，也就是，WL RDL 194與增進互連結構250，允許WL RDL 194運用窄節距RDL製作技術來提高半導體裝置260的I/O與電氣效能，而增進互連結構250則運用標準Fo-eWLB製作技術來最小化成本並且提供額外的繞送至外部組件。WL RDL 194的導體層184與188係在附著半導體晶粒124之前先被形成在暫時性基板180的上方，從而提供節省成本的方式來形成可縮小至次微米尺寸(也就是，奈米範圍)之具有超窄節距的RDL。導體層184與188裡面的導體線路的窄節距允許在WL RDL 194裡面有較高密度的互連線。高密度的互連線在半導體裝置的整合中提供更大的靈活性並且容納具有不同凸塊節距的半導體晶粒，舉例來說，來自多種製造源頭的半導 體晶粒。除此之外，導體線路的窄節距還會縮減WL RDL 194的大小並且縮短互連距離，也就是，電氣信號在半導體晶粒124與凸塊252之間必須前進的距離。較短的互連距離會提高半導體裝置260的速度與電氣效能。
相較於被用來形成TSV中介片封裝的製程，半導體裝置260裡面的WL RDL 194與增進互連結構250係利用更快速、更廉價、以及更低風險的製程來形成。除此之外，提供電氣互連而不必併入TSV中介片還會縮減半導體裝置260的體積與封裝輪廓。在增進互連結構250之前並且不相依地形成WLCSP 220則允許在鑲嵌WLCSP 220至基板230之前先測試半導體晶粒124之間的信號繞送以及WLCSP 220的功能。據此，僅有已知良好的WLCSP 220會被併入至半導體裝置260之中。僅使用已知良好的WLCSP 220來製作半導體裝置260會防止浪費製造時間與材料於製造有缺陷的封裝，且因此，半導體裝置260的產量會提高以及總成本會下降。
增進互連結構250在半導體裝置260裡面提供額外的導體層。該些額外的導體層可用於連接至其它內部裝置或外部裝置。增進互連結構250的導體層242與246係利用標準的Fo-eWLB製程以寬鬆的設計規則所形成。放寬增進互連結構250的設計規則允許在製作增進互連結構250中所使用的材料與製造技術有更大的靈活性。舉例來說，增進互連結構250能夠利用標準的Fo-eWLB設備及材料來形成，和製作具有超窄節距之導體層特有的材料不同。使用標準化設備及材料會縮短半導體裝置260的製造時間與成本。增進互連結構250裡面的導體線路的較寬節距同樣在凸塊252的擺放與節距中提供更大的靈活性。凸塊252的節距會經過選擇，以便反映工業標準。舉例來說，凸塊252能夠被形成具有和標準PCB上的互連觸 墊相同的節距。於其中一實施例中，凸塊252的節距為0.4mm。放寬凸塊252的設計規則會提高半導體裝置260與外部裝置的相容性並且消弭額外基板或中介片的需求。
在犧牲基板180上形成細節距WL RDL 194、藉由晶片至晶圓模製法將WL RDL 194轉印至半導體晶粒124、以及利用標準Fo-eWLB製作過程在WLCSP 220上方形成增進互連結構250允許半導體裝置260併入具有高I/O需求及/或不同I/O需求的半導體晶粒，同時最小化半導體裝置260的大小、製造時間、以及成本。
圖6a至6i配合圖1以及2a至2c圖解形成一包含細節距RDL與嵌入式被動裝置的半導體裝置的製程。圖6a所示的係一被形成在一載體或暫時性基板370上的WL RDL或增進互連結構384，雷同於圖4d中的WL RDL 194。基板370含有犧牲基礎材料，例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料。WL RDL 384包含絕緣層372、導體層374、絕緣層376、導體層378、絕緣層380、以及凸塊382。
絕緣層或鈍化層372會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在基板370的上方。絕緣層372包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層372經過選擇而對矽蝕刻劑有良好的選擇性並且能夠在基板370的稍後移除期間充當蝕刻阻止層。
導電層或RDL 374會使用PVD、CVD、電解質電鍍、無電 極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層372的上方。導體層374能夠係由下面所製成的一或更多層：Al、Ti、TiW、Cu、Sn、Ni、Au、Ag、或是其它導電材料。一部分的導體層374會相依於稍後鑲嵌的半導體晶粒的設計與功能而為共電或是被電氣隔離。導體層374包含複數條導體線路。導體層374的該些導體線路被形成具有細節距。舉例來說，於其中一實施例中，導體層374的該些導體線路具有2μm的節距。
絕緣層或鈍化層376會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層372與導體層374的上方。絕緣層376包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層376會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層374。
導電層378會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被保形沉積在絕緣層376與導體層374的上方。導體層378能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層378會被電氣連接至導體層374。其它部分的導體層378則能夠相依於稍後鑲嵌的半導體晶粒的設計與功能而為共電或是被電氣隔離。導體層378包含複數條導體線路。導體層378的該些導體線路被形成具有細節距。舉例來說，於其中一實施例中，導體層378的該些導體線路具有2μm的節距。
絕緣層或鈍化層380會利用PVD、CVD、印刷、旋塗、噴塗、層疊、燒結、或是熱氧化被形成在絕緣層376與導體層378的上方。絕緣層 380包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、PI、BCB、PBO、WPR、環氧樹脂、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層380係一防焊層。一部分的絕緣層380會藉由蝕刻、LDA、或是其它合宜的製程來移除，用以露出導體層378。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層378的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層378。於其中一實施例中，該凸塊材料會藉由將該材料加熱至該材料的熔點以上而被回焊，用以形成凸塊382。於某些應用中，凸塊382會被二次回焊，以便改良和導體層378的電氣接觸效果。於其中一實施例中，凸塊382被形成在一UBM層的上方。凸塊382亦能夠被壓縮焊接或熱壓縮焊接至導體層378。凸塊382代表能夠被形成在導體層378上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
絕緣層372、導體層374、絕緣層376、導體層378、絕緣層380、以及凸塊382構成WL RDL或增進互連結構384。WL RDL 384裡面的導體線路會被形成具有細節距，舉例來說，2μm的節距，並且可縮小至次微米的尺寸，也就是，奈米範圍。WL RDL 384中的導體線路的窄節距允許在WL RDL 384裡面形成較高密度(也就是，較大數量)的導體線路。提高導 體線路的數量會增加WL RDL 384的互連部位的數量以及I/O終端數。WL RDL 384會容納需要高I/O數的半導體晶粒。除此之外，有不同I/O需求的半導體晶粒及/或來自多個製造商的晶粒亦能夠被設置在WL RDL 384上。
圖6a進一步顯示被設置在WL RDL 384上方的半導體晶粒390(雷同於半導體晶粒124)以及被設置在半導體晶粒390的一周邊區域之中的WL RDL 384上方的半導體組件或被動裝置412。舉例來說，半導體晶粒390與被動裝置412會利用拾放操作被設置在WL RDL的上方。半導體晶粒390有一背表面或非主動表面392以及一面對於表面392的主動表面394，雷同於半導體晶粒124的主動表面130。一雷同於導體層132的導電層396被形成在主動表面394的上方。一雷同於絕緣層134的絕緣層或鈍化層398被形成在主動表面394與導體層396的上方。一部分的絕緣層398會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出一部分的導體層396。一雷同於半導體晶粒124之導體層150的導電層或RDL 400被形成在絕緣層398的上方。導體層400被電氣連接至導體層396。一雷同於絕緣層152的絕緣層或鈍化層402被形成在導體層400與絕緣層398的上方。一部分的絕緣層402會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出一部分的導體層400。一雷同於導體層160的導體層403被形成在導體層400與絕緣層402的上方。雷同於半導體晶粒124之互連結構168的複數個互連結構408被形成在導體層403的上方。互連結構408包含一不可熔化部分(導體柱404)與一可熔化部分(凸塊帽部406)。互連結構408代表能夠被形成在半導體晶粒390上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、凸塊、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
圖6b所示的係半導體晶粒390與被動裝置412被鑲嵌至WL RDL 384而形成一重組式晶圓414。凸塊帽部406會被回焊，以便以冶金方式及電氣方式將半導體晶粒390連接至WL RDL 384。於某些應用中，凸塊帽部406會被二次回焊，以便改善和凸塊382的電氣接觸效果。半導體晶粒390與被動裝置412會各自被電氣連接至WL RDL 384。於其中一實施例中，一雷同於圖4h中之底層填充材料202的底層填充材料會被設置在半導體晶粒390與WL RDL 384之間。
一囊封體或模製化合物416會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒390、被動裝置412、以及WL RDL 384的上方。囊封體416能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體416係非導體、提供物理性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體416還保護半導體晶粒390，避免因曝露於光中而受損。於其中一實施例中，一部分的囊封體416會在後續的背研磨步驟中從囊封體416的表面418處被移除。該背研磨操作會平坦化囊封體416的該表面並且縮減重組式晶圓414的總厚度。
在圖6c中，基板370會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，並且一部分的絕緣層372會利用雷射420藉由LDA來移除，用以露出導體層374。或者，該部分的絕緣層372會藉由曝光與顯影製程、藉由蝕刻、或是其它合宜的製程而被移除，用以露出導體層374。於其中一實施例中，一薄層基 板370會殘留在絕緣層372的上方，雷同於圖4k中的基板180。
在圖6d中，一切晶膠帶或支撐載體208會被塗敷在絕緣層372的上方。重組式晶圓414接著會利用鋸片或雷射削切工具424被單體化裁切貫穿囊封體416與WL RDL 384而成為個別的WLCSP 430，其包含半導體晶粒390、被動裝置412、以及細節距WL RDL 384。切晶膠帶422會在單體化裁切期間支撐重組式晶圓414。
在圖6e中，圖6d中的WLCSP 430會被設置在一載體或暫時性基板432的上方，該載體或暫時性基板432含有犧牲基礎材料，例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料。一介面層或雙面膠帶434會被形成在載體432的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
一半導體組件或被動裝置436會相鄰於WLCSP 430被設置在載體432與介面層434的上方。於其中一實施例中，WLCSP 430的被動裝置412係一較小的被動裝置，舉例來說，01005(公制碼0402)或0201(公制碼0603)大小的被動組件，而被動裝置436係一較大的被動裝置，舉例來說，0402(公制碼1005)或0603(公制碼1608)大小的被動組件。
圖6f所示的係WLCSP 430與被動裝置436被鑲嵌至載體432而形成一重組式晶圓438。一囊封體或模製化合物440會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在WLCSP 430、被動裝置436、以及載體432的上方。囊封體440能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。 囊封體440係非導體、提供物理性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體440還保護半導體晶粒390，避免因曝露於光中而受損。於其中一實施例中，一部分的囊封體440會在後續的背研磨步驟中從囊封體440的表面442處被移除。該背研磨操作會平坦化囊封體440的該表面並且縮減半導體裝置的總厚度。面對於背側表面442的囊封體440的一表面444被設置在載體432與介面層434上方，俾使得囊封體440的表面444共面於WLCSP 430的絕緣層372。
在圖6g中，載體432與介面層434會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除。移除載體432與介面層434會露出囊封體440的表面444、WLCSP 430的絕緣層372、以及被動裝置436。
在圖6h中，一增進互連結構456會被形成在囊封體440的表面444、WLCSP 430、以及被動裝置436的上方。增進互連結構456包含一絕緣層446、導體層448、絕緣層450、導體層452、以及絕緣層454。
絕緣層或鈍化層446會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在囊封體440的表面444、絕緣層372、以及被動裝置436的上方。絕緣層446包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層446會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層374與被動裝置436。於其中一實施例中，該部分的絕緣層372以及該部分的絕緣層446會同時被移除，也就是，在單一製造步驟中被移除， 用以露出導體層374與被動裝置436。
導電層或RDL 448會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層446的上方。導體層448能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層448會被電氣連接至導體層374。其它部分的導體層448則能夠相依於半導體晶粒390的設計與功能而為共電或是被電氣隔離。導體層448包含複數條導體線路。導體層448的該些導體線路係利用寬鬆的設計規則所形成並且具有寬於WL RDL 384裡面的導體線路的節距。於其中一實施例中，導體層448的該些導體線路具有15μm或更大的節距。
絕緣層或鈍化層450會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層446以及導體層448的上方。絕緣層450包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層450會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層448。
導電層或RDL 452會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層450與導體層448的上方。導體層452能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層452會被電氣連接至導體層448。其它部分的導體層452則能夠相依於半導體晶粒390的設計與功能而為共電或是被電氣隔離。導體層452包含複數條導體線路。導體層452 的該些導體線路被形成具有寬於WL RDL 384中的導體層374與378的導體線路的節距。於其中一實施例中，導體層452的該些導體線路具有15μm或更大的節距。
絕緣層或鈍化層454會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層450以及導體層452的上方。絕緣層454包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層454係一防焊層。一部分的絕緣層454會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層452。
絕緣層446、導體層448、絕緣層450、導體層452、以及絕緣層454會結合構成一增進互連結構456，其被形成在WLCSP 430、被動裝置436、以及囊封體440的上方。增進互連結構456裡面所包含的絕緣層與導體層的數量相依於該電路繞送設計的複雜度並且隨著該電路繞送設計的複雜度而改變。據此，增進互連結構456能夠包含任何數量的絕緣層與導體層，用以促成相對於半導體晶粒390的電氣互連。增進互連結構456裡面的導體線路的較大節距以及寬鬆設計規則允許在增進互連結構456的製作中所使用的材料與製造技術有較大的靈活性並且降低製造成本。
在圖6i中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層452的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是 Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層452。於其中一實施例中，該凸塊材料會藉由將該材料加熱至該材料的熔點以上而被回焊，用以形成球體或凸塊458。於某些應用中，凸塊458會被二次回焊，以便改良和導體層452的電氣接觸效果。於其中一實施例中，凸塊458被形成在一UBM層的上方。凸塊458亦能夠被壓縮焊接或熱壓縮焊接至導體層452。凸塊458代表能夠被形成在導體層452上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。重組式晶圓438的雷射標記能夠在凸塊成形之前或之後被實施，用以達到對齊、單體化裁切、及/或封裝辨識的目的。
圖6i進一步顯示重組式晶圓438利用鋸片或雷射削切工具460被單體化裁切貫穿增進互連結構456與囊封體440而成為個別的半導體裝置470，其包含WLCSP 430、被動裝置436、以及增進互連結構456。
圖7所示的係在單體化裁切之後的半導體裝置470。半導體晶粒390經由WL RDL 384以及增進互連結構456被電氣連接至凸塊458，用以連接至外部裝置。WL RDL 384在半導體晶粒390之間以及半導體晶粒390與被動裝置412之間繞送電氣信號。增進互連結構456在WLCSP 430、被動裝置436、以及外部裝置(舉例來說，PCB)之間繞送電氣信號。形成兩個分開的增進互連結構，也就是，WL RDL 384與增進互連結構456，允許WL RDL 384運用窄節距RDL製作技術來提高半導體裝置470的I/O與電氣效能，而增進互連結構456則運用標準Fo-eWLB製作技術來最小化成本並且提供額外的繞送至外部組件。WL RDL 384的導體層374與378係在附著 半導體晶粒390之前先被形成在暫時性基板370的上方，從而提供節省成本的方式來形成可縮小至次微米尺寸(也就是，奈米範圍)之具有超窄節距的RDL。導體層374與378裡面的導體線路的窄節距允許在WL RDL 384裡面有較高密度的互連線。高密度的互連線在半導體裝置的整合中提供更大的靈活性並且容納具有不同凸塊節距的半導體晶粒，舉例來說，來自多種製造源頭的半導體晶粒。除此之外，導體線路的窄節距還會縮減WL RDL 384的大小並且縮短互連距離，也就是，電氣信號在半導體晶粒390與凸塊458之間必須前進的距離。較短的互連距離會提高半導體裝置470的速度與電氣效能。
相較於被用來形成TSV中介片封裝的製程，半導體裝置470裡面的WL RDL 384與增進互連結構456係利用更快速、更廉價、以及更低風險的製程來形成。除此之外，提供電氣互連而不必併入TSV中介片還會縮減半導體裝置470的體積與封裝輪廓。在增進互連結構456之前並且不相依地形成WLCSP 430則允許在鑲嵌WLCSP 430至載體432之前先測試半導體晶粒390之間的信號繞送以及WLCSP 430的功能。據此，僅有已知良好的WLCSP 430會被併入至半導體裝置470之中。僅使用已知良好的WLCSP 430來製作半導體裝置470會防止浪費製造時間與材料於製造有缺陷的封裝，且因此，半導體裝置470的產量會提高以及總成本會下降。
增進互連結構456在半導體裝置470裡面提供額外的導體層。該些額外的導體層可用於連接至其它內部裝置(舉例來說，被動裝置436)或外部裝置。半導體裝置470裡面的嵌入式被動裝置436與412增加半導體裝置470的功能與電氣效能，但卻不會提高封裝輪廓。增進互連結構456 的導體層448與452係利用標準的Fo-eWLB製程以寬鬆的設計規則所形成。放寬增進互連結構456的設計規則允許在製作增進互連結構456中所使用的材料與製造技術有更大的靈活性。舉例來說，增進互連結構456能夠利用標準的Fo-eWLB設備及材料來形成，和製作具有超窄節距之導體層特有的材料不同。使用標準化設備及材料會縮短半導體裝置470的製造時間與成本。增進互連結構456裡面的導體線路的較寬節距同樣在凸塊458的擺放與節距中提供更大的靈活性。凸塊458的節距會經過選擇，以便反映工業標準。舉例來說，凸塊458能夠被形成具有和標準PCB上的互連觸墊相同的節距。於其中一實施例中，凸塊458的節距為0.4mm。放寬凸塊458的設計規則會提高半導體裝置470與外部裝置的相容性並且消弭額外基板或中介片的需求。
在犧牲基板370上形成細節距WL RDL 384、藉由晶片至晶圓模製法將WL RDL 384轉印至半導體晶粒390、以及利用標準Fo-eWLB製作過程在WLCSP 430上方形成增進互連結構456允許半導體裝置470併入具有高I/O需求及/或不同I/O需求的半導體晶粒，同時最小化半導體裝置470的大小、製造時間、以及成本。
圖8a至8i配合圖1以及2a至2c圖解形成一包含細節距RDL與嵌入式垂直互連單元的半導體裝置的製程。圖8a所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板480的一部分的剖視圖。一介面層或雙面膠帶482會被形成在載體480的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
在圖8b中，圖4l中的多個WLCSP 220被設置在載體480與介面層482的上方，絕緣層182朝向載體480。在圖8c中，複數個PCB模組式垂直互連單元484被設置在載體480與介面層482的上方。垂直互連單元484被設置圍繞WLCSP 220或是被設置在WLCSP 220的一周邊區域之中。垂直互連單元484可以相互鎖扣的圖樣被設置圍繞WLCSP 220，俾使得每一個WLCSP 220皆被數個垂直互連單元484包圍。於其中一實施例中，垂直互連單元484係單一的單元或薄板；或者，WLCSP 220被設置在多個開口之中，該些開口被形成貫穿或是擊穿該垂直互連單元。
垂直互連單元484包含一核心基板486。核心基板486包含由聚四氟乙烯膠片、FR-4、FR-1、CEM-1、或是CEM-3所製成的一或更多層疊層，其結合酚系棉紙、環氧樹脂、樹脂、織狀玻璃、毛面玻璃、聚酯、有填充劑的玻璃纖維、以及其它強化纖維或織物。或者，核心基板486包含一或更多個絕緣層或鈍化層。
複數個直通穿孔會利用雷射鑽鑿、機械鑽鑿、或是DRIE被形成貫穿核心基板486。該些穿孔會利用電解質電鍍製程、無電極電鍍製程、或是其它合宜的沉積製程來填充Al、Cu、Sn、Ni、Au、Ag、Ti、W、或是其它合宜的導電材料，以便形成z方向垂直互連線或導體穿孔488。於其中一實施例中，Cu藉由無電極電鍍與電致電鍍而被沉積在該些直通穿孔的側壁上方，而該些直通穿孔中的剩餘空間則被一絕緣或導體的填充劑材料填充。
一導電層或RDL 490會利用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在核心基板 486的表面與導體穿孔488的上方。導體層490包含由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層490被電氣連接至導體穿孔488。導體層490的操作如同被電氣連接至導體穿孔488的接觸墊。
一導電層或RDL 492會利用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在面對於導體層490的核心基板486的一表面的上方。導體層492包含由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層492被電氣連接至導體穿孔488以及導體層490。導體層492的操作如同被電氣連接至導體穿孔488的接觸墊。或者，導體穿孔488會在形成導體層490及/或導體層492之後才被形成貫穿核心基板486。
圖8d所示的係WLCSP 220與垂直互連單元484被鑲嵌至載體480而形成一重組式晶圓500。在圖8e中，一囊封體或模製化合物502會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在WLCSP 220以及垂直互連單元484的上方。囊封體502能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體502係非導體、提供物理性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體502還保護半導體晶粒124，避免因曝露於光中而受損。面對於背側表面504的囊封體502的一表面506被設置在載體480與介面層482上方，俾使得囊封體502的表面506共面於WLCSP 220的絕緣層182。
在圖8f中，載體480與介面層482會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，並且一增進互連結構522被形成在囊封體502的表面506、WLCSP 220、以及垂直互連單元484的上方。增進互連結構522包含絕緣層512、導體層514、絕緣層516、導體層518、以及絕緣層520。
絕緣層或鈍化層512會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在囊封體502的表面、WLCSP 220的絕緣層182、以及垂直互連單元484的上方。絕緣層512包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層512會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出WLCSP 220的絕緣層182以及垂直互連單元484的導體層492。
導電層或RDL 514會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層512的上方。導體層514能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層514會被電氣連接至WL RDL 194的導體層184。一部分的導體層514會被電氣連接至垂直互連單元484的導體層492。其它部分的導體層514則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。導體層514包含複數條導體線路。導體層514的該些導體線路被形成具有寬於WL RDL 194裡面的導體線路的節距。於其中一實施例中，導體層514的該些導體線路具有15μm或更大的節距。
絕緣層或鈍化層516會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層512以及導體層514的上方。絕緣層516包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層516會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層514。
導電層或RDL 518會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層516與導體層514的上方。導體層518能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層518會被電氣連接至WL RDL 194的導體層184。一部分的導體層518會被電氣連接至導體層514。其它部分的導體層518則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。導體層518包含複數條導體線路。導體層518的該些導體線路被形成具有寬於WL RDL 194中的導體層184與188的導體線路的節距。於其中一實施例中，導體層518的該些導體線路具有15μm或更大的節距。
絕緣層或鈍化層520會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層516以及導體層518的上方。絕緣層520包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層520係一防焊層。一部分的絕緣層520會藉由LDA、蝕刻、或是其它合宜的製程來 移除，用以露出導體層518。
絕緣層512、導體層514、絕緣層516、導體層518、以及絕緣層520會結合構成一增進互連結構522。增進互連結構522裡面所包含的絕緣層與導體層的數量相依於該電路繞送設計的複雜度並且隨著該電路繞送設計的複雜度而改變。據此，增進互連結構522能夠包含任何數量的絕緣層與導體層，用以促成相對於半導體晶粒124的電氣互連。增進互連結構522裡面的導體線路的較大節距以及寬鬆設計規則允許在增進互連結構522的製作中所使用的材料與製造技術有較大的靈活性並且降低製造成本。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層518的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層518。於其中一實施例中，該凸塊材料會藉由將該材料加熱至該材料的熔點以上而被回焊，用以形成球體或凸塊524。於某些應用中，凸塊524會被二次回焊，以便改良和導體層518的電氣接觸效果。於其中一實施例中，凸塊524被形成在一UBM層的上方。凸塊524亦能夠被壓縮焊接或熱壓縮焊接至導體層518。凸塊524代表能夠被形成在導體層518上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
在圖8g中，一部分的囊封體502利用研磨機526從囊封體502的表面504處被移除。該背研磨操作從半導體晶粒124的背表面128上 方移除囊封體502並且縮減重組式晶圓500的厚度。移除囊封體502同樣會降低重組式晶圓500的翹曲。於其中一實施例中，一部分的半導體晶粒124會在該背研磨操作期間從背表面128處被移除，用以進一步薄化重組式晶圓500。在背研磨之後，囊封體502會殘留在垂直互連單元484上方，並且囊封體502的一表面528共面於半導體晶粒124的表面128。介於囊封體502的表面528與導體層490之間的厚度D1為10μm至50μm。重組式晶圓500的雷射標記能夠在背研磨之後被實施，用以達到對齊、單體化裁切、及/或封裝辨識的目的。
在圖8h中，一部分的囊封體502會從垂直互連單元484的上方被移除，用以形成開口530。開口530包含一垂直或傾斜的側壁並且從囊封體502的表面528延伸至垂直互連單元484的導體層490。開口530係利用雷射532藉由LDA來形成、藉由蝕刻來形成、或是藉由其它合宜的製程來形成。藉由在半導體晶粒124的一周邊區域之中形成開口530貫穿囊封體502，一部分的導體層490會從囊封體502的背側露出。開口530會被配置成用以在半導體晶粒124以及堆疊於WLCSP 220上方的半導體晶粒或裝置(舉例來說，記憶體裝置、被動裝置、表面聲波濾波器(saw filter)、電感器、天線、…等)之間提供3-D電氣互連。於其中一實施例中，一拋光漆(例如，Cu有機保焊膜(Organic Solderability Preservative，OSP))會被塗敷至裸露的導體層490，用以防止Cu氧化。於一替代實施例中，焊膏會被印刷在導體層490的一表面上並且被回焊以便形成一帽部並且保護導體層490的該表面。於替代的實施例中，增進互連結構522與凸塊524會於形成開口530之後被形成在重組式晶圓500的上方。
在圖8i中，重組式晶圓500會利用鋸片或雷射削切工具534被單體化裁切貫穿增進互連結構522、垂直互連單元484的核心基板486、以及囊封體502而成為個別的半導體裝置538，其包含WLCSP 220、垂直互連單元484、以及增進互連結構522。
圖9所示的係在單體化裁切之後的半導體裝置538。半導體晶粒124經由WL RDL 194以及增進互連結構522被電氣連接至凸塊524，用以連接至外部裝置(舉例來說，PCB)。WL RDL 194在半導體晶粒124之間以及半導體晶粒124與增進互連結構522之間繞送電氣信號。增進互連結構522在WLCSP 220、垂直互連單元484、以及外部裝置之間繞送電氣信號。形成兩個分開的增進互連結構，也就是，WL RDL 194與增進互連結構522，允許WL RDL 194運用窄節距RDL製作技術來提高半導體裝置538的I/O與電氣效能，而增進互連結構522則運用標準Fo-eWLB製作技術來最小化成本並且提供額外的繞送至外部組件。WL RDL 194的導體層184與188係在附著半導體晶粒124之前先被形成在暫時性基板180的上方，從而提供節省成本的方式來形成可縮小至次微米尺寸(也就是，奈米範圍)之具有超窄節距的RDL。導體層184與188裡面的導體線路的窄節距允許在WL RDL 194裡面有較高密度的互連線。高密度的互連線在半導體裝置的整合中提供更大的靈活性並且容納具有不同凸塊節距的半導體晶粒，舉例來說，來自多種製造源頭的半導體晶粒。除此之外，導體線路的窄節距還會縮減WL RDL 194的大小並且縮短互連距離，也就是，電氣信號在半導體晶粒124與凸塊524之間必須前進的距離。較短的互連距離會提高半導體裝置538的速度與電氣效能。
相較於被用來形成TSV中介片封裝的製程，半導體裝置538裡面的WL RDL 194與增進互連結構522係利用更快速、更廉價、以及更低風險的製程來形成。除此之外，提供電氣互連而不必併入TSV中介片還會縮減半導體裝置538的體積與封裝輪廓。在增進互連結構522之前並且不相依地形成WLCSP 220則允許在鑲嵌WLCSP 220至基板480之前先測試半導體晶粒124之間的信號繞送以及WLCSP 220的功能。據此，僅有已知良好的WLCSP 220會被併入至半導體裝置538之中。僅使用已知良好的WLCSP 220來製作半導體裝置538會防止浪費製造時間與材料於製造有缺陷的封裝，且因此，半導體裝置538的產量會提高以及總成本會下降。
增進互連結構522在半導體裝置538裡面提供額外的導體層。該些額外的導體層可用於連接至其它內部裝置或外部裝置。囊封體502裡面的嵌入式垂直互連單元484為被設置在半導體裝置538上方的裝置提供電氣互連並且增加半導體裝置538的功能與電氣效能，但卻不會提高封裝輪廓。增進互連結構522的導體層514與518係利用標準的Fo-eWLB製程以寬鬆的設計規則所形成。放寬增進互連結構522的設計規則允許在製作增進互連結構522中所使用的材料與製造技術有更大的靈活性。舉例來說，增進互連結構522能夠利用標準的Fo-eWLB設備及材料來形成，和製作具有超窄節距之導體層特有的材料不同。使用標準化設備及材料會縮短半導體裝置538的製造時間與成本。增進互連結構522裡面的導體線路的較寬節距同樣在凸塊524的擺放與節距中提供更大的靈活性。凸塊524的節距會經過選擇，以便反映工業標準。舉例來說，凸塊524能夠被形成具有和標準PCB上的互連觸墊相同的節距。於其中一實施例中，凸塊524的節距為 0.4mm。放寬凸塊524的設計規則會提高半導體裝置538與外部裝置的相容性並且消弭額外基板或中介片的需求。
在犧牲基板180上形成細節距WL RDL 194、藉由晶片至晶圓模製法將WL RDL 194轉印至半導體晶粒124、以及利用標準Fo-eWLB製作過程在WLCSP 220與垂直互連單元484上方形成增進互連結構522允許半導體裝置538併入具有高I/O需求及/或不同I/O需求的半導體晶粒，同時最小化半導體裝置538的大小、製造時間、以及成本。
圖10a至10f配合圖1以及2a至2c圖解在一包含細節距RDL與嵌入式垂直互連單元的半導體裝置上方形成雙面RDL的製程。接續圖8e，圖10a所示的係重組式晶圓500，其包含被設置在載體480與介面層482上方的WLCSP 220與垂直互連單元484。囊封體502被設置在WLCSP 220與垂直互連單元484的上方。於其中一實施例中，一部分的囊封體502會在後續的背研磨操作中從囊封體502的表面504處被移除，雷同於圖8g。
一部分的囊封體502會從垂直互連單元484的上方被移除，用以形成開口510。開口510包含一垂直或傾斜的側壁並且從囊封體502的表面504延伸至垂直互連單元484的導體層490。開口510係藉由LDA、蝕刻、或是其它合宜的製程來形成。開口510被形成在半導體晶粒124的一周邊區域之中並且露出一部分的導體層490。
在圖10b中，絕緣層或鈍化層540會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在囊封體502與垂直互連單元484的上方。絕緣層540包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物 介電材料、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層540會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出垂直互連單元484的導體層490。
在圖10c中，導電層或RDL 542會使用PVD、CVD、電解質電鍍、或是無電極電鍍製程被形成在絕緣層540與導體層490的上方。導體層542能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、TiW/Cu、Ti/Cu、或是其它合宜的導電材料。一部分的導體層542會被電氣連接至WL RDL 194的導體層184。一部分的導體層542會被電氣連接至垂直互連單元484的導體層490。其它部分的導體層542則能夠相依於半導體晶粒124以及稍後鑲嵌的半導體晶粒或裝置的設計與功能而為共電或是被電氣隔離。
在圖10d中，絕緣層或鈍化層544會利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在絕緣層540以及導體層542的上方。絕緣層544包含由下面所製成的一或更多層：Si3N4、SiO2、SiON、SiO2/Si3N4、Ta2O5、Al2O3、聚合物介電質、低溫(小於250℃)固化聚合物介電材料、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層544係一防焊層。一部分的絕緣層544會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層542。導體層542的裸露部分提供3-D電氣互連並且幫助堆疊半導體晶粒或裝置(舉例來說，記憶體裝置、被動裝置、表面聲波濾波器、電感器、天線、…等)於WLCSP 220的上方。
在圖10e中，載體480與介面層482會藉由化學蝕刻、機械 性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，並且增進互連結構522被形成在囊封體502的表面506、WLCSP 220、以及垂直互連單元484的上方，該增進互連結構522包含絕緣層512、導體層514、絕緣層516、導體層518、以及絕緣層520。
在圖10f中，凸塊524被形成在導體層518的上方。凸塊524代表能夠被形成在導體層518上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。或者，增進互連結構522與凸塊524會在囊封體502之中形成開口510之前先被形成在重組式晶圓500的上方。重組式晶圓500的雷射標記能夠在凸塊成形之前或之後被實施，用以達到對齊、單體化裁切、及/或封裝辨識的目的。
圖10f進一步顯示重組式晶圓500利用鋸片或雷射削切工具546被單體化裁切貫穿增進互連結構522、垂直互連單元484的核心基板486、以及囊封體502而成為個別的半導體裝置550，其包含WLCSP 220、垂直互連單元484、以及雙面RDL(也就是，導體層542以及導體層514與518)。
圖11所示的係在單體化裁切之後的半導體裝置550。半導體晶粒124經由WL RDL 194以及增進互連結構522被電氣連接至凸塊524，用以連接至外部裝置(舉例來說，PCB)。WL RDL 194在半導體晶粒124之間以及半導體晶粒124與增進互連結構522之間繞送電氣信號。增進互連結構522在WLCSP 220、垂直互連單元484、以及外部裝置之間繞送電氣信號。形成兩個分開的增進互連結構，也就是，WL RDL 194與增進互連結構522，允許WL RDL 194運用窄節距RDL製作技術來提高半導體裝置550的I/O與 電氣效能，而增進互連結構522則運用標準Fo-eWLB製作技術來最小化成本並且提供額外的繞送至外部組件。WL RDL 194的導體層184與188係在附著半導體晶粒124之前先被形成在暫時性基板180的上方，從而提供節省成本的方式來形成可縮小至次微米尺寸(也就是，奈米範圍)之具有超窄節距的RDL。導體層184與188裡面的導體線路的窄節距允許在WL RDL 194裡面有較高密度的互連線。高密度的互連線在半導體裝置的整合中提供更大的靈活性並且容納具有不同凸塊節距的半導體晶粒，舉例來說，來自多種製造源頭的半導體晶粒。除此之外，導體線路的窄節距還會縮減WL RDL 194的大小並且縮短互連距離，也就是，電氣信號在半導體晶粒124與凸塊524之間必須前進的距離。較短的互連距離會提高半導體裝置550的速度與電氣效能。
相較於被用來形成TSV中介片封裝的製程，半導體裝置550裡面的WL RDL 194與增進互連結構522係利用更快速、更廉價、以及更低風險的製程來形成。除此之外，提供電氣互連而不必併入TSV中介片還會縮減半導體裝置550的體積與封裝輪廓。在增進互連結構522之前並且不相依地形成WLCSP 220則允許在鑲嵌WLCSP 220至基板480之前先測試半導體晶粒124之間的信號繞送以及WLCSP 220的功能。據此，僅有已知良好的WLCSP 220會被併入至半導體裝置550之中。僅使用已知良好的WLCSP 220來製作半導體裝置550會防止浪費製造時間與材料於製造有缺陷的封裝，且因此，半導體裝置550的產量會提高以及總成本會下降。
增進互連結構522在半導體裝置550裡面提供額外的導體層。該些額外的導體層可用於連接至其它內部裝置或外部裝置。囊封體502 裡面的嵌入式垂直互連單元484以及形成RDL於WLCSP 220的兩側(也就是，囊封體502的表面504上方的導體層542以及囊封體502的表面506上方的導體層514與518)幫助接續被設置在半導體裝置550上方的裝置進行電氣互連與堆疊。囊封體502裡面的嵌入式垂直互連單元484以及形成RDL於WLCSP 220的兩側會增加半導體裝置550的功能與電氣效能，但卻不會提高封裝輪廓。增進互連結構522的導體層514與518係利用標準的Fo-eWLB製程以寬鬆的設計規則所形成。放寬增進互連結構522的設計規則允許在製作增進互連結構522中所使用的材料與製造技術有更大的靈活性。舉例來說，增進互連結構522能夠利用標準的Fo-eWLB設備及材料來形成，和製作具有超窄節距之導體層特有的材料不同。使用標準化設備及材料會縮短半導體裝置550的製造時間與成本。增進互連結構522裡面的導體線路的較寬節距同樣在凸塊524的擺放與節距中提供更大的靈活性。凸塊524的節距會經過選擇，以便反映工業標準。舉例來說，凸塊524能夠被形成具有和標準PCB上的互連觸墊相同的節距。於其中一實施例中，凸塊524的節距為0.4mm。放寬凸塊524的設計規則會提高半導體裝置550與外部裝置的相容性並且消弭額外基板或中介片的需求。
在犧牲基板180上形成細節距WL RDL 194、藉由晶片至晶圓模製法將WL RDL 194轉印至半導體晶粒124、以及利用標準Fo-eWLB製作過程在WLCSP 220與垂直互連單元484上方形成增進互連結構522允許半導體裝置550併入具有高I/O需求及/或不同I/O需求的半導體晶粒，同時最小化半導體裝置550的大小、製造時間、以及成本。
圖12所示的係半導體裝置560，雷同於圖11中的半導體裝 置550。半導體裝置560包含被設置在囊封體502裡面的半導體組件或被動裝置562。被動裝置562被電氣連接至增進互連結構522。被嵌入在半導體裝置560裡面的被動裝置562會提高半導體裝置560的功能與電氣效能。
半導體晶粒124經由WL RDL 194以及增進互連結構522被電氣連接至凸塊524，用以連接至外部裝置。WL RDL 194在半導體晶粒124之間以及半導體晶粒124與增進互連結構522之間繞送電氣信號。增進互連結構522在WLCSP 220、被動裝置562、垂直互連單元484、以及外部裝置(舉例來說，PCB)之間繞送電氣信號。形成兩個分開的增進互連結構，也就是，WL RDL 194與增進互連結構522，允許WL RDL 194運用窄節距RDL製作技術來提高半導體裝置550的I/O與電氣效能，而增進互連結構522則運用標準Fo-eWLB製作技術來最小化成本並且提供額外的繞送至外部組件。WL RDL 194的導體層184與188係在附著半導體晶粒124之前先被形成在暫時性基板180的上方，從而提供節省成本的方式來形成可縮小至次微米尺寸(也就是，奈米範圍)之具有超窄節距的RDL。導體層184與188裡面的導體線路的窄節距允許在WL RDL 194裡面有較高密度的互連線。高密度的互連線在半導體裝置的整合中提供更大的靈活性並且容納具有不同凸塊節距的半導體晶粒，舉例來說，來自多種製造源頭的半導體晶粒。除此之外，導體線路的窄節距還會縮減WL RDL 194的大小並且縮短互連距離，也就是，電氣信號在半導體晶粒124與凸塊524之間必須前進的距離。較短的互連距離會提高半導體裝置560的速度與電氣效能。
相較於被用來形成TSV中介片封裝的製程，半導體裝置560裡面的WL RDL 194與增進互連結構522係利用更快速、更廉價、以及更低 風險的製程來形成。除此之外，提供電氣互連而不必併入TSV中介片還會縮減半導體裝置560的體積與封裝輪廓。在增進互連結構522之前並且不相依地形成WLCSP 220則允許在鑲嵌WLCSP 220至基板480之前先測試半導體晶粒124之間的信號繞送以及WLCSP 220的功能。據此，僅有已知良好的WLCSP 220會被併入至半導體裝置560之中。僅使用已知良好的WLCSP 220來製作半導體裝置560會防止浪費製造時間與材料於製造有缺陷的封裝，且因此，半導體裝置560的產量會提高以及總成本會下降。
增進互連結構522在半導體裝置560裡面提供額外的導體層。該些額外的導體層可用於連接至其它內部裝置(舉例來說，被動裝置562)或外部裝置。囊封體502裡面的嵌入式垂直互連單元484以及形成RDL於WLCSP 220的兩側(也就是，囊封體502的表面504上方的導體層542以及囊封體502的表面506上方的導體層514與518)幫助接續被設置在半導體裝置560上方的裝置進行電氣互連與堆疊。囊封體502裡面的嵌入式垂直互連單元484以及形成RDL於WLCSP 220的兩側會增加半導體裝置560的功能與電氣效能，但卻不會提高封裝輪廓。增進互連結構522的導體層514與518係利用標準的Fo-eWLB製程以寬鬆的設計規則所形成。放寬增進互連結構522的設計規則允許在製作增進互連結構522中所使用的材料與製造技術有更大的靈活性。舉例來說，增進互連結構522能夠利用標準的Fo-eWLB設備及材料來形成，和製作具有超窄節距之導體層特有的材料不同。使用標準化設備及材料會縮短半導體裝置560的製造時間與成本。增進互連結構522裡面的導體線路的較寬節距同樣在凸塊524的擺放與節距中提供更大的靈活性。凸塊524的節距會經過選擇，以便反映工業標準。舉例來說， 凸塊524能夠被形成具有和標準PCB上的互連觸墊相同的節距。於其中一實施例中，凸塊524的節距為0.4mm。放寬凸塊524的設計規則會提高半導體裝置560與外部裝置的相容性並且消弭額外基板或中介片的需求。
在犧牲基板180上形成細節距WL RDL 194、藉由晶片至晶圓模製法將WL RDL 194轉印至半導體晶粒124、以及利用標準Fo-eWLB製作過程於WLCSP 220、垂直互連單元484、以及被動裝置562上方形成增進互連結構522允許半導體裝置560併入具有高I/O需求及/或不同I/O需求的半導體晶粒，同時最小化半導體裝置560的大小、製造時間、以及成本。
本文雖然已經詳細解釋本發明的一或更多個實施例；但是，熟習本技術的人士便會明白，可以對此些實施例進行修正與更動，其並不會脫離如後面的申請專利範圍之中所提出之本發明的範疇。
124‧‧‧半導體晶粒或組件
128‧‧‧背表面或非主動表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣層或鈍化層
150‧‧‧導電層或重新分佈層(RDL)
152‧‧‧絕緣層或鈍化層
160‧‧‧導電層
164‧‧‧導體柱
166‧‧‧凸塊帽部
168‧‧‧互連結構
182‧‧‧絕緣層或鈍化層
184‧‧‧導電層或重新分佈層(RDL)
186‧‧‧絕緣層或鈍化層
188‧‧‧導電層或重新分佈層(RDL)
190‧‧‧絕緣層或鈍化層
192‧‧‧凸塊
194‧‧‧晶圓級重新分佈層(WL RDL)或增進互連結構
198‧‧‧囊封體或模製化合物
200‧‧‧表面
220‧‧‧晶圓級晶片尺寸封裝(WLCSP)
236‧‧‧囊封體或模製化合物
238‧‧‧表面
239‧‧‧表面
240‧‧‧絕緣層或鈍化層
242‧‧‧導電層或重新分佈層(RDL)
244‧‧‧絕緣層或鈍化層
246‧‧‧導電層或重新分佈層(RDL)
248‧‧‧絕緣層或鈍化層
250‧‧‧增進互連結構
252‧‧‧球體或凸塊
260‧‧‧半導體裝置

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供一第一導體層；設置一第一半導體晶粒於該第一導體層上方；設置一第一囊封體於該第一半導體晶粒與第一導體層上方；設置一第二囊封體於該第一囊封體上方；以及形成一第二導體層於該第一導體層與第二囊封體上方。
  2. 根據申請專利範圍第1項的方法，其進一步包含設置一被動裝置於該第一囊封體之中。
  3. 根據申請專利範圍第1項的方法，其進一步包含設置一被動裝置於該第二囊封體之中。
  4. 根據申請專利範圍第1項的方法，其進一步包含設置一第二半導體晶粒於該第一導體層上方。
  5. 根據申請專利範圍第1項的方法，其進一步包含設置一垂直互連單元於該第一半導體晶粒的一周邊區域之中。
  6. 一種製造半導體裝置的方法，其包括：提供一第一導體層；設置一第一半導體晶粒於該第一導體層上方；設置一第一囊封體於該第一半導體晶粒上方；以及形成一第二導體層於面對於該第一半導體晶粒的該第一導體層上方。
  7. 根據申請專利範圍第6項的方法，其進一步包含設置一第二半導體晶粒於該第一導體層上方。
  8. 根據申請專利範圍第6項的方法，其進一步包含設置一被動裝置於該第一半導體晶粒的一周邊區域之中。
  9. 根據申請專利範圍第6項的方法，其進一步包含：設置一垂直互連單元於該第一半導體晶粒的一周邊區域之中；以及沉積一第二囊封體於該垂直互連單元上方。
  10. 根據申請專利範圍第6項的方法，其中，該第一導體層包含複數條第一導體線路以及該第二導體層包含複數條第二導體線路，並且該些第一導體線路的節距小於該些第二導體線路的節距。
  11. 一種半導體裝置，其包括：一第一導體層，其包含複數條第一導體線路；一第一半導體晶粒，其被設置在該第一導體層的一第一表面上方；以及一第二導體層，其包含複數條第二導體線路，其被設置在面對於該第一導體層之第一表面的該第一導體層的一第二表面上方，其中，該些第一導體線路的節距小於該些第二導體線路的節距。
  12. 根據申請專利範圍第11項的半導體裝置，其進一步包含一第一囊封體，其被沉積在該第一半導體晶粒與第一導體層上方。
  13. 根據申請專利範圍第12項的半導體裝置，其進一步包含一第二囊封體，其被設置在該第一囊封體上方。
  14. 根據申請專利範圍第11項的半導體裝置，其進一步包含一垂直互連單元，其被設置在該第一半導體晶粒的一周邊區域之中。
  15. 根據申請專利範圍第11項的半導體裝置，其進一步包含一第二半導 體晶粒，其被設置在該第一導體層上方。
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