TWI701722B - 形成具有垂直互連單元的低輪廓扇出封裝的半導體裝置及方法 - Google Patents

形成具有垂直互連單元的低輪廓扇出封裝的半導體裝置及方法 Download PDF

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TWI701722B
TWI701722B TW102141021A TW102141021A TWI701722B TW I701722 B TWI701722 B TW I701722B TW 102141021 A TW102141021 A TW 102141021A TW 102141021 A TW102141021 A TW 102141021A TW I701722 B TWI701722 B TW I701722B
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semiconductor
semiconductor die
layer
interconnection
die
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TW102141021A
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TW201423851A (zh
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潘迪Ｃ 瑪莉姆蘇
沈一權
林耀劍
崔源璟
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新加坡商史達晶片有限公司
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Abstract

本發明提供一種半導體裝置，其包含一半導體晶粒。一第一互連結構被設置在該半導體晶粒的一周邊區域上方。一半導體構件被設置在該半導體晶粒上方。該半導體構件包含一第二互連結構。該半導體構件係被設置在該半導體晶粒上方，以便對齊該第二互連結構和該第一互連結構。該第一互連結構包含複數個互連單元，該複數個互連單元被設置圍繞該半導體晶粒的第一與第二相鄰側邊，以便形成圍繞該半導體晶粒之該些互連單元的L形邊界。一第三互連結構被形成在該半導體晶粒上方，垂直於該第一互連結構。一絕緣層會被形成在該半導體晶粒和第一互連結構上方。複數個通孔會被形成貫穿該絕緣層並且被形成在該第一互連結構之中，該第二互連結構則被設置在該些通孔裡面。

Description

形成具有垂直互連單元的低輪廓扇出封裝的半導體裝置及方法
本發明大體上和半導體裝置有關，且更明確地說，本發明係關於形成具有垂直互連單元的扇出封裝或封裝上封裝半導體裝置的半導體裝置及方法。
優先權之主張
本申請案主張2012年12月11日所提申之美國臨時申請案第61/735,926號的權利，本文以引用的方式將此申請案併入。
在現代的電子產品中經常發現半導體裝置。半導體裝置會有不同數量與密度的電構件。離散式半導體裝置通常含有一種類型的電構件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電構件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數 位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的結構使得可藉由施加電場或基極電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至半導體材料之中，以便操縱及控制半導體裝置的傳導性。
半導體裝置含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基極電流，電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該些被動式結構與主動式結構會被電連接以形成讓半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個半導體晶粒通常相同並且含有藉由電連接主動式構件和被動式構件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒，用以提供結構性支撐以及環境隔離。本文中所使用的「半導體晶粒(semiconductor die)」一詞兼 具單數和複數形式，且據此會表示單一半導體裝置以及多個半導體裝置兩者。
半導體製造的其中一個目標便係生產較小型的半導體裝置。較小型裝置通常會消耗較少的電力，具有較高的效能，並且能夠被更有效地生產。此外，較小型的半導體裝置還具有較小的覆蓋區，這係較小型末端產品所需要的。藉由改良前端製程能夠達成較小的半導體晶粒尺寸，從而導致具有較小尺寸以及較高密度之主動式構件和被動式構件的半導體晶粒。後端製程可以藉由改良電互連材料及封裝材料而導致具有較小覆蓋區的半導體裝置封裝。
小封裝輪廓對在蜂巢式電話或智慧型電話產業中進行封裝特別重要。三維(3D)扇出半導體封裝及外部裝置之間的電氣互連運用各種互連類型，例如，藉由藉由重新分配層(ReDistribution Layer，RDL)互連的直通矽通孔(Through Silicon Via，TSV)以及直通孔洞通孔(Through Hole Via，THV)。RDL充當一包含具有封裝輸入/輸出(Input/Output，I/O)觸墊之電互連線的封裝裡面用於電氣互連的中間層，該些輸入/輸出觸墊提供從一半導體封裝裡面的一半導體晶粒至該半導體封裝之外部點的電氣互連。RDL被形成在該半導體封裝裡面該半導體晶粒的前表面和背表面兩者上方並且具有薄晶圓和平板處理能力。然而，在半導體晶粒的前表面和背表面上方形成多個RDL會需要以客製焊接材料進行暫時性焊接，其會需要耐受較高的溫度並且會係一種用以製造用於半導體封裝之電互連的緩慢且成本昂貴的方式，從而導致較高的製作成本。除此之外，RDL的薄型堆疊會有結構上限制以及低設計彈性。舉例來說，RDL提供有限的封裝處理機械性強度以及 可靠度。RDL缺乏模組性並且難以形成在半導體封裝的特定區域中。
本技術領域需要形成一種具有減少RDL應用之低輪廓3D半導體封裝結構。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一半導體晶粒；沿著該半導體晶粒的一周邊區域設置一第一模組式互連結構；提供一半導體構件，其包含一被形成在該半導體構件上方的第二互連結構；以及設置該半導體構件於該半導體晶粒上方，以便對齊該第二互連結構和該第一模組式互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一半導體晶粒；以及沿著該半導體晶粒的第一側邊和第二側邊設置一模組式互連結構。
於另一實施例中，本發明係一種半導體裝置，其包括一半導體晶粒以及被形成在該半導體晶粒的一表面上方的第一互連結構。一第二互連結構會沿著該半導體晶粒的一周邊區域並且垂直於該第一互連結構被設置。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧訊號線路
56‧‧‧焊線封裝
58‧‧‧覆晶
60‧‧‧球柵陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙直列封裝(DIP)
66‧‧‧平台格柵陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧方形扁平無導線封裝(QFN)
72‧‧‧方形扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導體導線
82‧‧‧焊線
84‧‧‧囊封體
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底層填充材料或環氧樹脂膠黏材料
94‧‧‧焊線
96‧‧‧接觸墊
98‧‧‧接觸墊
100‧‧‧模製化合物或囊封體
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中間載體
108‧‧‧主動區
110‧‧‧凸塊
112‧‧‧凸塊
114‧‧‧訊號線
116‧‧‧模製化合物或囊封體
120‧‧‧半導體晶圓
122‧‧‧基礎基板材料
124‧‧‧半導體晶粒或構件
126‧‧‧切割道
128‧‧‧背表面或非主動表面
130‧‧‧主動表面
132‧‧‧導體層
134‧‧‧絕緣層或鈍化層
135‧‧‧雷射
136‧‧‧開口
138‧‧‧鋸片或雷射削切工具
140‧‧‧載體或暫時性基板
142‧‧‧介面層或雙面膠帶
150‧‧‧晶粒附接區
152‧‧‧間隙或空間
160‧‧‧囊封體或模製化合物
170‧‧‧合成基板或重組晶圓
174‧‧‧絕緣層或鈍化層
180‧‧‧導體層
182‧‧‧絕緣層或鈍化層
184‧‧‧導體層
186‧‧‧絕緣層或鈍化層
188‧‧‧球體或凸塊
190‧‧‧互連結構
202‧‧‧載體或暫時性基板
206‧‧‧研磨機
210‧‧‧絕緣層
216‧‧‧通孔或開口
224‧‧‧球體或凸塊
226‧‧‧鋸片或雷射削切工具
227‧‧‧半導體封裝
228‧‧‧載體
230‧‧‧半導體封裝、半導體晶粒、或是半導體構件
252‧‧‧背表面
254‧‧‧主動表面
255‧‧‧絕緣層或鈍化層
256‧‧‧導體層
258‧‧‧球體或凸塊
260‧‧‧底層填充材料
261‧‧‧晶粒附接區
300‧‧‧半導體封裝
306‧‧‧半導體封裝
308‧‧‧載體或暫時性基板
310‧‧‧介面層或雙面膠帶
312‧‧‧互連層
316‧‧‧絕緣層或鈍化層
318‧‧‧導電層
320‧‧‧絕緣層或鈍化層
322‧‧‧導體層
323‧‧‧核心基板
324‧‧‧導體通孔
325‧‧‧囊封體或模製化合物
326‧‧‧模組式互連單元或互連結構
327‧‧‧絕緣層
330‧‧‧增進互連結構
332‧‧‧絕緣層或鈍化層
334‧‧‧導體層
336‧‧‧導體層
338‧‧‧凹腔
340‧‧‧底層填充材料
346‧‧‧機械性支撐層
348‧‧‧球體或凸塊
350‧‧‧半導體封裝
352‧‧‧LGA觸墊
362‧‧‧絕緣層
363‧‧‧導體層
364‧‧‧模組式互連單元或互連結構
366‧‧‧互連層
367‧‧‧絕緣層或鈍化層
368‧‧‧導體層
370‧‧‧導體層
372‧‧‧囊封體或模製化合物
374‧‧‧互連層
375‧‧‧絕緣層或鈍化層
376‧‧‧導體層
378‧‧‧導體層
380‧‧‧機械性支撐層
382‧‧‧增進互連結構
383‧‧‧絕緣層或鈍化層
384‧‧‧導體層
385‧‧‧絕緣層或鈍化層
386‧‧‧導體層
388‧‧‧絕緣層或鈍化層
390‧‧‧開口
392‧‧‧球體或凸塊
400‧‧‧半導體封裝
572‧‧‧核心基板
574‧‧‧直通導體通孔
575‧‧‧直通導體通孔
576‧‧‧導體層
578‧‧‧絕緣層或鈍化層
580‧‧‧導體層
582‧‧‧絕緣層或鈍化層
600‧‧‧模組式3D互連單元
圖1所示的係一印刷電路板(PCB)，在其表面安裝著不同類型的封裝；圖2a至2c所示的係被安裝至該PCB的代表性半導體封裝的進一步細節；圖3a至3c所示的係具有藉由切割道分離之複數個半導體晶粒的半導體晶圓； 圖4a至4n所示的係用於形成具有垂直互連單元的低輪廓扇出封裝上封裝結構的製程；圖5所示的係一具有互連單元的健全半導體封裝；圖6a至6h所示的係具有被設置在一半導體晶粒之相反表面上方的互連單元以及支撐結構的另一半導體封裝；圖7所示的係具有LGA觸墊之半導體封裝的替代實施例；以及圖8a至8g所示的係具有被形成在半導體封裝之間的RDL以及一背表面保護層的另一半導體封裝。
在下面的說明中參考圖式於一或更多個實施例中說明本發明，於該些圖式中，相同的符號代表相同或雷同的元件。雖然本文以達成本發明之目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可以併入的替代例、修正例、以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電構件和被動式電構件，它們會被電連接而形成功能性電路。主動式電構件(例如電晶體與二極體)能夠控制電流的流動。被動式電構件(例如電容器、電感器、以及電阻器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式構件和主動式構件會藉由一連串的製程步驟被形成 在該半導體晶圓的表面上方，該些製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會藉由響應於電場或基極電流來動態改變半導體材料傳導性而修正主動式裝置中半導體材料的導電性。電晶體含有不同類型及不同摻雜程度的多個區域，它們會在必要時被排列成用以在施加電場或基極下讓該電晶體提高或限制電流的流動。
主動式構件和被動式構件係由具有不同電氣特性的多層材料構成。該些層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式構件、被動式構件、或是構件之間的電連接線的一部分。
後端製造係指將已完成的晶圓切割或單體化裁切成個別的晶粒，並且接著封裝該半導體晶粒，以達結構性支撐以及環境隔離的效果。為單體化裁切半導體晶粒，該晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別半導體晶粒便會被安裝至包含接針或接觸墊的封裝基板，以便和其它系統構件進行互連。被形成在該半導體晶粒上方的接觸墊接著會被連接至該封裝裡面的接觸墊。該些電連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封體或是其它模製材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，已完成的封裝便會被插入一電氣系統之中並且讓其它系 統構件可取用該半導體裝置的功能。
圖1圖解電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上安裝著複數個半導體封裝。電子裝置50會具有某一種類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋的目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係獨立式系統，其使用該些半導體封裝來實施一或更多項電功能。或者，電子裝置50亦可能係一較大型系統中的子構件。舉例來說，電子裝置50可能係蜂巢式電話、個人數位助理(Personal Digital Assistant，PDA)、數位錄像機(Digital Video Camera，DVC)、或是其它電子通信裝置的一部分。或者，電子裝置50可能係圖形卡、網路介面卡、或是能夠被插入在電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻(Radio Frequency，RF)電路、離散式裝置、或是其它半導體晶粒或電構件。該些產品要被市場接受，微型化以及減輕重量相當重要。半導體裝置之間的距離必須縮小，以達更高密度的目的。
在圖1中，PCB 52提供一通用基板，用以達到結構性支撐以及電互連被安裝在該PCB上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該些半導體封裝、被安裝的構件、以及其它外部系統構件中的每一者之間提供電通訊。線路54還提供連接至每一個該些半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載體的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載體附接至該PCB。於其它實施例中，一半導體裝置可以僅有該第一層封裝，其中，該晶粒係以機械方式及電氣方式直接被安裝至該PCB。
為達解釋的目的，圖中在PCB 52上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被安裝在PCB 52上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載體(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合的半導體封裝和其它電子構件所組成的任何組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則會需要多個互連封裝。藉由在單一基板上方組合一或更多個半導體封裝，製造商便能夠將預先製造的構件併入電子裝置和系統之中。因為該些半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的構件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而降低消費者的成本。
圖2a至圖2c所示的係示範性半導體封裝。圖2a所示的係被安裝在PCB 52上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該些類比電路或數位電路會被施行為形成在 該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76係由導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))所製成的一或更多層，並且被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂或是環氧樹脂)被安裝至中間載體78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與PCB 52之間提供電互連。囊封體84會被沉積在該封裝的上方，用以藉由防止濕氣和粒子進入封裝並且防止污染晶粒74或焊線82而達到環境保護的目的。
圖2b所示的係被安裝在PCB 52之上的BCC 62的進一步細節。半導體晶粒88係利用底層填充材料或環氧樹脂膠黏材料92被安裝在載體90的上方。焊線94會在接觸墊96與98之間提供第一層封裝互連。模製化合物或囊封體100係被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的表面上方，用以防止氧化。接觸墊102會被電連接至PCB 52中的一或更多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸墊98和PCB 52的接觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被安裝至中間載體106。半導體晶粒58的主動區108含有類 比電路或數位電路，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可能包含在主動區108裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載體106。
BGA 60會以利用多個凸塊112的BGA樣式第二層封裝，以電氣方式及機械方式被連接至PCB 52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電連接至PCB 52中的導體訊號線路54。一模製化合物或囊封體116會被沉積在半導體晶粒58和載體106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會從半導體晶粒58上的主動式裝置至PCB 52上的傳導軌提供一條短電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改良整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至PCB 52，而沒有中間載體106。
圖3a所示的係半導體晶圓120，其具有基礎基板材料122(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或構件124會被形成在晶圓120上，藉由如上面所述之沒有作用的晶粒間晶圓區域或切割道126來分離。切割道126提供削切區，以便將半導體晶圓120單體化裁切成個別的半導體晶粒124。
圖3b所示的係半導體晶圓120的一部分的剖視圖。每一個半導體晶粒124皆具有一背表面或非主動表面128以及含有類比電路或數位電路的主動表面130，該些類比電路或數位電路會被施行為根據該晶粒的電 氣設計與功能被形成在該晶粒裡面及電互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面130裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可以還含有用於RF訊號處理的整合式被動裝置(Integrated Passive Device，IPD)，例如，電感器、電容器、以及電阻器。
一導電層132會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面130的上方。導體層132可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層132的操作如同被電連接至主動表面130上之電路的接觸墊。導體層132會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒124的邊緣相隔第一距離處，如圖3b之中所示。或者，導體層132會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。
一非必要的絕緣層或鈍化層134係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在主動表面130的上方。絕緣層134含有由下面所製成的一或更多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)、或是具有雷同絕緣特性及結構特性的其它介電材料。絕緣層134會覆蓋並且保護主動表面130。絕緣層134中的一部分會藉由蝕刻製程或是藉由利用雷射135的雷射直接 燒蝕(Laser Direct Ablation，LDA)被移除，用以形成開口136，該些開口會露出導體層132並且提供用於後續的電互連。
半導體晶圓120會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓120上實施檢查。軟體會被使用在半導體晶圓120的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓120的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。
半導體晶粒124裡面的主動式構件和被動式構件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒124係利用一探針或是其它測試裝置來測試功能與電氣參數。探針係被用來電接觸每一個半導體晶粒124上的節點或接觸墊132並且提供電氣刺激給該些接觸墊。半導體晶粒124會回應該些電氣刺激，該回應會被測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻率、連續性、可靠度、接面深度、靜電放電(Electric-Static Discharge，ESD)、射頻(Radio Frequency，RF)效能、驅動電流、臨界電流、漏電流、以及該構件類型特有的操作參數。半導體晶圓120的檢查與電氣測試可讓通過而被指定為已知良品晶粒(Known Good Die，KGD)的半導體晶粒124可用於半導體封裝中。
在圖3c中，半導體晶圓120會利用鋸片或雷射削切工具138貫穿切割道126被單體化裁切成個別的半導體晶粒124。個別的半導體晶粒124會被檢查與電氣測試，以便找出單體化裁切後的KGD。
圖4a至4n配合圖1以及2a至2c顯示用以利用預先製作的模組式互連單元來形成低輪廓3D半導體封裝結構的製程。圖4a顯示一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板140的一部分的剖視圖。一介面層或雙面膠帶142會被形成在載體140的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
載體140可能係一圓形或矩形平板(大於300mm)，含有多個半導體晶粒124。載體140的表面積可以大於半導體晶圓120的表面積。較大的載體會降低半導體封裝的製造成本，因為較多半導體晶粒能夠在較大的載體上被處理，因而降低單位成本。半導體封裝和處理設備係針對被處理的晶圓或載體的大小來進行設計與配置。
為進一步降低製造成本，載體140的大小係以和半導體晶粒124的大小無關或是和半導體晶圓120的大小無關的方式被選擇。也就是，載體140具有固定或標準化大小，其能夠容納從一或更多個半導體晶圓120處單體化裁切下來之各種大小的半導體晶粒124。於其中一實施例中，載體140為直徑330mm的圓形。於另一實施例中，載體140為寬度560mm且長度為600mm的矩形。半導體晶粒124可以有10mm乘10mm的面積，其係被放置在標準化載體140上。或者，半導體晶粒124可以有20mm乘20mm的面積，其係被放置在相同的標準化載體140上。據此，標準化載體140能夠應付任何大小的半導體晶粒124，其允許後續的半導體處理設備以一共同載體為基準被標準化，也就是，和晶粒大小或進料晶圓大小無關。半導體封裝設備能夠利用一組共同的處理治具、設備、以及材料清單針對一標 準載體來進行設計與配置，以便處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體140因減少或消弭以晶粒大小或進料晶圓大小為基礎之特殊半導體處理線的需求而降低製造成本和資本風險。藉由選擇用於來自所有半導體晶圓之任何大小半導體晶粒的預設載體大小，一種彈性的製造線便能夠被施行。
在圖4b中，舉例來說，圖3c中的半導體晶粒124會利用拾放操作被安裝至載體140的晶粒附接區150，主動表面130配向成朝向該載體。被安裝至晶粒附接區150的半導體晶粒124可以選自KGD。半導體晶粒124會被擠壓至介面層142，俾使得一部分的絕緣層134被設置在該介面層裡面並且被該介面層包圍。
圖4b還顯示預先製作的模組式3D互連單元600，其包含核心基板572，複數個直通導體通孔574至575會被形成貫穿該核心基板。一導電層或RDL 576會使用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程被形成在核心基板572以及導體通孔574至575的上方。導體層576包含由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層576會被電連接至導體通孔574至575。
一絕緣層或鈍化層578會利用下面方法被形成在核心基板572和導體層576的上方：PVD、CVD、印刷、旋塗、噴塗、狹縫式塗佈(slit coating)、滾塗、層疊、燒結、或是熱氧化。絕緣層578包含由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、具有或是不具有填充劑或纖維的聚合物介電質光阻、或是具有雷同結構特 性及介電特性的其它材料。一部分的絕緣層578會藉由LDA、蝕刻、或是其它合宜的製程來移除，以便露出導體通孔574上方的導體層576部分。
一絕緣層或鈍化層582會利用下面方法被形成在核心基板572的上方：PVD、CVD、印刷、旋塗、噴塗、狹縫式塗佈、滾塗、層疊、燒結、或是熱氧化。絕緣層582包含由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、具有或是不具有填充劑或纖維的聚合物介電質光阻、或是具有雷同結構特性及介電特性的其它材料。一部分的絕緣層582會藉由LDA或是蝕刻來移除，以便露出一部分的導體通孔574至575。
一導電層或RDL 580會使用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程被形成在和導體層576反向的核心基板572以及導體通孔574的上方。導體層580包含由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、Ti、W、或是其它合宜的導電材料。導體層580會被電連接至導體通孔574。或者，導體通孔574會在形成導體層576和導體層580之後被形成貫穿核心基板572。
舉例來說，模組式互連單元600會利用拾放操作被安裝至載體140，其會配合非必要的黏著劑。互連單元600會被設置在半導體晶粒124的一周邊區域中的介面層142之上。互連單元600係以L形排列被設置在晶粒附接區150的一角落周圍的載體140上方並且至少部分沿著半導體晶粒124之兩個側邊的長度，如圖4c中所示。互連單元600可以聚集在一起而形成一連續的互連單元層，或者被設置在載體140上方之隔離且預設的部分上方。於某些實施例中，半導體晶粒124係在安裝互連單元600之前被安 裝至載體140。或者，互連單元600係在安裝半導體晶粒124之前被安裝至載體140。半導體晶粒124和互連單元600能夠同時被安裝至載體140。
互連單元600係一模組式垂直互連構件，它們會輕易地被設置在一半導體封裝裡面，用以在半導體晶粒124的一側邊部分的上方或周圍形成一邊界、狹孔、或是框架。模組式互連單元600係被設置在半導體晶粒124周圍，用以提供垂直互連，同時減少被形成在該半導體封裝裡面的RDL的數量或數額。舉例來說，互連單元600在製造步驟期間以改良的效率提供部分背側RDL。被設置在半導體晶粒124周圍的互連單元600還在封裝期間提供結構性支撐並且在塗敷囊封體及額外半導體構件期間減少移動。互連單元600延伸設計彈性並且降低z方向封裝高度，同時提供有用的垂直互連。作為個別的模組式單元，互連單元600會被設置在該半導體封裝裡面半導體晶粒124周圍的特定預設位置處，以便最佳化該半導體封裝裡面的空間。利用互連單元600會減少製造步驟，並且大幅增加半導體封裝設計彈性。
於某些實施例中，互連單元600的高度大於半導體晶粒124的高度或厚度。於其它實施例中，互連單元600的高度等於或小於該半導體晶粒的高度或厚度。當安裝相鄰於半導體晶粒124的互連單元時，一間隙或空間152可以殘留在晶粒附接區150和互連單元600之間的晶粒附接區150周圍。或者，晶粒附接區150會被分配成讓半導體晶粒124鄰接或接觸互連單元600。
圖4d所示的係囊封體160被沉積在半導體晶粒124和互連單元600上方的合成基板或重組晶圓170。重組晶圓170會被處理成許多類 型的半導體封裝，其包含：三維(3D)封裝，例如，封裝上封裝(Package-on-Package，PoP)；嵌入式晶圓級球柵陣列(embedded Wafer Level Ball grid array，eWLB)；扇入晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package，WLCSP)；重組或嵌入式晶圓級晶片尺寸封裝(embedded Wafer Level Chip Scale Package，eWLCSP)；扇出WLCSP；覆晶封裝；或是其它半導體封裝。重組晶圓170係根據所生成的半導體封裝的規格來配置。載體140上的半導體晶粒294之間的距離經過最佳化，以便以最低的單位成本來製造半導體封裝。載體140的較大表面積容納較多的半導體晶粒124並且降低製造成本，因為每個重組晶圓170中有較多半導體晶粒124被處理。被安裝至載體140的半導體晶粒124的數量會大於從半導體晶圓120處單體化裁切下來的半導體晶粒124的數量。載體140和重組晶圓170提供利用來自不同大小半導體晶圓120之不同大小半導體晶粒124製造許多不同類型半導體封裝的彈性。
囊封體或模製化合物160會利用擠壓模製(compressive molding)塗敷機、轉印模製(transfer molding)塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124和互連單元600的上方。或者，囊封體160會於一模套中被形成在重組晶圓170的上方。囊封體160可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體160係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。在沉積囊封體160之前，重組晶圓170可以先進行高壓退火製程。囊封體160會被形成在半導體晶粒124的背表面128上方，並 且會在後續的背面研磨步驟中被薄化。囊封體160亦能夠被沉積成使得該囊封體和背表面128共面。半導體晶粒124周圍的互連單元600會減少囊封期間半導體晶粒124的移動並且在封裝期間提供結構性支撐。
在圖4e中，載體140和介面層142會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除從重組晶圓170處被移除，用以露出導體層132、互連單元600、以及囊封體160。亦可以使用非必要的清洗製程，例如，雷射清洗、乾式電漿、或是濕式顯影。
在圖4f中，一絕緣層或鈍化層174會利用下面方法被形成在半導體晶粒124、囊封體160、以及互連單元600的上方：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。絕緣層174含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有或是不具有填充劑的可低溫(小於260℃)固化聚合物介電質光阻、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層174會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出半導體晶粒124的導體層132以及互連單元600，以便進行後續的電互連。
一導電層180會使用PVD、CVD、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在絕緣層174、半導體晶粒124、以及互連單元600的上方。導體層180含有由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層180會被電連接至導體層132和導體通孔574。一部分的導體層180會相依於半導體晶粒124的設計和功能而共電或是被電隔離並且操作如同一RDL，用以將電氣連接從 該半導體晶粒處扇出並且延伸至互連單元600。
在圖4g中，一絕緣層或鈍化層182會利用下面方法被形成在絕緣層174以及導體層180的上方：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。絕緣層182含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有或是不具有填充劑的可低溫(小於260℃)固化聚合物介電質光阻、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層182會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層180，以便進行後續的電互連。
一導電層184會使用PVD、CVD、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層180以及絕緣層182的上方。導體層184含有由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層184會被電連接至導體層180。一部分的導體層184會相依於半導體晶粒124的設計和功能而共電或是被電隔離。
在圖4h中，一絕緣層或鈍化層186會利用下面方法被形成在絕緣層182以及導體層184的上方：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。絕緣層186含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有或是不具有填充劑的可低溫(小於260℃)固化聚合物介電質光阻、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層186會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以露出導體層184，以便進行後續的電互連。
圖4h進一步顯示一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層184 的上方以及絕緣層186中的開口裡面。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層184。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊188。於某些應用中，凸塊188會被二次回焊，以便改良和導體層184的電接觸效果。於其中一實施例中，凸塊188係被形成在一具有潤濕層、屏障層、以及黏著層的凸塊下層金屬(Under Bump Metallization，UBM)的上方。該些凸塊亦能夠被壓縮焊接至導體層184。凸塊188代表能夠被形成在導體層184上方的其中一種類型互連結構。該互連結構亦能夠使用導體膏、短柱凸塊、微凸塊、或是其它電互連線。於某些實施例中，凸塊188係在一第二半導體構件被設置在半導體晶粒124上方之後才被形成。
絕緣層174、182、186以及導體層180、184以及凸塊188一起構成互連結構190。互連結構190裡面包含的絕緣層和導體層的數量相依於電路繞線設計的複雜度並且會隨之改變。據此，互連結構190能夠包含任何數量的絕緣層和導體層，用以幫助進行和半導體晶粒124有關的電互連。或者，背側互連結構或RDL中所包含的元件亦能夠被整合成互連結構190的一部分，以便簡化製造並且降低和包含前側與背側互連線或RDL的封裝有關的製作成本。
在圖4i中，一雷同於載體140的非必要載體或暫時性基板202會被設置在互連結構190的上方。載體202可以為背面研磨膠帶、支撐膠帶、以及含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用 於達到結構性支撐之目的的其它合宜低成本剛性材料)的其它載體。載體202會包含一介面層(例如，雙面膠帶)，其被配置成用以接收互連結構190。載體202視情況為一半導體封裝的後續處理步驟提供額外的支撐，如圖4i至4n中所示。或者，該些後續處理步驟係在沒有載體202下被實施。
圖4i進一步顯示在利用研磨機206平坦化囊封體160之表面並且縮減厚度的研磨操作中和凸塊188反向的囊封體160頂表面。化學蝕刻或CMP製程亦能夠被用來移除機械性損壞並且配合背表面128來平坦化囊封體160。於其中一實施例中，在移除一部分的囊封體160之後，囊封體160的厚度落在100至400μm的範圍中。該研磨操作會向下移除一部分的囊封體160至半導體晶粒124的背表面128。或者，一層囊封體160仍會殘留在半導體晶粒124的背表面128上方。於某些實施例中，研磨操作會露出導體層576並且可以露出互連單元600的導體材料574。或者，一部分的囊封體160仍會殘留在互連單元600的上方。
在圖4j中，一絕緣層、聚合物基質合成膜、或是翹曲平衡層210會被形成在半導體晶粒124的背表面128、囊封體160、以及互連單元600的上方。絕緣層210包含環氧樹脂、樹脂、或是具有強化纖維或織物(例如，酚系棉紙、環氧樹脂、樹脂、織狀玻璃、毛玻璃、聚酯、以及其它強化纖維或織物)的聚合物。於另一實施例中，絕緣層210含有一模製化合物；具有或是不具有填充劑的聚合物介電質；SiO2、Si3N4、SiON、Ta2O5、Al2O3所製成的一或更多層；以織狀玻璃纖維強化的聚合物基質；或是具有雷同絕緣特性及結構特性的其它材料。於又一實施例中，絕緣層210包含由下面所製成的一或更多層疊層：膠片、FR環氧樹脂-4、FR-1、CEM-1、 或是CEM-3。絕緣層210係利用有加熱或不加熱的真空或壓力層疊、PVD、CVD、網印、旋塗、噴塗、注入式塗佈、燒結、熱氧化、或是其它合宜製程所沉積。絕緣層210經過選擇而具有雷同於Cu之熱膨脹係數(Coefficient of Thermal Expansion，CTE)的CTE，也就是，落在Cu的CTE的10ppm/℃裡面。被選擇用於絕緣層210的材料(例如，膠片)會強化半導體封裝的整體強度並且改良封裝翹曲，尤其是在150℃至260℃的溫度處。絕緣層210平衡該半導體裝置中的翹曲並且在後續的裝置整合期間提供額外的支撐。絕緣層210還會保護半導體晶粒124的外露部分。於某些實施例中，半導體晶粒124會被絕緣層210、囊封體160、以及互連結構190完全嵌入。
在圖4k中，一部分的絕緣層210和囊封體160會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以形成貫穿絕緣層210和囊封體160的通孔或開口216，以便露出互連單元600的導體通孔574。於某些實施例中，通孔216之形成進一步包含移除一部分的絕緣層578。
於某些實施例中，在形成通孔216之後，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、網印製程、焊膏印刷製程、噴射製程、或是其它合宜的製程被沉積在通孔216之中以及互連單元600的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。該助熔溶液會在一浸漬製程中被旋塗、模板印刷、或是塗敷。該助熔溶液係一含有溶劑的免清洗助熔劑或是水洗式助熔劑。該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至互連單元600。於某些實施例中，凸塊材料會被焊接至形成在導體層576 上的一焊料帽(solder cap)。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊224，如圖4m中所示。於某些應用中，凸塊224會被二次回焊，以便改良和互連單元600的電接觸效果。凸塊224會在有或沒有載體202的支撐以及有一分離載體的支撐下被回焊。於其中一實施例中，凸塊224係被形成在一具有潤濕層、屏障層、以及黏著層的UBM的上方。凸塊224亦能夠被壓縮焊接至互連單元600。凸塊224代表能夠被形成在互連單元600上方的其中一種類型互連結構。該互連結構亦能夠使用導體膏、短柱凸塊、微凸塊、具有Cu核心的焊球、Cu球、或是具有浸漬焊膏或焊接塗料的柱狀體、或是被設置在通孔216裡面的其它電互連線。
凸塊224會連同互連結構190、互連單元600、以及半導體晶粒124一起構成一3D互連線，用以進行下一級的互連。於其中一實施例中，凸塊224係藉由表面安裝技術(Surface Mount Technology，SMT)所形成，印刷焊膏係在重組晶圓級處被沉積在通孔216之中。在形成凸塊224之後，一非必要的聚合物介電質填塞焊膏可以被塗敷在該些凸塊的上方與周圍，用以提供額外的支撐。該聚合物介電質填塞焊膏係經由印刷、噴塗、浸漬、噴射、或是其它合宜的製程來塗敷並且接著在真空下進行非必要的回焊或熱處理。或者，凸塊會稍後被形成在一外部半導體封裝上，如圖4l中所示。
圖4k進一步顯示合成基板或重組晶圓170利用鋸片或雷射削切工具226被單體化裁切成個別的半導體封裝227。藉由在安裝額外的半導體裝置於該重組晶圓170上方之前先單體化裁切重組晶圓170，半導體封裝之形成可藉由安裝額外的半導體裝置至個別半導體封裝227來完成，而 並非在重組晶圓級處。或者，重組晶圓170會在額外的半導體裝置被安裝至該重組晶圓170之後才被單體化裁切。半導體封裝227可以在單體化裁切之前或之後進行電氣測試。
在將半導體裝置單體化裁切成個別半導體封裝227並且移除載體202之後，一非必要載體、載體盤、或是暫時性基板228會被設置在互連結構190上方，如圖4l中所示。或者，載體202會連同重組晶圓170一起被單體化裁切。載體228包含一背面研磨膠帶、支撐膠帶、以及含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的其它載體。載體228會包含一介面層、雙面膠帶、以及多個開口，其被配置成用以接收合成基板170或半導體封裝227以及互連結構190。載體228視情況為該半導體封裝的後續處理步驟提供額外的支撐，如圖4l至4n中所示。或者，該些後續處理步驟係在沒有載體228下被實施。
圖4l進一步顯示從一雷同於圖3a至3c的半導體晶圓處單體化裁切下來的半導體封裝、半導體晶粒、或是半導體構件230，其具有一背表面252以及含有類比電路或數位電路的主動表面254，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面254裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒230可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。半導體晶粒230會在從一半 導體晶圓處進行單體化裁切之前或之後進行電氣測試，雷同於圖3a至3c的半導體晶粒124。
一絕緣層或鈍化層255會利用下面方法被形成在半導體晶粒230的上方：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。絕緣層255含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。一部分的絕緣層255會藉由LDA、蝕刻、或是其它合宜的製程來移除，以便進行後續的電互連。
一導電層256會使用PVD、CVD、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在主動表面254的上方。導體層256可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層256的操作如同被電連接至主動表面254上之電路的接觸墊256。導體層256會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒230的邊緣相隔第一距離處。或者，導體層256會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層256的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程 被焊接至導體層256。於某些實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊258。於某些應用中，凸塊258會被二次回焊，以便改良和導體層256的電接觸效果。於某些實施例中，凸塊258係被形成在一具有潤濕層、屏障層、以及黏著層的UBM的上方。該些凸塊亦能夠被壓縮焊接或是熱壓縮焊接至導體層256。凸塊258代表能夠被形成在導體層256上方的其中一種類型互連結構。該互連結構亦能夠使用導體膏、短柱凸塊、微凸塊、或是其它電互連線。
於某些實施例中，凸塊258會形成被形成在導體層256上方的BGA的一部分。該BGA被形成使得凸塊258對齊互連單元600上方的通孔216的配向。或者，第一部分的凸塊258對齊互連單元600上方的通孔216，而第二部分的凸塊258則和互連單元600隔離或者形成半導體晶粒230周圍的額外互連結構的一部分。
半導體晶粒230會利用拾放操作被安裝至個別的半導體封裝227，主動表面254配向成朝向通孔216，並且凸塊258延伸至通孔216之中用以接觸互連單元600。如前面的討論，凸塊224可以在進行堆疊組裝之前預先被形成在通孔216裡面(圖4m)。於某些實施例中，半導體晶粒230的寬度大於半導體晶粒124的寬度。在半導體晶粒230被安裝至半導體封裝227之後，半導體晶粒230會被放置在或是部分被放置在半導體晶粒124的覆蓋區外面。於某些實施例中，一互連結構會被形成在半導體晶粒230的主動表面254的上方並且多個凸塊258會被形成在該互連結構的一表面的上方。於其它實施例中，半導體晶粒230不具有凸塊258而且半導體晶粒230經由預先形成在通孔216中的凸塊224來連接互連單元600處的個別半導體 封裝227，如圖4m中所示。於另一實施例中，半導體晶粒230經由凸塊258以及一互連結構的組合或是經由一互連結構而沒有凸塊258來連接互連單元600處的個別半導體封裝227。凸塊258之形成能夠在將半導體晶粒230安裝至個別半導體封裝227之前或期間來進行。
在安裝半導體晶粒230於個別半導體封裝227的上方之前，一底層填充材料260、環氧樹脂膠黏材料、環氧樹脂化合物、或是模製材料會被設置在半導體封裝227的覆蓋區裡面的絕緣層210上方，如圖4n中所示。虛線261表示半導體晶粒230的晶粒附接區。底層填充材料260會依照平衡位置被塗敷成為設置在個別半導體封裝227的覆蓋區裡面的絕緣層210上方的圓點。底層填充材料260在堆疊組裝以及安裝半導體晶粒230於個別半導體封裝227上方期間支撐半導體晶粒230。或者，一非導體膏會取代或結合底層填充材料260被設置在絕緣層210上方，用以在堆疊組裝以及安裝半導體晶粒230於個別半導體封裝227上方期間提供額外的支撐。底層填充材料260在安裝期間以及在後續的回焊製程期間提供支撐。底層填充材料260可以視情況被設置在半導體晶粒230的主動表面254上。
於某些實施例中，凸塊258形成被設置在半導體晶粒230之主動表面254上方的一互連結構的一部分，用以幫助半導體晶粒230之重新繞線，雷同於互連結構190。凸塊258能夠延伸自一互連結構，俾使得該互連結構、該些凸塊258、該互連結構190、以及該些互連單元600組成一從半導體封裝227形成至半導體晶粒230的L形互連線。
載體228會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除在堆疊組裝之後或期間被移除。 一非必要的囊封體可以被沉積在半導體封裝227和半導體晶粒230的上方。
圖5所示的係利用圖4a至4n中所示之製程所形成之和載體228分離之後的半導體封裝300，半導體晶粒230和凸塊258被安裝在半導體晶粒124的上方。於某些實施例中，半導體晶粒230橫向偏移於半導體晶粒124上方，俾使得半導體晶粒230被設置在半導體晶粒124之一部分的上方。互連單元600係被設置在半導體封裝300裡面，正交於互連結構190，並且垂直延伸在互連結構190上方。於某些實施例中，結合互連單元600之後的凸塊258的高度大於半導體晶粒124的厚度。因此，一間隙存在於主動表面254和背表面128之間。絕緣層210係被插設在該介於主動表面254和背表面128之間的間隙之中。或者，結合互連單元600之後的凸塊258的高度等於或小於半導體晶粒124的厚度。半導體晶粒230的主動表面254可以靜置在背表面128上方的絕緣層210上，在主動表面254和背表面128之間沒有任何間隙。被形成在背表面128及囊封體160上方並且被插設在主動表面254和背表面128之間的絕緣層210會提供實體支撐，控制整體的封裝翹曲，以及為半導體晶粒124提供環境保護，避免受到外部元素與污染物的破壞。絕緣層210為半導體封裝300提供結構性支撐，平衡封裝上的應力，並且在後續的處置及處理期間減少封裝300的翹曲或破裂。
半導體封裝300經由互連結構190、互連單元600、以及凸塊258之組合提供3D垂直電氣互連。該垂直互連係由低背側RDL所形成。互連結構190被形成在半導體晶粒124的主動表面130上方以及囊封體160的上方，一部分互連結構190圍繞半導體晶粒124的周邊。互連結構190包含絕緣層和導電層，它們構成一扇出互連結構並且包含會被包含在一背側 RDL或互連結構中的元件。互連單元600提供垂直互連以減少RDL層，並且提供部分的背側RDL，而不會有和在半導體封裝300之背側上方形成一完整RDL層或多重RDL相關聯的成本以及較困難的製程。利用半導體封裝300裡面的互連單元600提供設計彈性並且降低半導體封裝300的高度。半導體封裝300係一低輪廓3D封裝結構。
利用預先製作的模組式互連單元600會在封裝期間提供額外的彈性，因為互連單元600能夠在封裝過程的各種階段被安裝至載體140或半導體封裝300。利用黏著劑來安裝互連單元600不需要在半導體封裝300的封裝期間於載體140上方形成層。互連單元600為能夠被設置在一半導體封裝(例如，半導體封裝300)裡面或是從一半導體封裝處移除的模組式單元，不同於形成在半導體封裝裡面的層。被設置在半導體晶粒124周圍的互連單元600以減少RDL應用提供垂直互連。被形成在半導體晶粒124周圍的互連單元600在封裝期間提供結構性支撐並且在塗敷囊封體160及外部半導體構件(例如，半導體晶粒230)期間減少移動。於某些實施例中會沿著一垂直平面從導體層256處製作一連續的垂直互連線，經過凸塊258、互連單元600、導電層180、導電層184、抵達凸塊188。真實3D互連可利用半導體封裝300達成，同時降低半導體封裝300的高度。作為垂直結構，互連單元600除了提供垂直電氣互連之外，還會在半導體晶粒124的一側邊部分或周邊區域周圍形成一邊界、框架、狹孔、或是雷同的支撐結構。互連單元600會減少被形成在一封裝裡面的RDL的數量。互連單元600提供部分背側RDL，但卻不會有和在一半導體封裝中形成多重RDL相關聯的成本、時間、以及其它製造限制條件。互連單元600提供設計彈性，同時降低z 方向封裝高度。
凸塊258，或是一外部裝置(例如，半導體晶粒230)的互連結構，會被設置在或是被形成在半導體晶粒230上，配向匹配被設置圍繞半導體晶粒124的互連單元600的佈局或配向。匹配凸塊258或半導體晶粒230之互連結構和互連單元600的佈局會減少製造材料以及成本。匹配互連單元600和凸塊258或半導體晶粒230的互連結構提供一種一致性且可靠的3D垂直互連。於某些實施例中，互連結構190進一步匹配半導體晶粒124周圍的互連單元600的配向。
藉由設置互連單元600為反向於增進層和RDL來創造垂直互連會為封裝設計提供更大的彈性。互連單元600不必被設置在一完整的表面區域上方並且能夠當作模組式單元被設置在一半導體封裝300裡面的客製化位置處，這很難以其它互連結構來達成。舉例來說，設置互連單元600在半導體晶粒124的第一側邊部分上方並且不圍繞半導體晶粒124的第二側邊部分能夠釋放半導體封裝300裡面的寶貴空間，並且裸露半導體晶粒124周圍的第二側邊部分供額外的電構件使用。或者，當希望提高垂直互連密度時，互連單元600亦能夠完全包圍半導體晶粒124，以便達到密集但卻有彈性的垂直互連。互連單元600會節省材料，同時最佳化半導體封裝300裡面的空間。
圖6a至6h所示的係用於一半導體封裝之替代實施例的製程流程，該半導體封裝係利用雷同於圖4a至4n中的半導體封裝300的製程所形成。圖6a顯示一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時 性基板308(雷同於圖4a的載體140)的一部分的剖視圖。一介面層或雙面膠帶310會被形成在載體308的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
圖6a顯示，舉例來說，圖3c中的半導體晶粒124會利用拾放操作被安裝至介面層310，主動表面130配向成朝向載體308。被安裝至晶粒附接區150的半導體晶粒124能夠選自KGD。半導體晶粒124會被擠壓至介面層310，俾使得一部分的絕緣層134被設置在該介面層裡面並且被該介面層包圍。
預先製作的模組式互連單元或互連結構326(雷同於互連單元600)會利用一非必要的黏著劑被安裝至介面層310。雷同於互連單元600，互連單元326係在平板/脫除級(panel/strip level)以一典型的層疊基板被預先製作並且被單體化裁切成個別的互連單元326。互連單元326包含互連層312、核心基板323、以及導體通孔324。互連單元326被設置在和載體邊緣相隔一距離處，也就是，一間隙或空間殘留在該載體邊緣和互連單元326之間。或者，互連單元326延伸至載體308的邊緣。互連單元326被設置在和半導體晶粒124相隔一距離處，也就是，一間隙或空間殘留在半導體晶粒124和互連單元326之間。
互連層312包含一位於核心基板323上方的第一絕緣層或鈍化層316，其含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層316係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。
互連層312包含一被形成在絕緣層316之中的第一導電層 318，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層318可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層318充當用於互連單元326的Cu觸墊。
互連層312進一步包含一被形成在導體層318和絕緣層316上方的第二絕緣層或鈍化層320，其含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層320係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。
互連層312進一步包含一被形成在絕緣層320和導體層318上方的第二導電層322，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層322可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層322會被電連接至導體層318和導體通孔324。其它部分的導體層322會相依於半導體裝置的設計和功能而共電或是被電隔離。
圖6b所示的係被安裝至圍繞半導體晶粒124之介面層310的互連單元326。互連單元326被安裝在半導體晶粒124之反向側邊上方的介面層310上，如圖6c中所示，半導體晶粒124的主動表面130配向成朝向介面層310以及和介面層310反向的互連單元326的互連層312。
圖6b進一步顯示利用焊膏印刷(paste printing)塗敷機、擠壓模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124、互連單元 326、載體308、以及介面層310上方的囊封體或模製化合物325。或者，囊封體325係利用一模套來塗敷。囊封體325可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體325係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體325係被形成在半導體晶粒124的背表面128上方，並且會在後續的背面研磨步驟中被薄化。
圖6c所示的係在囊封體325之前以及安裝互連單元326至介面層310之後圖6b中的半導體封裝的俯視圖。於某些實施例中，互連單元326被設置在半導體晶粒124的反向側邊上方。虛線261表示用於稍後安裝半導體晶粒230的晶粒附接區。
在圖6d中，載體308和介面層310會藉由化學蝕刻、機械性剝除、化學機械性平坦化(Chemical Mechanical Planarization，CMP)、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除。亦可以使用非必要的清洗製程，例如，雷射清洗、乾式電漿、或是濕式顯影。
在圖6e中，一額外的增進互連結構330會被形成在囊封體325、主動表面130、以及互連單元326的上方。互連結構330包含一被形成在半導體晶粒124上方的互連結構330之中的凹腔338。於某些實施例中，凹腔338係一晶粒附接區。於某些實施例中，凹腔338會露出該凹腔上方的主動表面130，以便後續直接安裝腔半導體晶粒230至半導體晶粒124。於某些實施例中，如圖6e中所示，互連結構330的一已薄化部分殘留在半導體晶粒124的上方，俾使得主動表面130不會因凹腔338而露出。在互連結構330的形成期間，絕緣層327可以藉由部分機械性研磨或雷射燒蝕而被部 分移除或是完全移除。
互連結構330包含一絕緣層或鈍化層332，其含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層332係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。
互連結構330包含一被形成在絕緣層332之中的導電層334，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層334可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於某些實施例中，一部分的導體層334會被電連接至互連單元326以及一部分的導體層334會被電連接至主動表面130上方的導體層132。其它部分的導體層334會相依於半導體裝置的設計和功能而共電或是被電隔離。
互連結構330進一步包含一被形成在絕緣層332之中以及導體層334上方的導電層336，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層336可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於某些實施例中，一部分的導體層336會被電連接至導體層334。其它部分的導體層336會相依於半導體裝置的設計和功能而共電或是被電隔離。
在圖6f中，和互連結構330反向的囊封體325的表面會以研磨機206進行研磨操作，用以平坦化囊封體325的表面並且縮減囊封體325的厚度，從而露出導體層318。或者，亦能夠使用淺LDA經由囊封體 325來露出互連單元326的導體層318。
在圖6g中，從一雷同於圖3a至3c的半導體晶圓處單體化裁切下來的半導體封裝、半導體晶粒、或是半導體構件230會被設置在凹腔338的上方。半導體晶粒230會利用拾放操作被安裝至互連結構330的凹腔338。半導體晶粒230的凸塊258會被焊接至凹腔338裡面及半導體晶粒124之主動表面130上方的互連結構330的導體部分，例如，導體層334。或者，凹腔338會露出主動表面130並且半導體晶粒230會經由凸塊258直接連接主動表面130上方的導體層132。於某些實施例中，半導體晶粒230的寬度小於半導體晶粒124的寬度。於某些實施例中，半導體晶粒230被設置在半導體晶粒124的覆蓋區上方。於某些實施例中，半導體晶粒230不具有凸塊258，且取而代之的係，凸塊係預先形成在凹腔338裡面。
圖6g進一步顯示一機械性支撐層346，其係利用印刷、旋塗、噴塗、網印、模板印刷、噴射、層疊、或是其它合宜的製程被形成在背表面128的上方。亦可以使用非必要的清洗製程，例如，雷射清洗、乾式電漿、或是濕式顯影。機械性支撐層346的材料包含由下面所製成的一或更多層：具有或不具有填充劑的光敏聚合物介電質膜、光敏合成光阻、非光敏聚合物介電質膜、液晶聚合物(Liquid Crystal Polymer，LCP)、層疊複合膜、具有填充劑的絕緣膏、液體模製複合物、粒狀模製複合物、聚亞醯胺、聚合物助熔劑、底層填充物、或是具有雷同絕緣特性及結構特性的其它材料。機械性支撐層346中的一或更多個部分會利用LDA來移除。機械性支撐層346提供結構性支撐，平衡半導體封裝上的應力，並且減少翹曲與破裂。於其中一實施例中，機械性支撐層346係在進行雷射燒蝕以露出 導體層318之前先被層疊在半導體晶粒124的背表面128以及囊封體325的上方。
圖6h所示的係半導體晶粒230被安裝在半導體晶粒124之主動表面130上方的互連結構330的凹腔338裡面而成為一半導體封裝306。載體308和介面層310會藉由化學蝕刻、機械性剝除、化學機械性平坦化(CMP)、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除。亦可以使用非必要的清洗製程，例如，雷射清洗、乾式電漿、或是濕式顯影。
一非必要的底層填充材料340會圍繞凸塊258被設置在半導體晶粒230和主動表面130之間。於某些實施例中，如圖6h中所示，半導體晶粒230延伸在互連結構330的厚度以上。或者，半導體晶粒230可以包括某個厚度，使得在安裝半導體晶粒230於凹腔338裡面時，背表面252會和被形成在互連單元326上方之表面反向的互連結構330表面共面，或是在該表面之下。至少一部分的互連單元326會被囊封體325以及互連結構330完全嵌入。
圖6h進一步顯示一利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在互連單元326的導體層318上方的導電凸塊材料。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層318。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊 348。於某些應用中，凸塊348會被二次回焊，以便改良和導體層318的電接觸效果。於其中一實施例中，凸塊348係被形成在一具有潤濕層、屏障層、以及黏著層的UBM的上方。該些凸塊亦能夠被壓縮焊接至導體層318。凸塊348代表能夠被形成在導體層318上方的其中一種類型互連結構。該互連結構亦能夠使用導體膏、短柱凸塊、微凸塊、或是其它電互連線。
被設置在半導體晶粒124周圍的模組式互連單元326以減少RDL應用提供垂直互連。沿著其中一側或是以L形配置被設置在半導體晶粒124周圍的互連單元326，雷同於圖4c，在封裝期間提供結構性支撐並且在塗敷囊封體325及外部半導體構件(例如，半導體晶粒230)期間減少移動。互連單元326會在半導體晶粒124的一或更多個側邊部分周圍或是一周邊區域上方形成一邊界、框架、狹孔、或是雷同的支撐結構。互連單元326會減少被形成在一封裝裡面的RDL的數量。互連單元326提供部分背側RDL，但卻不會有和在一半導體封裝中形成多重RDL相關聯的成本、時間、以及其它製造限制條件。互連單元326提供設計彈性，同時降低z方向封裝高度。
凸塊258，或是一外部裝置(例如，半導體晶粒230)的互連結構，會被設置在或是被形成在半導體晶粒230上，配向匹配被設置圍繞半導體晶粒124的互連單元326的佈局或配向。匹配凸塊258或半導體晶粒230之互連結構和互連單元326的佈局會減少製造材料以及成本。匹配互連單元326和凸塊258或半導體晶粒230的互連結構提供一種一致性且可靠的3D垂直互連。
藉由設置互連單元326為反向於增進層和RDL來創造垂直互連會為封裝設計提供更大的彈性。互連單元326不必被設置在一完整的 表面區域上方並且能夠當被設置在半導體封裝306裡面的客製化位置處，這很難以其它互連結構來達成。舉例來說，設置互連單元326在半導體晶粒124的第一側邊部分上方並且不圍繞半導體晶粒124的第二側邊部分能夠釋放半導體封裝306裡面的寶貴空間，並且裸露半導體晶粒124周圍的第二側邊部分供額外的電構件使用。或者，當希望提高垂直互連密度時，互連單元326亦能夠完全包圍半導體晶粒124，以便達到密集但卻有彈性的垂直互連。互連單元326有助於節省材料並且還可以最佳化半導體封裝306裡面的空間。
圖7所示的係一半導體封裝的替代實施例350，其係利用雷同於圖6a至6h中的半導體封裝306的製程所形成。在半導體封裝350中，凸塊348會被移除並且由被形成在互連層312上方或裡面的LGA觸墊352取代。LGA觸墊352取代凸塊348提供用於半導體封裝350的I/O，以便降低該封裝的高度或厚度。
機械性支撐層346亦從半導體封裝350處被移除。從半導體封裝350處移除機械性支撐層346和凸塊348提供低輪廓並且減少製造步驟。於某些實施例中，半導體封裝350包含一底部表面，其共面於背表面128、互連層312的底部表面、以及囊封體325的底部表面。因此，其為半導體封裝350提供一細薄卻健全的輪廓。
圖8a至8g所示的係用於一半導體封裝之替代實施例的製程流程，該半導體封裝係以雷同於圖6a至6h中所示之半導體封裝306的製程所形成。圖8a顯示一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時 性基板308(雷同於圖4a的載體140)的一部分的剖視圖。一介面層或雙面膠帶310會被形成在載體308的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。
圖8a顯示，舉例來說，圖3c中的半導體晶粒124會利用拾放操作被安裝至介面層310，主動表面130配向成朝向載體308。被安裝至晶粒附接區150的半導體晶粒124能夠選自KGD。半導體晶粒124會被擠壓至介面層310，俾使得一部分的絕緣層134被設置在該介面層裡面並且被該介面層包圍。
預先製作的模組式互連單元或互連結構364(雷同於圖6a中的互連單元326)會利用一非必要的黏著劑被安裝至介面層310。雷同於互連單元600，互連單元364係在平板/脫除級以一典型的層疊基板被預先製作並且被單體化裁切成個別的互連單元364。互連單元364包含互連層366、絕緣層362、導體層363、以及互連層374。互連單元364被設置在和半導體晶粒124相隔一距離處。一間隙或空間殘留在半導體晶粒124和互連單元364之間。
互連層366係互連單元364的一部分並且提供額外的垂直互連，其包含一用於互連單元364的Cu觸墊。作為互連單元364的一部分，互連層366延伸自互連單元364的覆蓋區並且落在覆蓋區裡面。互連層366包含一絕緣層或鈍化層367，其含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層367係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。
互連層366進一步包含一被形成在絕緣層367之中的導電層368，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層368可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。
互連層366進一步包含一被形成在絕緣層367之中及導體層368上方的導電層370，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層370可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於某些實施例中，一部分的導體層370會被電連接至導體層368。其它部分的導體層370會相依於半導體裝置的設計和功能而共電或是被電隔離。導體層370形成用於互連單元364的Cu觸墊。
互連層374和互連層366反向，係互連單元364的一部分。作為互連單元364的一部分，互連層374延伸自互連單元364的覆蓋區並且落在覆蓋區裡面。互連層374包含一絕緣層或鈍化層375，其含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層375係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。
互連層374進一步包含一被形成在絕緣層375之中的導電層376，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層376可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。
互連層374進一步包含一被形成在絕緣層375之中及導體層 376上方的導電層378，其係使用諸如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程所形成。導體層378可能係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於某些實施例中，一部分的導體層378會被電連接至導體層376。其它部分的導體層378會相依於半導體裝置的設計和功能而共電或是被電隔離。
圖8b所示的係被安裝至圍繞半導體晶粒124之介面層310的互連單元364。互連單元364被安裝在半導體晶粒124的一側邊部分上方的介面層310上。
圖8b進一步顯示利用焊膏印刷塗敷機、擠壓模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124、互連單元364、載體308、以及介面層310上方的囊封體或模製化合物372。或者，囊封體372係利用一模套來塗敷。囊封體372可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體372係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封體372係被形成在半導體晶粒124的背表面128上方。
在圖8c中，增進互連結構382會被形成在絕緣層375的一表面、絕緣層134、主動表面130、以及囊封體372的上方。互連結構382包含一被形成在囊封體372、絕緣層134、絕緣層375、導體層378、以及主動表面130上方的絕緣層或鈍化層383。於某些實施例中，絕緣層383含有由下面所製成的一或更多層：具有或是不具有填充劑的可低溫固化聚合物 介電質光阻(也就是，在小於260℃處固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層383係利用下面方法所沉積：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。一部分的絕緣層383會藉由LDA、蝕刻、或是其它合宜的製程來移除，用以形成導體層132上方的開口。該些開口露出半導體晶粒124的導體層132，以便進行後續的電互連。
一導電層384會被形成在絕緣層383、絕緣層134、半導體晶粒124、以及互連單元364的上方，並且被設置在絕緣層383中的開口裡面，以便填充該些開口並且接觸導體層132。導體層384中的該些一或更多層包含Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層384的沉積使用PVD、CVD、電解質電鍍、無電極電鍍、或是其它合宜的製程。於某些實施例中，導體層384的操作如同RDL，用以扇出及延伸來自半導體晶粒124的電連接線至半導體晶粒124的外部點，例如，互連單元364。
一絕緣層或鈍化層385會被保形塗敷至絕緣層383與導體層384並且遵循它們的外形。絕緣層385含有由下面所製成的一或更多層：具有或是不具有填充劑的可低溫固化聚合物介電質光阻(也就是，在小於260℃處固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層385係利用下面方法所沉積：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。一部分的絕緣層385會藉由曝光或顯影製程、LDA、蝕刻、或是其它合宜的製程來移除，用以在該絕緣層中形成開口，該些開口露出一部分的導體層384，以便進行後續的電互連。
一導電層386會被形成在絕緣層385上方、導體層384上方，並且被設置在絕緣層385中的開口裡面，以便填充該些開口並且接觸導體層384。導體層386中的該些一或更多層包含Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層386的沉積使用PVD、CVD、電解質電鍍、無電極電鍍、或是其它合宜的製程。於某些實施例中，導體層386的操作如同RDL，用以扇出及延伸來自半導體晶粒124的電連接線至半導體晶粒124的外部點。
在圖8d中，和互連結構382反向的囊封體372的表面會以研磨機206進行研磨操作，用以縮減囊封體372的厚度，雷同於圖6f。該研磨操作會露出導體層370，如圖8e中所示。或者，可以使用淺LDA，或是結合研磨操作，經由囊封體372來露出互連單元364的導體層370，如圖8e中所示。於某些實施例中會使用化學蝕刻來移除囊封體372的一或更多個部分。圖8e進一步顯示一機械性支撐層380，其係利用印刷、旋塗、噴塗、網印、模板印刷、噴射、層疊、或是其它合宜的製程被形成在背表面128以及囊封體372的上方。亦可以使用非必要的清洗製程，例如，雷射清洗、乾式電漿、或是濕式顯影。機械性支撐層380的材料包含由下面所製成的一或更多層：具有或不具有填充劑的光敏聚合物介電質膜、光敏合成光阻、非光敏聚合物介電質膜、LCP、層疊複合膜、具有填充劑的絕緣膏、液體模製複合物、粒狀模製複合物、聚亞醯胺、聚合物助熔劑、底層填充物、或是具有雷同絕緣特性及結構特性的其它材料。機械性支撐層380中的一或更多個部分會利用LDA來移除。
在圖8f中，一絕緣層或鈍化層388會被保形塗敷在絕緣層 386與導體層385的上方並且遵循它們的外形。絕緣層388含有由下面所製成的一或更多層：具有或是不具有填充劑的可低溫固化聚合物介電質光阻(也就是，在小於260℃處固化)、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層388係利用下面方法所沉積：PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜的製程。一部分的絕緣層388會藉由曝光或顯影製程、LDA、蝕刻、或是其它合宜的製程來移除，用以在該絕緣層中形成開口390，該些開口露出一部分的導體層386，以便進行後續的電互連。於某些實施例中，絕緣層388包括一雷同於囊封體372的囊封體。
圖8f進一步顯示，從一雷同於圖3a至3c的半導體晶圓處單體化裁切下來的半導體封裝、半導體晶粒、或是半導體構件230被設置在絕緣層388中的開口390的上方。半導體晶粒230會利用拾放操作被安裝在絕緣層388的上方，俾使得凸塊258被設置在開口390裡面，用以焊接導體層386的外露部分。於某些實施例中，半導體晶粒230不具有凸塊258，且取而代之的係，凸塊係預先形成在開口390裡面。
圖8g顯示半導體晶粒230被安裝在半導體晶粒124的上方，凸塊258被設置在絕緣層388的通孔390裡面，成為一半導體封裝400。一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層370的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層 370。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊392。於某些應用中，凸塊392會被二次回焊，以便改良和導體層370的電接觸效果。於其中一實施例中，凸塊392係被形成在一具有潤濕層、屏障層、以及黏著層的UBM的上方。該些凸塊亦能夠被壓縮焊接至導體層370。凸塊392代表能夠被形成在導體層370上方的其中一種類型互連結構。該互連結構亦能夠使用導體膏、短柱凸塊、微凸塊、或是其它電互連線。
被設置在半導體晶粒124周圍的模組式互連單元364以減少RDL應用提供垂直互連。沿著其中一側或是以L形配置被設置在半導體晶粒124周圍的互連單元364，雷同於圖4c，在封裝期間提供結構性支撐並且在塗敷囊封體372及外部半導體構件(例如，半導體晶粒230)期間減少移動。互連單元364會在半導體晶粒124的一或更多個側邊部分周圍或是一周邊區域上方形成一邊界、框架、狹孔、或是雷同的支撐結構。互連單元364在封裝期間提高結構性支撐並且減少半導體晶粒124的移動。互連單元364會減少被形成在一封裝裡面的RDL的數量。互連單元364提供部分背側RDL，但卻不會有和在一半導體封裝中形成多重RDL相關聯的成本、時間、以及其它製造限制條件。互連單元364提供設計彈性，同時降低z方向封裝高度。機械性支撐層380係一背側保護/平衡層，其為半導體封裝400提供結構性支撐，平衡半導體封裝400上的應力，並且減少半導體封裝400的翹曲或破裂。
凸塊258，或是一外部裝置(例如，半導體晶粒230)的互連結構，會被設置在或是被形成在半導體晶粒230上，配向匹配被設置圍繞半 導體晶粒124的互連單元364的佈局或配向。匹配凸塊258或半導體晶粒230之互連結構和互連單元364的佈局會減少製造材料以及成本。匹配互連單元364和凸塊258或半導體晶粒230的互連結構提供一種一致性且可靠的3D垂直互連。
藉由形成互連單元364為反向於增進層和RDL來創造垂直互連會為封裝設計提供更大的彈性。互連單元364不必被設置在一完整的表面區域上方並且能夠當被設置在半導體封裝400裡面的客製化位置處，這很難以其它互連結構來達成。舉例來說，設置互連單元364在半導體晶粒124的第一側邊部分上方並且不圍繞半導體晶粒124的第二側邊部分能夠釋放半導體封裝400裡面的寶貴空間，並且裸露半導體晶粒124周圍的第二側邊部分供額外的電構件使用。或者，當希望提高垂直互連密度時，互連單元364亦能夠完全包圍半導體晶粒124，以便達到密集但卻有彈性的垂直互連。互連單元364有助於節省材料並且還可以最佳化半導體封裝400裡面的空間。
本文雖然已經詳細解釋本發明的一或更多個實施例；但是，熟習本技術的人士便會明白，可以對此些實施例進行修正與更動，其並不會脫離如後面的申請專利範圍之中所提出之本發明的範疇。
124‧‧‧半導體晶粒或構件
128‧‧‧背表面或非主動表面
130‧‧‧主動表面
132‧‧‧導體層
134‧‧‧絕緣層或鈍化層
160‧‧‧囊封體或模製化合物
174‧‧‧絕緣層或鈍化層
180‧‧‧導體層
182‧‧‧絕緣層或鈍化層
184‧‧‧導體層
186‧‧‧絕緣層或鈍化層
188‧‧‧球體或凸塊
190‧‧‧互連結構
210‧‧‧絕緣層
230‧‧‧半導體封裝、半導體晶粒、或是半導體構件
252‧‧‧背表面
254‧‧‧主動表面
255‧‧‧絕緣層或鈍化層
256‧‧‧導體層
258‧‧‧球體或凸塊
300‧‧‧半導體封裝
572‧‧‧核心基板
574‧‧‧直通導體通孔
575‧‧‧直通導體通孔
576‧‧‧導體層
578‧‧‧絕緣層或鈍化層
580‧‧‧導體層
582‧‧‧絕緣層或鈍化層
600‧‧‧模組式3D互連單元

Claims (14)

  1. 一種製造半導體裝置的方法，其包括：提供載體；將半導體晶粒安裝至該載體；將第一模組式互連結構設置於該載體上方並且沿著該半導體晶粒的兩個側邊的長度；將囊封體設置於該半導體晶粒和該第一模組式互連結構上方；在設置該囊封體之後移除該載體；將該囊封體平坦化以曝露該半導體晶粒的背表面；將底層填充點設置於該半導體晶粒的該背表面上；提供半導體構件，其包含被形成在該半導體構件的第一側上方的第二互連結構；以及在將該底層填充點設置於該半導體晶粒的該背表面上之後將該半導體構件設置於該半導體晶粒上方，其中該第二互連結構和該第一模組式互連結構的通孔對齊並且該底層填充點在平衡位置支撐該半導體構件的第二側。
  2. 根據申請專利範圍第1項的方法，其進一步包含僅沿著該半導體晶粒之第一與第二相鄰側邊以L形形成該第一模組式互連結構。
  3. 根據申請專利範圍第1項的方法，其進一步包含沿著該半導體晶粒之第一與第二反向側邊形成該第一模組式互連結構。
  4. 根據申請專利範圍第1項的方法，其進一步包含預先製作該第一模組式互連結構。
  5. 根據申請專利範圍第1項的方法，其進一步包含： 形成絕緣層於該半導體晶粒的表面上方以及該第一模組式互連結構上方；形成該通孔貫穿該絕緣層並且延伸至該第一模組式互連結構之中；以及設置該第二互連結構於該通孔裡面。
  6. 一種製造半導體裝置的方法，其包括：提供半導體晶粒；沿著該半導體晶粒設置模組式互連結構；將絕緣材料設置於該半導體晶粒上方；以及在將絕緣材料設置於該半導體晶粒上方之後將半導體構件設置於該模組式互連結構和該半導體晶粒上方，其中該半導體構件包含互連結構在接觸該模組式互連結構的該半導體構件的第一側，並且其中該絕緣材料插設在該半導體晶粒的第二側和該半導體構件之間以支撐該半導體構件於該半導體晶粒上方。
  7. 根據申請專利範圍第6項的方法，其進一步包含：沉積囊封體於該半導體晶粒和該模組式互連結構上方；形成絕緣層於該半導體晶粒、該囊封體、以及該模組式互連結構上方；以及形成導體通孔貫穿該絕緣層和該囊封體至該模組式互連結構。
  8. 根據申請專利範圍第6項的方法，其中，該模組式互連結構包含：提供基板；形成複數個開口於該基板之中；以及 沉積導體材料於該基板的該開口之中。
  9. 根據申請專利範圍第6項的方法，其中，該模組式互連結構包含僅沿著該半導體晶粒之第一與第二相鄰側邊設置的L形。
  10. 一種半導體裝置，其包括：半導體晶粒；第一互連結構，其被形成在該半導體晶粒的表面上方；第二互連結構，其係沿著該半導體晶粒的周邊區域並且垂直於該第一互連結構被設置；半導體構件，其被設置在該半導體晶粒、該第一互連結構和該第二互連結構上方；以及底層填充點，其被插設在該半導體晶粒和該半導體構件之間。
  11. 根據申請專利範圍第10項的半導體裝置，其中，該第二互連結構包含：基板；開口，其被形成在該基板之中；以及導體材料，其被設置在該基板的該開口之中。
  12. 根據申請專利範圍第10項的半導體裝置，其中，該第二互連結構被設置圍繞該半導體晶粒之第一與第二相鄰側邊。
  13. 根據申請專利範圍第10項的半導體裝置，其中，該第二互連結構被設置圍繞該半導體晶粒之第一與第二反向側邊。
  14. 根據申請專利範圍第10項的半導體裝置，其中該底層填充點在該半導體晶粒上支撐該半導體構件。
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Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
KR101488608B1 (ko) 2013-07-19 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9620457B2 (en) * 2013-11-26 2017-04-11 Infineon Technologies Ag Semiconductor device packaging
US11068770B2 (en) * 2014-03-08 2021-07-20 Féinics AmaTech Teoranta Lower Churchfield Connection bridges for dual interface transponder chip modules
US9768037B2 (en) * 2014-05-16 2017-09-19 Infineon Technologies Ag Electronic device package including metal blocks
US9379097B2 (en) 2014-07-28 2016-06-28 Apple Inc. Fan-out PoP stacking process
US9449908B2 (en) * 2014-07-30 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package system and method
US10056304B2 (en) * 2014-11-19 2018-08-21 Deca Technologies Inc Automated optical inspection of unit specific patterning
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
TWI690044B (zh) * 2015-04-29 2020-04-01 美商戴卡科技有限公司 全模製封裝之３ｄ互連組件
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US11018025B2 (en) * 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US20170053858A1 (en) * 2015-08-20 2017-02-23 Intel Corporation Substrate on substrate package
US9799636B2 (en) 2015-11-12 2017-10-24 Nxp Usa, Inc. Packaged devices with multiple planes of embedded electronic devices
KR102109569B1 (ko) * 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
KR102017635B1 (ko) * 2016-03-25 2019-10-08 삼성전자주식회사 팬-아웃 반도체 패키지
US10818621B2 (en) 2016-03-25 2020-10-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
DE102016107031B4 (de) * 2016-04-15 2019-06-13 Infineon Technologies Ag Laminatpackung von Chip auf Träger und in Kavität, Anordnung diese umfassend und Verfahren zur Herstellung
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
KR102506697B1 (ko) * 2016-05-18 2023-03-08 에스케이하이닉스 주식회사 관통 몰드 볼 커넥터를 포함하는 반도체 패키지
KR101982040B1 (ko) * 2016-06-21 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
US9761570B1 (en) 2016-06-28 2017-09-12 Nxp Usa, Inc. Electronic component package with multple electronic components
US11378468B2 (en) * 2016-08-12 2022-07-05 Brightsentinel Limited Sensor module and process for producing same
KR101994748B1 (ko) 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
US10090199B2 (en) * 2017-03-01 2018-10-02 Semiconductor Components Industries, Llc Semiconductor device and method for supporting ultra-thin semiconductor die
CN106920797B (zh) * 2017-03-08 2018-10-12 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
US10276424B2 (en) * 2017-06-30 2019-04-30 Applied Materials, Inc. Method and apparatus for wafer level packaging
US20190057931A1 (en) * 2017-08-17 2019-02-21 Powertech Technology Inc. Package method for generating package structure with fan-out interfaces
US10529650B2 (en) * 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10304716B1 (en) 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
US10504841B2 (en) 2018-01-21 2019-12-10 Shun-Ping Huang Semiconductor package and method of forming the same
US11101260B2 (en) * 2018-02-01 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a dummy die of an integrated circuit having an embedded annular structure
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
TWI706478B (zh) * 2018-05-08 2020-10-01 黃順斌 半導體封裝件及其形成方法
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
KR102586794B1 (ko) 2018-06-08 2023-10-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11309294B2 (en) * 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11088079B2 (en) * 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
TW202125872A (zh) * 2019-12-27 2021-07-01 晶元光電股份有限公司 發光裝置的修補方法
US11158551B2 (en) * 2020-01-07 2021-10-26 Dialog Semiconductor (Uk) Limited Modular WLCSP die daisy chain design for multiple die sizes
US11227795B2 (en) * 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
CN111696879B (zh) * 2020-06-15 2021-08-31 西安微电子技术研究所 一种基于转接基板的裸芯片kgd筛选方法
CN111900094A (zh) * 2020-07-15 2020-11-06 中国电子科技集团公司第五十八研究所 一种高传输率晶圆级扇出型封装方法及其结构
US20220069489A1 (en) * 2020-08-28 2022-03-03 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040207077A1 (en) * 2003-04-18 2004-10-21 Leal George R. Circuit device with at least partial packaging and method for forming
US20050121769A1 (en) * 2003-12-05 2005-06-09 Watts Nicholas R. Stacked integrated circuit packages and methods of making the packages
US20060267175A1 (en) * 2005-05-31 2006-11-30 Stats Chippac Ltd. Stacked Semiconductor Package Assembly Having Hollowed Substrate
US20090134528A1 (en) * 2007-11-28 2009-05-28 Samsung Electronics Co, Ltd. Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package
US20090236686A1 (en) * 2006-04-19 2009-09-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die
US20100038764A1 (en) * 2006-02-15 2010-02-18 Texas Instruments Incorporated Package on Package Design a Combination of Laminate and Tape Substrate with Back-to-Back Die Combination

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509994A (en) 1984-09-04 1985-04-09 Mcdonnell Douglas Corporation Solder composition for high-density circuits
US5172851A (en) 1990-09-20 1992-12-22 Matsushita Electronics Corporation Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device
US6077725A (en) 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US5817545A (en) 1996-01-24 1998-10-06 Cornell Research Foundation, Inc. Pressurized underfill encapsulation of integrated circuits
DE69728113T2 (de) * 1996-05-22 2005-02-10 Shipro Kasei Kaisha, Ltd. Negativer widerstand des molekulardispersionstyps und verfahren zur herstellung
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
JP2003197848A (ja) * 2001-12-28 2003-07-11 Toshiba Corp 半導体パッケージ及びパッケージ実装体
US7087458B2 (en) 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
US20070100048A1 (en) 2003-12-05 2007-05-03 Korea Institute Of Science & Technology Composite dielectric film including polymer and pyrochlore ceramic and method of forming the same
KR100656751B1 (ko) * 2005-12-13 2006-12-13 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
US20090206480A1 (en) 2008-02-20 2009-08-20 Atmel Corporation Fabricating low cost solder bumps on integrated circuit wafers
US7750454B2 (en) * 2008-03-27 2010-07-06 Stats Chippac Ltd. Stacked integrated circuit package system
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5280309B2 (ja) * 2009-07-17 2013-09-04 新光電気工業株式会社 半導体装置及びその製造方法
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8367475B2 (en) 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
US20130154091A1 (en) * 2011-12-14 2013-06-20 Jason R. Wright Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040207077A1 (en) * 2003-04-18 2004-10-21 Leal George R. Circuit device with at least partial packaging and method for forming
US20050121769A1 (en) * 2003-12-05 2005-06-09 Watts Nicholas R. Stacked integrated circuit packages and methods of making the packages
US20060267175A1 (en) * 2005-05-31 2006-11-30 Stats Chippac Ltd. Stacked Semiconductor Package Assembly Having Hollowed Substrate
US20100038764A1 (en) * 2006-02-15 2010-02-18 Texas Instruments Incorporated Package on Package Design a Combination of Laminate and Tape Substrate with Back-to-Back Die Combination
US20090236686A1 (en) * 2006-04-19 2009-09-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die
US20090134528A1 (en) * 2007-11-28 2009-05-28 Samsung Electronics Co, Ltd. Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package

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SG2013080023A (en) 2014-07-30
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