CN102157492A - 晶片封装体 - Google Patents

晶片封装体 Download PDF

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Publication number
CN102157492A
CN102157492A CN2011100209916A CN201110020991A CN102157492A CN 102157492 A CN102157492 A CN 102157492A CN 2011100209916 A CN2011100209916 A CN 2011100209916A CN 201110020991 A CN201110020991 A CN 201110020991A CN 102157492 A CN102157492 A CN 102157492A
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China
Prior art keywords
semiconductor
hole
wafer
depressed part
encapsulation body
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Granted
Application number
CN2011100209916A
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CN102157492B (zh
Inventor
林佳升
蔡佳伦
徐长生
李柏汉
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XinTec Inc
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XinTec Inc
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Priority claimed from US12/687,093 external-priority patent/US8432032B2/en
Application filed by XinTec Inc filed Critical XinTec Inc
Priority to CN201510063568.2A priority Critical patent/CN104701285B/zh
Publication of CN102157492A publication Critical patent/CN102157492A/zh
Application granted granted Critical
Publication of CN102157492B publication Critical patent/CN102157492B/zh
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Abstract

提供一种晶片封装体，晶片封装体包括半导体基底，具有第一表面和相对的第二表面。间隔层设置在半导体基底的第二表面下方，并且盖板设置在间隔层下方。形成凹陷部邻接半导体基底的侧壁，由半导体基底的第一表面至少延伸至间隔层。然后，保护层设置在半导体基底的第一表面之上以及凹陷部内。本发明可提升晶片封装体的信赖性，并避免导线层产生脱层现象。

Description

晶片封装体
技术领域
本发明有关于一种晶片封装体，特别有关于一种具有硅通孔(through-silicon via)的晶片封装体及其制造方法。
背景技术
为了使电子装置的尺寸越来越小，电子装置内所含的晶片封装体也需要越变越小。降低晶片封装体尺寸的方法之一包括在被封装的晶片内使用硅通孔。然而，在某些情况下，硅通孔内的重布路线层在热循环试验过程中很容易从硅通孔的侧壁脱层(delaminated)，因此，硅通孔也会使得被封装晶片的信赖性下降。
因此，业界亟需一种新的晶片封装体设计以及其制造方法。
发明内容
本发明提供一种晶片封装体，包括半导体基底，具有第一表面和相对的第二表面；贯穿孔设置于第一表面上，由第一表面延伸至第二表面；导线层设置于第一表面之上，且延伸至贯穿孔；缓冲插塞设置于贯穿孔内的导线层之上；以及保护层设置于半导体基底的整个第一表面之上。
此外，本发明还提供一种晶片封装体的制造方法，包括：提供一半导体基底，具有第一表面和相对的第二表面；形成贯穿孔于第一表面上，由第一表面延伸至第二表面；在第一表面之上顺应性地形成导线层，且延伸至贯穿孔；在贯穿孔内的导线层之上形成缓冲插塞；以及形成保护层覆盖半导体基底的整个第一表面。
本发明另提供一种晶片封装体，包括半导体基底，具有第一表面和相对的第二表面；间隔层设置在半导体基底的第二表面下方；盖板设置在间隔层下方；形成凹陷部邻接半导体基底的侧壁，由半导体基底的第一表面至少延伸至间隔层。然后，保护层设置在半导体基底的第一表面之上以及凹陷部内。
本发明还提供一种晶片封装体的制造方法，包括：提供半导体基底，具有第一表面和相对的第二表面；在半导体基底的第二表面下方形成间隔层；将盖板粘着至间隔层的下方；在半导体基底的第一表面上沿着切割线形成沟槽开口，由第一表面至少延伸至间隔层；在半导体基底的第一表面上方以及沟槽开口内形成保护层。然后，沿着切割线分割半导体基底，形成晶片封装体，其中每个晶片封装体包括至少一凹陷部，邻接半导体基底的侧壁，由半导体基底的第一表面至少延伸至间隔层，并且被保护层覆盖。
本发明又提供一种晶片封装体，包括：一半导体基底，具有一第一表面和一与该第一表面相对的第二表面；一间隔层，设置在该半导体基底的该第二表面之下；一盖板，设置在该间隔层之下；一凹陷部，邻接该半导体基底的一侧壁；一贯穿孔，设置于该半导体基底的该第一表面上，由该第一表面延伸至该第二表面；以及一保护层，设置于该半导体基底的该第一表面之上，且填充于该凹陷部与该贯穿孔内。
本发明所述的晶片封装体，该凹陷部由该半导体基底的该第一表面延伸至该间隔层。
本发明所述的晶片封装体，该凹陷部由该半导体基底的该第一表面延伸至该盖板。
本发明所述的晶片封装体，该凹陷部与该贯穿孔同时形成。
本发明所述的晶片封装体，该凹陷部由该半导体基底的该第一表面延伸至该第二表面。
本发明所述的晶片封装体，该凹陷部在该贯穿孔之后形成。
本发明所述的晶片封装体，该凹陷部经由一预切割制程形成。
本发明所述的晶片封装体，该贯穿孔内还包括一缓冲插塞，且该缓冲插塞设置于该保护层下方。
本发明所述的晶片封装体，还包括一导线层顺应性地设置于该半导体基底的该第一表面之上，延伸至该贯穿孔内，且设置于该缓冲插塞下方，以及设置在该凹陷部邻接该半导体基底的该侧壁上。
本发明所述的晶片封装体，该凹陷部具有一倾斜面。
本发明可提升晶片封装体的信赖性，并避免导线层产生脱层现象。
附图说明
图1是显示依据本发明的一实施例，晶片封装体的剖面示意图。
图2A-2H是显示依据本发明的一实施例，制造图1的晶片封装体的各步骤的剖面示意图。
图3是显示依据本发明的一实施例，晶片封装体的剖面示意图。
图4A-4I是显示依据本发明的一实施例，制造图3的晶片封装体的各步骤的剖面示意图。
附图中符号的简单说明如下：
10、10a、10b：晶片；100：半导体基底；100a：第一表面；100b：第二表面；102：半导体元件；102a：导电垫；104：粘着层；106：间隔层；110：盖板；112：空穴；114：贯穿孔；116、130：凹陷部、沟槽开口；118：绝缘层；120：导线层；122：缓冲材料；124：缓冲插塞；126：保护层；128：导电凸块；SL：切割线。
具体实施方式
为了让本发明的上述目的、特征及优点能更明显易懂，以下配合所附图式，作详细说明如下。
以下以实施例并配合图式详细说明本发明，在图式或说明书描述中，相似或相同的部分使用相同的图号。且在图式中，实施例的形状或是厚度可扩大，以简化或是方便标示。再者，图式中各元件的部分将以描述说明，值得注意的是，图中未绘示或描述的元件，为本领域普通技术人员所知的形式。另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明是以一制作影像感测元件封装体(image sensorpackage)的实施例作为说明。然而，可以了解的是，在本发明的晶片封装体的实施例中，其可应用于各种包括有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digitalor analog circuits)等集成电路的电子元件(electroniccomponents)，例如是有关于光电元件(opto electronic devices)、微机电系统(micro electro mechanical system；MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surfaceacoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级晶片封装(wafer level chip scalepackage；WLCSP)。另外，上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
请参阅图1，其是显示本发明一实施例的晶片封装体的部分剖面示意图，其可由晶圆级封装制程形成。首先，提供带有半导体基底100的晶片10，半导体基底100具有第一表面100a与相对的第二表面100b。半导体元件102例如为互补式金属氧化物半导体(CMOS)影像感测元件，以及/或微透镜形成第二表面100b上作为有源面(active surface)。至少一贯穿孔(through hole)114形成于第一表面100a上，由第一表面100a延伸至第二表面100b。至少一导电垫102a经由贯穿孔114暴露出来，并且可经由内连线与半导体元件102电性连接。在另一实施例中，还可形成至少一凹陷部116邻接半导体基底100的侧壁，并由第一表面100a延伸至第二表面100b，其中凹陷部116经由在切割线SL处切割出沟槽开口(trench opening)而形成，切割线SL设置于任两个相邻的晶片之间。
图案化的绝缘层118在第一表面100a上形成，且延伸至贯穿孔114与凹陷部116的侧壁。在另一实施例中，贯穿孔114底部上的绝缘层118被移除。形成绝缘层118的材料包括，但不限定于，例如为二氧化硅的无机材料，或者是例如为绝缘光致抗蚀剂的感光型绝缘材料。然后，图案化的导线层120顺应性地形成在位于第一表面100a之上的绝缘层118上，且延伸至贯穿孔114。在一实施例中，导线层120可以是重布路线层，其可以是由铜、铝、银、镍或前述金属的合金所制成的金属层。在另一实施例中，图案化的导线层120更可顺应性地形成在凹陷部116内，在贯穿孔114与凹陷部116内的导线层120之间会形成间隙，以隔绝贯穿孔114与凹陷部116内的导线层120。
值得一提的是，在贯穿孔114内形成缓冲插塞(bufferplug)124，然后形成保护层126覆盖第一表面100a，并填充贯穿孔114与凹陷部116，在贯穿孔114内填充的缓冲插塞可用来分离导线层120与后续填充的保护层126。在凹陷部116内，导线层120可用来分离保护层126与后续形成的间隔层106。在本发明的实施例中，缓冲插塞124可由一层或一层以上的软性材料形成，保护层126则可以是硬性材料，例如阻焊材料(solder mask)。
在一实施例中，为了提升晶片封装体的信赖性，缓冲插塞124的材料并未完全固化(cured)，因此在贯穿孔114内的缓冲插塞124与保护层126之间的附着力会降低。要使得缓冲插塞124的材料未完全固化，缓冲插塞124可以在其玻璃转化点(glasstransition temperature；Tg)的温度以下固化，或者以较短的时间进行固化，借此可得到附着力较差的软性固化产物。固化的方法有很多种，可通过热、光、电子束或其他类似的方式进行固化。当晶片封装体进行热循环试验(thermal cycle test)时，由硬性材料制成的保护层126可能会收缩，然后从保护层126产生一向上拉拔的力，而软性的缓冲插塞124则可以变形，以抵销从保护层126产生的向上拉拔的力，并避免导线层120产生脱层现象。在上述的固化步骤后，大部分在贯穿孔114内的缓冲插塞124在形状上或尺寸上都是不同的。
此外，为了补偿保护层126的热膨胀系数(coefficient ofthermal expansion；CTE)与绝缘层118的热膨胀系数之间较大的差距，依据本发明一实施例，使得缓冲插塞124的热膨胀系数介于保护层126的热膨胀系数与绝缘层118的热膨胀系数之间，借此可经由缓冲插塞124来调整保护层126与绝缘层118之间的热膨胀系数差距，避免晶片封装体在热循环试验期间产生脱层现象。在一实施例中，保护层126的热膨胀系数可约为159ppm/℃，绝缘层118的热膨胀系数可约为54ppm/℃，因此，缓冲插塞124的热膨胀系数需介于约159ppm/℃至54ppm/℃之间。另外，在一实施例中，缓冲插塞124可由一层以上的光致抗蚀剂形成，并且含有一种以上的材料，因此，缓冲插塞124的热膨胀系数可由54ppm/℃渐变至159ppm/℃。
再参阅图1，在半导体基底100的第二表面100b底下贴附盖板110，盖板110可以是透明基板或半导体基板。在本发明一实施例中，可在盖板110与半导体基底100之间设置间隔层106，并在盖板110与半导体元件102之间形成空穴112，其中空穴112被间隔层106围绕。在另一实施例中，间隔层106可填满盖板110与半导体基底100之间的空间，且无空穴产生。间隔层106可由环氧树脂(epoxy resin)、阻焊材料(solder mask)或任何其他合适的支撑材料制成。此外，当间隔层106形成在盖板110上时，可使用粘着层104来粘接间隔层106与半导体基底100。另外，当间隔层106是形成于半导体基底100上时，可在间隔层106与盖板110之间施加粘着层。粘着层可以是高分子膜，或者是一种或一种以上的粘着剂，例如为环氧化物(epoxy)或聚氨酯(polyurethane)粘着剂。
导电凸块128设置在位于第一表面100a上的保护层126的开口内，与导线层120电性连接，导电凸块128可以是锡球(solderball)或焊垫(solder paste)。
在凹陷部116内形成导线层120有许多优点，首先，如图1所示，在凹陷部116内的导线层120会延伸至切割线SL，且覆盖半导体基底100的侧壁，因此可避免晶片封装体被水气渗透。第二，间隔层106可能会由与保护层126相同的材料形成，例如阻焊材料(solder mask)，在此时，如果保护层与间隔层连接在一起，则在保护层与间隔层所产生的应力会很大。然而，依据本发明的一实施例，保护层126与间隔层106会被导线层120及粘着层104分开来，因此可降低在保护层126与间隔层106所产生的应力。
图2A-2H是显示依据本发明的一实施例，制造晶片封装体的各步骤的部分剖面示意图。参阅图2A，首先，在晶圆厂制造阶段(foundry stage)提供一半导体基底100，例如为带有晶片的晶圆，其具有第一表面100a及相对的第二表面100b，多个半导体元件102形成于第二表面100b上，多个导电垫(conductivepad)102a形成于第二表面100b上，且与每个半导体元件102电性连接。
接着，进行封装阶段，在一实施例中，晶圆100的第二表面100b被贴附至作为载体的盖板110上，盖板110可由玻璃、石英(quartz)、蛋白石(opal)、塑胶或其它任何可供光线进出的透明基板制成。值得一提的是，也可以选择性地形成滤光片(filter)以及/或抗反射层(anti-reflective layer)在盖板110上。在一实施例中，间隔层106可在盖板110或晶圆100上形成，然后将盖板110与晶圆100互相贴附，借此在盖板110与晶圆100之间形成空穴112，如图2A所示，空穴112被间隔层106所围绕。间隔层106的材料可以是环氧树脂、阻焊材料或任何其他合适的支撑材料，例如无机材料或者为聚亚酰胺(polyimide；PI)的有机材料。为了增加封装体的密封性，当间隔层106形成于盖板110上时，可在间隔层106与晶圆100之间施加粘着层104；另外，当间隔层106形成于晶圆100上时，可在间隔层106与盖板110之间施加粘着层。接着，可选择性地在晶圆100的第一表面100a上进行薄化步骤，此薄化步骤可以是蚀刻、铣削(milling)、磨削(grinding)或研磨(polishing)制程。
参阅图2B，在晶圆100内通过移除步骤例如钻孔(drilling)或蚀刻方式，形成多个贯穿孔114以及/或沟槽开口116，其是沿着由第一表面100a至第二表面100b的方向延伸，并且经由贯穿孔114暴露出导电垫102a。每个沟槽开口116在两个相邻的晶片10a与10b之间的切割线SL处形成，在一实施例中，贯穿孔114与沟槽开口116可通过相同的蚀刻制程同时形成。另外，沟槽开口116可以是在预刻痕(pre-cutting)制程时经由切割刀于切割线SL处所形成的凹口(notch)。
接着，请参阅图2C，为了将半导体基底100与后续形成的导线层隔绝，可顺应性地形成绝缘材料覆盖半导体基底的第一表面100a，并且延伸至贯穿孔114与沟槽开口116的侧壁与底部。然后，将绝缘材料图案化，移除在贯穿孔114与沟槽开口116底部的绝缘材料，形成图案化的绝缘层118，在贯穿孔114底部的导电垫102a可通过图案化的绝缘层118暴露出来。在一实施例中，绝缘层118可由感光性绝缘材料形成，感光性绝缘材料可以是感光性有机高分子材料，其成分包括，但不限定于聚亚酰胺(polyimide；PI)、苯环丁烯(butylcyclobutene；BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)或丙烯酸酯(accrylates)等材料。此感光性有机高分子材料可以利用涂布方式，例如旋转涂布(spin coating)、喷涂(spray coating)或淋幕涂布(curtain coating)，或者是其它适合的沉积方式涂布。
参阅图2D，在整个绝缘层118上顺应性地形成导电材料，覆盖晶圆100的第一表面100a，且延伸至贯穿孔114与沟槽开口116的侧壁与底部。在一实施例中，导电材料可以是铜、铝、银、镍或前述金属的合金，其可以经由物理气相沉积(physical vapordeposition；PVD)法或溅镀(sputtering)法顺应性地沉积在绝缘层118上。然后，利用微影蚀刻制程将导电材料图案化，形成导线层120，导线层120从晶圆100的第一表面100a延伸至贯穿孔114的侧壁及底部，并且与贯穿孔114底部的导电垫电性连接。导线层120也可以在沟槽开口116的侧壁与底部上形成，但是在贯穿孔114内的导线层120与沟槽开口116内的导线层120之间会形成一间隙使两者隔绝开来，因此贯穿孔114内的导线层120与沟槽开口116内的导线层120并不连续。
接着，参阅图2E，利用涂布方式，例如旋转涂布、喷涂或淋幕涂布等方式，形成缓冲材料122覆盖晶圆100的整个第一表面100a，并填充贯穿孔114与沟槽开口116。在一实施例中，缓冲材料122可以是感光性材料，例如无填充物的环氧基光致抗蚀剂(epoxy based photo resist)。接着，参阅图2F，利用曝光与显影制程将缓冲材料122图案化，留下部分的缓冲材料122在贯穿孔114内，形成缓冲插塞124，缓冲插塞124可以是在每个贯穿孔114内形成的插塞。然后，使得贯穿孔114内的缓冲插塞124不完全固化，以降低缓冲插塞124与后续形成的保护层之间的附着力，借此，缓冲插塞124可抵抗在热循环试验期间来自保护层的向上拉拔力，并避免在贯穿孔114内的导线层120脱层。此外，因为缓冲插塞124未完全固化，在至少两个贯穿孔114内形成的缓冲插塞124于剖面上会具有不同的形状，例如，在一贯穿孔114内的缓冲插塞124与另一贯穿孔114内的缓冲插塞124的剖面形状不同。此外，缓冲插塞124可由一层或一层以上的感光材料形成。
接着，参阅图2G，在导线层120上形成保护层126，覆盖晶圆100的第一表面100a，并填充贯穿孔114与沟槽开口116。保护层126可以是带有填充物的阻焊材料(solder mask with fillers)，填充物的材料例如为碳化硅、氧化硅或氧化铝。值得一提的是，缓冲插塞124的热膨胀系数是介于保护层126的热膨胀系数与绝缘层118或导线层120的热膨胀系数之间，因此，保护层126与绝缘层118或导线层120之间的热膨胀系数差距可通过缓冲插塞124进行调整，以避免晶片封装体在热循环试验期间产生脱层问题。在一实施例中，保护层126的热膨胀系数可约为159ppm/℃，绝缘层118的热膨胀系数可约为54ppm/℃，因此，缓冲插塞124的热膨胀系数需介于约159ppm/℃至54ppm/℃之间。
接着，请参阅图2H，导电凸块128穿过保护层126形成，且与导线层120电性连接。在一实施例中，于保护层126形成之后，可将保护层126图案化，形成开口暴露出部分的导线层120。接着，利用电镀或网版印刷(screen printing)方式在上述开口内填充焊接材料，然后进行回焊(re-flow)步骤形成导电凸块128，其例如为锡球(solder ball)或焊垫(solder paste)。然后，沿着切割线SL将上述晶圆级封装体切割，分离各个晶片，形成多个如图1所示的晶片封装体。
依据本发明的实施例，位于切割线SL上的沟槽开口116由蚀刻制程形成，因此在半导体基底100的侧壁上不会有微小裂缝产生。此外，在晶圆级封装体的切割制程之后会形成凹陷部116，凹陷部116内的导线层120会延伸至切割线SL，并覆盖半导体基底100的侧壁。因此，导线层120可有效地避免晶片封装体被水气渗透。
另外，在本发明一实施例中，于凹陷部116内没有缓冲插塞存在，因此，凹陷部116内的保护层126的附着力比贯穿孔114内的保护层126的附着力强，借此可避免凹陷部116内的保护层126脱层。
接着，参阅图3，其是显示本发明一实施例的晶片封装体的部分剖面示意图，可由晶圆级晶片封装制程形成。首先，提供带有半导体基底100的晶片10，半导体基底100具有第一表面100a与相对的第二表面100b。半导体元件102例如为互补式金氧半导体(CMOS)影像感测元件，以及/或微透镜形成第二表面100b上作为主动面。至少一贯穿孔114形成于第一表面100a上，由第一表面100a延伸至第二表面100b。至少一导电垫102a经由贯穿孔114暴露出来，并且可经由内连线与半导体元件102电性连接。
在半导体基底100的第二表面100b底下贴附盖板110，盖板110可以是透明基板或半导体基板。在一实施例中，于盖板110与半导体基底100之间设置间隔层106，并在盖板110与半导体元件102之间形成空穴112，其中空穴112被间隔层106围绕。在另一实施例中，间隔层106可填满盖板110与半导体基底100之间的空间，因此无空穴产生。间隔层106可由环氧树脂、阻焊材料或任何其他合适的支撑材料制成。此外，当间隔层106是形成在盖板110上时，可使用粘着层104来粘接间隔层106与半导体基底100。另外，当间隔层106是形成于半导体基底100上时，可在间隔层106与盖板110之间施加粘着层。粘着层可以是高分子膜，或者是一种或一种以上的粘着剂，例如为环氧化物或聚氨酯粘着剂。
可形成至少一凹陷部130邻接半导体基底100的侧壁，由第一表面100a延伸至间隔层106，或者更进一步地延伸至盖板110，其中凹陷部130是经由在切割线SL处切割出沟槽开口而形成，切割线SL设置在任两个相邻的晶片之间。
绝缘层118在第一表面100a上形成，且延伸至贯穿孔114的侧壁，在贯穿孔114底部上的绝缘层118被移除，以暴露出导电垫102a。形成绝缘层118的材料包括，但不限定于，例如为二氧化硅的无机材料，或者是例如为绝缘光致抗蚀剂的感光型绝缘材料。然后，在第一表面100a之上的绝缘层118上顺应性地形成图案化的导线层120，其延伸至贯穿孔114，但是不延伸至凹陷部130。在一实施例中，导线层120可以是重布路线层，导线层120可以是由铜、铝、银、镍或前述金属的合金所制成的金属层。
在贯穿孔114内，于导线层120之上形成缓冲插塞124，然后形成保护层126覆盖第一表面100a，并填充贯穿孔114与凹陷部130。在贯穿孔114内，填充的缓冲插塞可用来分离导线层120与后续填充的保护层126。在凹陷部130内，保护层126直接覆盖半导体基底100以及间隔层106的侧壁，或者更进一步地覆盖盖板110的侧壁。在此实施例中，缓冲插塞124可由一层或一层以上的软性材料形成，保护层126则可以是硬性材料，例如阻焊材料。
在一实施例中，为了提升晶片封装体的信赖性，缓冲插塞124的材料并未完全固化，因此在贯穿孔114内的缓冲插塞124与保护层126之间的附着力会降低。例如，可固化的缓冲插塞124可以在其玻璃转化点(Tg)的温度以下固化，或者以较短的时间进行固化，借此可得到附着力较差的软性固化产物。固化的方法有很多种选择，可通过使用热、光、电子束或其他类似的方式进行固化。当晶片封装体进行热循环试验时，由硬性材料制成的保护层126可能会收缩，然后从保护层126产生向上拉拔的力。然而，软性的缓冲插塞124可以变形，以抵销从保护层126产生的向上拉拔的力，并且避免在贯穿孔114内的导线层120发生脱层。在上述的固化制程进行之后，在贯穿孔114内的缓冲插塞124大部分在形状上或尺寸上都是不同的。
此外，为了补偿保护层126的热膨胀系数(CTE)与绝缘层118的热膨胀系数之间较大的差距，依据本发明的一实施例，缓冲插塞124的热膨胀系数是介于保护层126的热膨胀系数与绝缘层118的热膨胀系数之间，因此可通过缓冲插塞124来调整保护层126与绝缘层118之间的热膨胀系数差距，避免晶片封装体在热循环试验期间产生脱层现象。在一实施例中，保护层126的热膨胀系数可约为159ppm/℃，并且绝缘层118的热膨胀系数可约为54ppm/℃，因此，缓冲插塞124的热膨胀系数需介于约159ppm/℃至54ppm/℃之间。另外，在一实施例中，缓冲插塞124可由一层以上的光致抗蚀剂形成，其含有一种以上的材料，因此，缓冲插塞124的热膨胀系数可由54ppm/℃阶梯式地渐变至159ppm/℃。
然后，在第一表面100a上的保护层126的开口内设置导电凸块128，以与导线层120电性连接，导电凸块128可以是锡球(solder ball)或焊垫(solder paste)。
在凹陷部130内的保护层126至少会覆盖半导体基底100以及间隔层106的侧壁，并且可更进一步地覆盖盖板110的侧壁，使得在半导体基底100、间隔层106与盖板110之间的界面不会暴露在外界环境中。因此，可避免晶片封装体被水气渗透。
图4A-4I是显示依据本发明的一实施例，制造晶片封装体的各步骤的部分剖面示意图。参阅图4A，首先，在晶圆厂制造阶段提供一半导体基底100，例如为带有晶片的晶圆，其具有第一表面100a与相对的第二表面100b，多个半导体元件102形成于第二表面100b上，多个导电垫102a形成于第二表面100b上，且与每个半导体元件102电性连接。
接着，进行封装阶段，在一实施例中，晶圆100的第二表面100b被贴附至作为载体的盖板110上，盖板110可由玻璃、石英、蛋白石、塑胶或其它可供光线进出的透明基板制成。此外，也可以选择性地在盖板110上形成滤光片以及/或抗反射层。在一实施例中，间隔层106可在盖板110上或晶圆100上形成，然后将盖板110与晶圆100互相贴附，借此在盖板110与晶圆100之间形成空穴112，如图4A所示。空穴112被间隔层106所围绕，间隔层106的材料可以是环氧树脂、阻焊材料或任何其他合适的支撑材料，例如无机材料或者为聚亚酰胺的有机材料。为了增加封装体的密封性，当间隔层106形成于盖板110上时，可在间隔层106与晶圆100之间施加粘着层104；另外，当间隔层106形成于晶圆100上时，可在间隔层106与盖板110之间施加粘着层。接着，可选择性地在晶圆100的第一表面100a上进行薄化步骤，此薄化步骤可以是蚀刻、铣削(milling)、磨削(grinding)或研磨(polishing)制程。
参阅图4B，通过移除制程，例如钻孔(drilling)或蚀刻制程，在晶圆100内形成多个贯穿孔114，其沿着由第一表面100a向第二表面100b的方向延伸，导电垫102a经由贯穿孔114暴露出来。
参阅图4C，为了将半导体基底100与后续形成的导线层隔绝，可顺应性地形成绝缘材料覆盖半导体基底的第一表面100a，并且延伸至贯穿孔114的侧壁与底部。然后，将绝缘材料图案化，移除在贯穿孔114底部的绝缘材料，形成图案化的绝缘层118，在贯穿孔114底部的导电垫102a通过图案化的绝缘层118而暴露出来。在一实施例中，绝缘层118可由感光性绝缘材料形成。在此实施例中，感光性绝缘材料可以是感光性有机高分子材料，其成分包括，但不限定于聚亚酰胺(polyimide；PI)、苯环丁烯(butylcyclobutene；BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)及丙烯酸酯(accrylates)等材料。此感光性有机高分子材料可通过涂布制程形成，例如旋转涂布(spin coating)、喷涂(spray coating)或淋幕涂布(curtain coating)，或者是其它适合的沉积制程。
参阅图4D，在整个绝缘层118上形成导电材料，此导电材料顺应性地形成在晶圆100的第一表面100a之上，并且延伸至贯穿孔114的侧壁与底部。在一实施例中，导电材料可以是铜、铝、银、镍或前述金属的合金，其可以通过物理气相沉积(PVD)或溅镀制程顺应性地沉积。然后，通过微影与蚀刻制程将导电材料图案化，形成图案化的导线层120。图案化的导线层120从晶圆100的第一表面100a延伸至贯穿孔114的侧壁及底部，与在贯穿孔114底部的导电垫电性连接。为了电性隔绝，两个相邻的晶片10a与10b的图案化导线层120之间会有空隙存在。
参阅图4E，通过涂布制程，例如旋转涂布、喷涂或淋幕涂布等制程，形成缓冲材料122覆盖晶圆100的整个第一表面100a，并填充贯穿孔114。在一实施例中，缓冲材料122可以是感光性材料，例如无填充物的环氧基光致抗蚀剂(epoxy based photoresist)。接着，参阅图4F，通过曝光与显影制程将缓冲材料122图案化，留下部分的缓冲材料122在贯穿孔114内，形成缓冲插塞124，缓冲插塞124可以是在每个贯穿孔114内的插塞。然后，将贯穿孔114内的缓冲插塞124固化，但是不完全固化，以降低缓冲插塞124与后续形成的保护层之间的附着力。因此，缓冲插塞124可抵抗在热循环试验期间来自保护层的向上拉拔力，并避免在贯穿孔114内的导线层120发生脱层。此外，因为缓冲插塞124并未完全固化，在至少两个贯穿孔114内形成的缓冲插塞124于剖面上会有不同的形状，例如，在一贯穿孔114内的缓冲插塞124与另一贯穿孔114内的缓冲插塞124的剖面形状不同。
接着，参阅图4G，沿着介于两个相邻的晶片10a与10b之间的切割线SL形成沟槽开口130，可通过预切割(pre-cutting)制程经由切割刀形成沟槽开口130，使得沟槽开口130在半导体基底100以及间隔层106的侧壁上具有倾斜的面，并且沟槽开口130可更进一步地形成在盖板110的侧壁上。此外，沟槽开口130在剖面上具有曲线形状。在一实施例中，沟槽开口130可由半导体基底100的第一表面100a延伸至间隔层106的任何深度处而形成。在另一实施例中，沟槽开口130可由半导体基底100的第一表面100a延伸至盖板110的任何深度处而形成。
参阅图4H，形成保护层126覆盖晶圆100的第一表面100a，并填充贯穿孔114与沟槽开口130。在贯穿孔114内的缓冲插塞124被保护层126覆盖，并且半导体基底100、间隔层106以及盖板110的侧壁也被保护层126覆盖。保护层126可以是带有填充物的阻焊材料(solder mask with fillers)，填充物的材料例如为碳化硅、氧化硅或氧化铝。
参阅图4I，导电凸块128穿过保护层126形成，以与导线层120电性连接。在一实施例中，于形成保护层126之后，可通过将保护层126图案化，形成开口暴露出部分的导线层120。接着，通过电镀或网版印刷(screen printing)方式在上述开口内填充焊接材料，然后进行回焊(re-flow)制程形成导电凸块128，其例如为锡球或焊垫。然后，沿着切割线SL将上述晶圆级晶片封装体切割，分离各个晶片，形成多个如图3所示的晶片封装体。
依据本发明的一实施例，位于切割线SL上的沟槽开口130是通过预切割制程形成，因此沟槽开口130可由半导体基底100的第一表面100a延伸至间隔层106，或更进一步地延伸至盖板110。此外，在切割制程之后，形成晶片封装体的凹陷部130，并且凹陷部130被保护层126覆盖，因此，在凹陷部130内的保护层126可有效地避免晶片封装体被水气渗透。
另外，在本发明的一实施例中，在凹陷部130内没有缓冲插塞存在，因此，在凹陷部130内的保护层126的附着力比贯穿孔114内的保护层126的附着力强，借此可避免凹陷部130内的保护层126发生脱层。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (10)

1.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面和一与该第一表面相对的第二表面；
一间隔层，设置在该半导体基底的该第二表面之下；
一盖板，设置在该间隔层之下；
一凹陷部，邻接该半导体基底的一侧壁；
一贯穿孔，设置于该半导体基底的该第一表面上，且由该第一表面延伸至该第二表面；以及
一保护层，设置于该半导体基底的该第一表面之上，且填充于该凹陷部与该贯穿孔内。
2.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部由该半导体基底的该第一表面延伸至该间隔层。
3.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部由该半导体基底的该第一表面延伸至该盖板。
4.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部与该贯穿孔同时形成。
5.根据权利要求4所述的晶片封装体，其特征在于，该凹陷部由该半导体基底的该第一表面延伸至该第二表面。
6.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部在该贯穿孔之后形成。
7.根据权利要求6所述的晶片封装体，其特征在于，该凹陷部经由一预切割制程形成。
8.根据权利要求1所述的晶片封装体，其特征在于，该贯穿孔内还包括一缓冲插塞，且该缓冲插塞设置于该保护层下方。
9.根据权利要求8所述的晶片封装体，其特征在于，还包括一导线层顺应性地设置于该半导体基底的该第一表面之上，延伸至该贯穿孔内，且设置于该缓冲插塞下方，以及设置在该凹陷部邻接该半导体基底的该侧壁上。
10.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部具有一倾斜面。
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CN104900607A (zh) * 2014-03-07 2015-09-09 精材科技股份有限公司 晶片封装体及其制造方法
CN105742304A (zh) * 2014-12-26 2016-07-06 精材科技股份有限公司 感光模组及其制造方法
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