CN106469699A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN106469699A
CN106469699A CN201510518731.XA CN201510518731A CN106469699A CN 106469699 A CN106469699 A CN 106469699A CN 201510518731 A CN201510518731 A CN 201510518731A CN 106469699 A CN106469699 A CN 106469699A
Authority
CN
China
Prior art keywords
nude film
die attached
semiconductor device
pad
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510518731.XA
Other languages
English (en)
Inventor
栾竟恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
STMicroelectronics Pte Ltd
Original Assignee
STMicroelectronics Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Pte Ltd filed Critical STMicroelectronics Pte Ltd
Priority to CN202110495531.2A priority Critical patent/CN113257766A/zh
Priority to CN201510518731.XA priority patent/CN106469699A/zh
Priority to US14/981,338 priority patent/US10269583B2/en
Publication of CN106469699A publication Critical patent/CN106469699A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06506Wire or wire-like electrical connections between devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本公开的实施例涉及半导体装置及其制造方法。所述半导体装置包括:裸片附接焊盘;钉头凸点,位于所述裸片附接焊盘上并且与所述裸片附接焊盘直接接触;第一裸片,位于所述钉头凸点上并且与所述钉头凸点电耦合;以及导电附接材料,位于所述裸片附接焊盘和所述第一裸片之间。

Description

半导体装置及其制造方法
技术领域
本公开涉及半导体技术领域,更具体而言,涉及半导体装置及其制造方法。
背景技术
在堆叠半导体装置中,通常需要在堆叠的半导体器件之间进行互连来实现电信号的传输。半导体器件通常使用金属接合焊盘来实现电路之间的连接,其中适用于接合焊盘的金属通常主要是铝,并且可能继续是铝,这是因为其可靠的沉积和图案化特性。然而,与其它金属(诸如铜)相比,铝具有相对高的电阻率并且在制造过程中容易被氧化,这继而导致结合处的电阻不稳定,甚至可能导致间歇性故障。
已经提出了一些技术来替代,例如焊盘上金属化(over padmetallization)技术,其通常使用诸如钯、镍、金之类的贵金属,这使得半导体器件的制造成本飞升。
发明内容
鉴于上述问题,本公开的实施例提出一种新的解决方案。
根据本公开的第一方面,提供了一种半导体装置,包括:裸片附接焊盘;钉头凸点,位于所述裸片附接焊盘上并且与所述裸片附接焊盘直接接触;第一裸片,位于所述钉头凸点上并且与所述钉头凸点电耦合;以及导电附接材料,位于所述裸片附接焊盘和所述第一裸片之间。
可选地,该半导体装置还包括:基板,所述裸片附接焊盘位于所述基板上。
可选地,该半导体装置还包括:第二裸片,所述裸片附接焊盘位于所述第二裸片上并且与所述第二裸片电耦合。
可选地,该半导体装置还包括:基板,所述第二裸片位于所述基板上。
可选地,该半导体装置还包括:树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
可选地,该半导体装置还包括:引线框架,所述裸片附接焊盘耦合至所述引线框架。
可选地,该半导体装置还包括:树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
可选地,通过超声波处理来实现所述钉头凸点与所述裸片附接焊盘的直接接触。
根据本公开的另一方面,提供一种电子设备,包括上述项中任一项所述的半导体装置。
根据本公开的又一方面,提供一种制造半导体装置的方法,包括:提供裸片附接焊盘;在所述裸片附接焊盘上提供钉头凸点,使得所述裸片附接焊盘与所述钉头凸点直接接触;在所述裸片附接焊盘上提供导电附接材料;以及在所述钉头凸点和所述导电附接材料上提供第一裸片。
可选地,提供裸片所述附接焊盘包括在基板上提供所述裸片附接焊盘。
可选地,提供裸片所述附接焊盘包括在第二裸片上提供所述裸片附接焊盘,使得所述裸片附接焊盘与所述第二裸片电耦合。
可选地,该方法还包括提供基板,使得所述第二裸片位于所述基板上。
可选地,该方法还包括:使用树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
可选地,该方法还包括:提供引线框架,使得所述裸片附接焊盘耦合至所述引线框架。
可选地,该方法还包括:使用树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
可选地,使用超声波对所述半导体装置进行处理,使得至少去除所述裸片附接焊盘表面上的部分金属氧化物层,从而实现所述裸片附接焊盘与所述钉头凸点的直接接触。
通过使用根据本公开的实施例的制造半导体装置的方法,可以显著减小制造成本。
附图说明
通过结合附图对本公开示例性实施方式进行更详细的描述,本公开的上述以及其它目的、特征和优势将变得更加明显,其中,在本公开示例性实施方式中,相同的参考标号通常代表相同部件。
图1是一种常规堆叠半导体装置的示意图;
图2是根据本公开的一个实施例的半导体装置的示意图;
图3是根据本公开的另一实施例的半导体装置的示意图;以及
图4是根据本公开的又一实施例的半导体装置的示意图。
具体实施方式
现在下文描述中阐述某些具体细节以便提供对本公开的主题内容的各种方面的透彻理解。然而在不具有这些具体细节的情形下仍然可以实现本公开的主题内容。
除非上下文另有要求,否则在说明书和所附权利要求书全文中,词语“包括”将解释成开放式包含意义,也就是说,解释为“包括但不限于”。
在本说明书全文中引用“一个实施例”或者“实施例”意味着结合该实施例描述的特定特征、结构或者特性包含于至少一个实施例中。因此,在本说明书全文中各处出现表达“在一个实施例中”或者“在实施例中”未必都是指相同方面。另外,可以在本公开内容的一个或者多个方面中以任何适当方式组合特定特征、结构或者特性。
参见图1,图1示出了一种常规的堆叠半导体装置100的示意图。在半导体装置100中,具有基板/引线框架101,其中基板/引线框架101可以是印刷电路板、玻璃、陶瓷、金属等材料制成的用于支撑和/或传输电学信号的平板。可选地,基板材料具有优良的导热性能以将芯片中产生的热量传导至外部环境/装置。在基板/引线框架101上,其中集成了电路的第二或底部裸片103通过裸片附接材料102被附接至基板/引线框架101。裸片附接材料诸如是焊料、粘着剂、导电胶等,并且可以根据实际需要而为导电或非导电的。在图1的示例中,底部芯片103的上表面具有键合焊盘105和顶部附接焊盘104。在图1中,键合焊盘105经由接线107键合至基板或引线框架101。第一或顶部裸片108经由顶部炉盘附接材料106被附接至底部芯片103的顶表面上的裸片附接焊盘104。由于需要在顶部芯片和底部芯片之间传输电学信号或功率,因此,附接材料106是导电的,诸如导电焊接、导电粘着剂或导电胶等。顶部芯片108的上表面上也具有键合焊盘,该键合焊盘同样经由接线被键合至底部芯片103上的焊盘。
在实际制造过程中,通常使用铝来制作顶部附接焊盘104,但是铝焊盘的表面容易被氧化,形成氧化铝的膜。由于氧化铝的绝缘性,这容易导致接合电阻不稳以及电学性能的故障。现有的解决技术方案例如通过使用焊盘上金属化技术方案。参见中国专利申请CN102754203,其公开了一种多层焊盘上金属化的接合焊盘及形成方法。这种方法通常使用钯、镍之类的贵金属来金属化,并且需要多个掩膜来图案化,这导致半导体装置的制造成本急剧上升。
本公开的实施例构思了一种新的技术方案来解决该技术问题。参见图2,其示出了根据本公开的一个实施例的半导体装置。图2与图1相似的部件以相似的附图标记示出,并且不再赘述。在图2的实施例中,底部裸片203通过裸片接合材料202接合至衬底/引线框架201,并且通过接线203电耦合至衬底/引线框架201。在底部裸片203的上表面上具有键合焊盘205和附接焊盘204。在附接焊盘204上,设置了钉头凸点210。图中示出了4个钉头凸点,但是可以理解,可以具有一个或其它多个钉头凸点。优选地,为了保持顶部裸片的稳定,设置多个钉头凸点,例如,3个或4个钉头凸点。钉头凸点210与附接焊盘204直接接触,钉头凸点210的周围是裸片附接材料206,顶部裸片208位于定钉头凸点210和裸片附接材料206上,并且与钉头凸点210和附接材料206电耦合。此外,顶部裸片208也通过接线电耦合至底部裸片203。
如前针对图1所述,由于裸片附接焊盘204上容易生长的诸如氧化物(例如氧化铝)之类的绝缘膜导致的间歇性故障,因此有必要破坏氧化物膜,使得顶部裸片208和焊盘204之间形成性能良好的电连接。通过研究发现,相比于现有技术中的焊盘上金属化的技术方案,根据本发明的实施例的技术方案,可以实现在顶部裸片208和焊盘204之间形成性能良好的电连接,而无需显著增加制造成本。
通过研究发现,可以在焊盘204上焊接钉头凸点(例如由金制成的钉头凸点),使用超声波能量来破坏焊盘204表面上的薄的氧化层,从而实现钉头凸点210与焊盘204的直接接触。超声波能量使得钉头凸点210与焊盘表面的薄氧化层摩擦,从而破坏氧化层并且实现钉头凸点与金属焊盘204的直接接触。本领域技术人员可以理解,超声波仅是示例,可以使用其它技术手段来实现钉头凸点与金属焊盘的直接连接。例如,在真空环境下或在还原气氛中制造焊盘204并且施加钉头凸点。
图3是根据本公开的另一实施例。图3与图2相似的部件以相似的附图标记示出,并且不再赘述。在图3的示例中,去除了底部裸片。换言之,在图3的实施例中,半导体装置300仅具有一个裸片,即裸片308。但是本领域技术人员可以理解,图3仅是示例,可以有其它布置,例如3个或更多个堆叠的半导体裸片,其中,裸片之间的电耦合方式与前面针对图2描述的耦合方式相似,在此也不再赘述。
在图3的示例中,钉头凸点310直接设置在有机基板301的上表面上的铝焊盘上,并且在钉头凸点310的周围涂覆导电胶306,裸片308继而通过导电胶电耦合至接合焊盘。裸片308上可以具有些键合焊盘,并且通过接线电耦合至有机基板301,在有机基板301中,具有一些电路部件,与裸片308电耦合。在图3的示例中,也通过诸如超声波之类的手段破坏钉头凸点310与焊盘之间的薄的氧化层,使得钉头凸点310与焊盘直接电耦合。最终通过树脂密封该半导体装置。此外,钉头凸点帮助维持裸片平整,减少倾斜,维持导电胶306的厚度。使半导体装置达到最好的性能。
图4示出了根据本公开的又一示例,图4与图2相似的部件以相似的附图标记示出,并且不再赘述。在图4的示例中,在引线框架上提供裸片附接焊盘404,在附接焊盘404上提供钉头凸点410,并且在钉头凸点周围具有焊料/导电胶406。裸片408在钉头凸点410和导电胶406上,并且经由钉头凸点410和导电胶406电耦合至附接焊盘404。在图4的示例中,在裸片408的上表面上也可以具有键合焊盘,并且经由接线电耦合至引线框架。半导体装置400由树脂409密封。此外,钉头凸点帮助维持裸片平整,减少倾斜,维持导电胶406的厚度。使半导体装置达到最好的性能。
下面说明本公开的实施例的半导体装置的制造方法。在根据本公开的一个实施例中,以矩阵阵列的形式,提供多个基板或引线框架,在多个基板或引线框架中的每个基板或引线框架上提供裸片接合材料,并且通过该接合材料接合底部裸片。继而,在底部裸片上提供裸片附接焊盘;在裸片附接焊盘上提供钉头凸点,在所述裸片附接焊盘上在钉头凸点周围提供导电附接材料;以及在所述钉头凸点和所述导电附接材料上提供顶部裸片,使得顶部裸片接合至导电附接材料和钉头凸点。随后执行接线键合工艺,并且在该工艺过程中使用超声波能量破坏钉头凸点下的薄的氧化膜。然后,使用树脂密封。最后将具有多个半导体装置的晶片切割为单个的半导体装置芯片。
本领域技术人员可以理解,上述方法的执行顺序只是示例说明而非限定,可以有其它执行顺序。
概括而言,根据本公开的第一方面,提供了一种半导体装置,包括:裸片附接焊盘;钉头凸点,位于所述裸片附接焊盘上并且与所述裸片附接焊盘直接接触;第一裸片,位于所述钉头凸点上并且与所述钉头凸点电耦合;以及导电附接材料,位于所述裸片附接焊盘和所述第一裸片之间。
可选地,该半导体装置还包括:基板,所述裸片附接焊盘位于所述基板上。
可选地,该半导体装置还包括:第二裸片,所述裸片附接焊盘位于所述第二裸片上并且与所述第二裸片电耦合。
可选地,该半导体装置还包括:基板,所述第二裸片位于所述基板上。
可选地,该半导体装置还包括:树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
可选地,该半导体装置还包括:引线框架,所述裸片附接焊盘耦合至所述引线框架。
可选地,该半导体装置还包括:树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
可选地,通过超声波处理来实现所述钉头凸点与所述裸片附接焊盘的直接接触。
根据本公开的另一方面,提供一种电子设备,包括上述项中任一项所述的半导体装置。
根据本公开的又一方面,提供一种制造半导体装置的方法,包括:提供裸片附接焊盘;在所述裸片附接焊盘上提供钉头凸点,使得所述裸片附接焊盘与所述钉头凸点直接接触;在所述裸片附接焊盘上提供导电附接材料;以及在所述钉头凸点和所述导电附接材料上提供第一裸片。
可选地,提供裸片所述附接焊盘包括在基板上提供所述裸片附接焊盘。
可选地,提供裸片所述附接焊盘包括在第二裸片上提供所述裸片附接焊盘,使得所述裸片附接焊盘与所述第二裸片电耦合。
可选地,该方法还包括提供基板,使得所述第二裸片位于所述基板上。
可选地,该方法还包括:使用树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
可选地,该方法还包括:提供引线框架,使得所述裸片附接焊盘耦合至所述引线框架。
可选地,该方法还包括:使用树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
可选地,使用超声波对所述半导体装置进行处理,使得至少去除所述裸片附接焊盘表面上的部分金属氧化物层,从而实现所述裸片附接焊盘与所述钉头凸点的直接接触。
此外,尽管在附图中以特定顺序描述了本公开的实施例的方法的操作,但是,这并非要求或者暗示必须按照该特定顺序来执行这些操作,或是必须执行全部所示的操作才能实现期望的结果。相反,流程图中描绘的步骤可以改变执行顺序。附加地或备选地,可以省略某些步骤,将多个步骤合并为一个步骤执行,和/或将一个步骤分解为多个步骤执行。
虽然已经参考若干具体实施方式描述了本公开的实施例,但是应该理解,本公开的实施例并不限于所公开的具体实施方式。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。所附权利要求的范围符合最宽泛的解释,从而包含所有这样的修改及等同结构和功能。

Claims (17)

1.一种半导体装置,包括:
裸片附接焊盘;
钉头凸点,位于所述裸片附接焊盘上并且与所述裸片附接焊盘直接接触;
第一裸片,位于所述钉头凸点上并且与所述钉头凸点电耦合;以及
导电附接材料,位于所述裸片附接焊盘和所述第一裸片之间。
2.根据权利要求1所述的半导体装置,还包括:
基板,所述裸片附接焊盘位于所述基板上。
3.根据权利要求1所述的半导体装置,还包括:
第二裸片,所述裸片附接焊盘位于所述第二裸片上并且与所述第二裸片电耦合。
4.根据权利要求3所述的半导体装置,还包括:
基板,所述第二裸片位于所述基板上。
5.根据权利要求2或4所述的半导体装置,还包括:
树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
6.根据权利要求1所述的半导体装置,还包括:
引线框架,所述裸片附接焊盘耦合至所述引线框架。
7.根据权利要求6所述的半导体装置,还包括:
树脂,所述树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
8.根据权利要求1-7中任一项所述的半导体装置,其中通过超声波处理来实现所述钉头凸点与所述裸片附接焊盘的直接接触。
9.一种电子设备,包括根据权利要求1-8中任一项所述的半导体装置。
10.一种制造半导体装置的方法,包括:
提供裸片附接焊盘;
在所述裸片附接焊盘上提供钉头凸点,使得所述裸片附接焊盘与所述钉头凸点直接接触;
在所述裸片附接焊盘上提供导电附接材料;以及
在所述钉头凸点和所述导电附接材料上提供第一裸片。
11.根据权利要求10所述的方法,其中提供裸片所述附接焊盘包括:
在基板上提供所述裸片附接焊盘。
12.根据权利要求10所述的方法,其中提供裸片所述附接焊盘包括:
在第二裸片上提供所述裸片附接焊盘,使得所述裸片附接焊盘与所述第二裸片电耦合。
13.根据权利要求12所述的方法,还包括:
提供基板,使得所述第二裸片位于所述基板上。
14.根据权利要求11或13所述的方法,还包括:
使用树脂包封所述第一裸片、所述导电附接材料和所述基板或者包封所述第一裸片、所述第二裸片、所述导电附接材料和所述基板。
15.根据权利要求10所述的方法,还包括:
提供引线框架,使得所述裸片附接焊盘耦合至所述引线框架。
16.根据权利要求15所述的方法,还包括:
使用树脂包封所述第一裸片、所述导电附接材料和所述引线框架。
17.根据权利要求10-16中任一项所述的方法,其中使用超声波对所述半导体装置进行处理,使得至少去除所述裸片附接焊盘表面上的部分金属氧化物层,从而实现所述裸片附接焊盘与所述钉头凸点的直接接触。
CN201510518731.XA 2015-08-21 2015-08-21 半导体装置及其制造方法 Pending CN106469699A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202110495531.2A CN113257766A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法
CN201510518731.XA CN106469699A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法
US14/981,338 US10269583B2 (en) 2015-08-21 2015-12-28 Semiconductor die attachment with embedded stud bumps in attachment material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510518731.XA CN106469699A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202110495531.2A Division CN113257766A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法

Publications (1)

Publication Number Publication Date
CN106469699A true CN106469699A (zh) 2017-03-01

Family

ID=58157719

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201510518731.XA Pending CN106469699A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法
CN202110495531.2A Pending CN113257766A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202110495531.2A Pending CN113257766A (zh) 2015-08-21 2015-08-21 半导体装置及其制造方法

Country Status (2)

Country Link
US (1) US10269583B2 (zh)
CN (2) CN106469699A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2589568A (en) 2019-11-28 2021-06-09 Prevayl Ltd Sensor device, system and wearable article
GB2589567A (en) * 2019-11-28 2021-06-09 Prevayl Ltd Semiconductor package, article and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040080055A1 (en) * 2002-06-24 2004-04-29 Tongbi Jiang No flow underfill material and method for underfilling semiconductor components
CN101345199A (zh) * 2007-07-11 2009-01-14 台湾积体电路制造股份有限公司 一种封装结构及其形成方法
US20110042798A1 (en) * 2009-08-21 2011-02-24 Stats Chippac, Ltd. Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
CN104425429A (zh) * 2013-08-29 2015-03-18 英飞凌科技股份有限公司 具有多层裸片组块的半导体封装
CN205016516U (zh) * 2015-08-21 2016-02-03 意法半导体有限公司 半导体装置和电子设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030009876A1 (en) * 2000-01-14 2003-01-16 Akira Yamauchi Method and device for chip mounting
JP3813797B2 (ja) * 2000-07-07 2006-08-23 株式会社ルネサステクノロジ 半導体装置の製造方法
TW200511531A (en) * 2003-09-08 2005-03-16 Advanced Semiconductor Eng Package stack module
KR101003585B1 (ko) * 2008-06-25 2010-12-22 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US8394713B2 (en) 2010-02-12 2013-03-12 Freescale Semiconductor, Inc. Method of improving adhesion of bond pad over pad metallization with a neighboring passivation layer by depositing a palladium layer
US20140291834A1 (en) * 2013-03-27 2014-10-02 Micron Technology, Inc. Semiconductor devices and packages including conductive underfill material and related methods
US9583420B2 (en) * 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
JP2015146384A (ja) * 2014-02-03 2015-08-13 イビデン株式会社 プリント配線板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040080055A1 (en) * 2002-06-24 2004-04-29 Tongbi Jiang No flow underfill material and method for underfilling semiconductor components
CN101345199A (zh) * 2007-07-11 2009-01-14 台湾积体电路制造股份有限公司 一种封装结构及其形成方法
US20110042798A1 (en) * 2009-08-21 2011-02-24 Stats Chippac, Ltd. Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
CN104425429A (zh) * 2013-08-29 2015-03-18 英飞凌科技股份有限公司 具有多层裸片组块的半导体封装
CN205016516U (zh) * 2015-08-21 2016-02-03 意法半导体有限公司 半导体装置和电子设备

Also Published As

Publication number Publication date
US20170053856A1 (en) 2017-02-23
US10269583B2 (en) 2019-04-23
CN113257766A (zh) 2021-08-13

Similar Documents

Publication Publication Date Title
TWI294757B (en) Circuit board with a through hole wire, and forming method thereof
JP5587844B2 (ja) パワー半導体モジュールおよびその製造方法
CN101189717B (zh) 内装半导体元件的印刷布线板及其制造方法
CN101013686B (zh) 互连衬底、半导体器件及其制造方法
TW393709B (en) Flip chip assembly with via interconnection
WO2007088851A1 (ja) Inハンダ被覆銅箔リボン導線及びその接続方法
US20100186231A1 (en) Method for producing a metal-ceramic substrate for electric circuits on modules
CN103493610A (zh) 刚性柔性基板及其制造方法
WO1998038261A1 (en) Adhesive, liquid crystal device, method of manufacturing liquid crystal device, and electronic apparatus
JPH02152245A (ja) 多数の回路要素を取り付けうる両面回路板
TW200807588A (en) Semiconductor device, built-up type semiconductor device using the same, base substrate, and manufacturing method of semiconductor device
CN105210462B (zh) 元器件内置基板的制造方法及元器件内置基板
TW201320276A (zh) 封裝基板及其製法
CN106469699A (zh) 半导体装置及其制造方法
CN100468670C (zh) 带有大面积接线的功率半导体器件的连接技术
JP2014053597A (ja) チップ型電子部品及び接続構造体
CN205016516U (zh) 半导体装置和电子设备
JPWO2014097835A1 (ja) 樹脂多層基板
CN111162047A (zh) 布线基板和电子装置
JPH0342860A (ja) フレキシブルプリント配線板
JPH02222598A (ja) 半導体装置モジュール
JP2004128042A (ja) 半導体装置の製造方法及び半導体装置
TWI769010B (zh) 異質基板結構及其製作方法
WO2023273808A1 (zh) 半导体封装方法及半导体封装结构
JPH11204941A (ja) 回路基板の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170301

RJ01 Rejection of invention patent application after publication