WO2023273808A1 - 半导体封装方法及半导体封装结构 - Google Patents

半导体封装方法及半导体封装结构 Download PDF

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Publication number
WO2023273808A1
WO2023273808A1 PCT/CN2022/097361 CN2022097361W WO2023273808A1 WO 2023273808 A1 WO2023273808 A1 WO 2023273808A1 CN 2022097361 W CN2022097361 W CN 2022097361W WO 2023273808 A1 WO2023273808 A1 WO 2023273808A1
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WIPO (PCT)
Prior art keywords
layer
passive device
die
electrical connection
substrate layer
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PCT/CN2022/097361
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English (en)
French (fr)
Inventor
涂旭峰
霍炎
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矽磐微电子(重庆)有限公司
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Priority to US18/547,864 priority Critical patent/US20240321846A1/en
Publication of WO2023273808A1 publication Critical patent/WO2023273808A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a semiconductor packaging method and a semiconductor packaging structure.
  • One aspect of the present application provides a semiconductor packaging method, comprising:
  • a substrate layer is provided on the front side of the passive device; the front side of the passive device has electrical connectors, and the substrate layer is provided with a substrate layer opening penetrating through two opposite surfaces of the substrate layer, and the substrate layer opening is connected to the substrate layer Corresponding to the above electrical connectors;
  • a protective layer is formed on the front side of the bare chip, and an opening in the protective layer is formed on the protective layer; wherein, the front side of the bare chip is provided with a soldering pad, and the opening of the protective layer is in contact with the soldering pad on the front side of the bare chip correspond;
  • An encapsulation layer is formed, the encapsulation layer encapsulating at least sides of the die and the passive device.
  • the above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the embodiment of the present application solve the technical problem that the tin terminal surface of some passive devices cannot be directly packaged by pre-arranging the substrate layer on the surface of the passive device, and are conducive to ensuring the safety of the passive device. Stability and reliability.
  • Protective layers are respectively formed on the fronts of the bare chips, which can protect the fronts of the bare chips during the molding process, so as to prevent the fronts of the bare chips from being damaged by the penetration of the molding material.
  • the formation of the substrate layer opening and the protective layer opening enables the electrical connectors on the passive device and the pads on the front side of the bare chip to be accurately positioned through the corresponding openings before the subsequent panel level packaging process.
  • FIG. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
  • FIGS. 2-15 are process flow charts of a semiconductor packaging method according to an exemplary embodiment of the present application.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. Words such as “upper” and/or “lower” are for convenience of description only, and are not limited to a position or a spatial orientation.
  • Words such as “upper” and/or “lower” are for convenience of description only, and are not limited to a position or a spatial orientation.
  • the singular forms “a”, “the” and “the” are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term “and/or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
  • a substrate layer is provided on the front side of the passive device; the front side of the passive device has an electrical connector, and the substrate layer is provided with a substrate layer opening penetrating through two opposite surfaces of the substrate layer, The substrate layer opening corresponds to the electrical connector; and a protective layer is formed on the front of the bare chip, and a protective layer opening is formed on the protective layer; wherein, the front of the bare chip is provided with a solder pad, the The opening of the protective layer corresponds to the welding pad on the front side of the die; then, the passive device and the die are mounted on the carrier board at intervals; wherein, the front side of the die faces the carrier board, so The front side of the passive device faces the carrier plate; finally, an encapsulation layer is formed, and the encapsulation layer is formed, and the en
  • the above-mentioned embodiment of the present application solves the technical problem that the tin terminal surface of some passive devices cannot be directly packaged by pre-arranging the substrate layer on the surface of the passive device, and is beneficial to ensure the stability and reliability of the passive device.
  • Protective layers are respectively formed on the fronts of the bare chips, which can protect the fronts of the bare chips during the molding process, so as to prevent the fronts of the bare chips from being damaged by the penetration of the molding material.
  • the formation of the substrate layer opening and the protective layer opening enables the electrical connectors on the passive device and the pads on the front side of the bare chip to be accurately positioned through the corresponding openings before the subsequent panel level packaging process.
  • the packaging method of the present application is beneficial to reduce the size of the system-level package structure.
  • the small size is conducive to the realization of product miniaturization, and makes the distance between the bare chip and passive components closer, the response time is shorter, and the electrical performance of the product is improved.
  • the present application provides a semiconductor packaging method and a semiconductor packaging structure.
  • FIG. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in Figure 1, the semiconductor packaging method includes the following steps 101 to 107:
  • Step 101 setting a substrate layer on the front side of the passive device; the front side of the passive device has an electrical connector, and the substrate layer is provided with a substrate layer opening penetrating through two opposite surfaces of the substrate layer, and the substrate layer The opening corresponds to the electrical connector.
  • Step 103 Form a protective layer on the front side of the die, and form an opening in the protective layer on the protective layer; wherein, the front side of the die is provided with a soldering pad, and the opening of the protective layer is similar to the soldering pad on the front side of the die correspond.
  • Step 105 Mount the passive device and the die on the carrier board at intervals; wherein, the front side of the die faces the carrier board, and the front side of the passive device faces the carrier board.
  • Step 107 forming an encapsulation layer, the encapsulation layer at least encapsulates side surfaces of the die and the passive device.
  • step 101 can be specifically implemented through the following steps 1011 to 1014:
  • Step 1011 providing a substrate 300 .
  • the material of the substrate 300 may be FR-4 or glass fiber.
  • Step 1012 forming a plurality of solder joints of the passive devices 202 arranged in preset positions on the surface of the substrate 300 .
  • the surface on which the solder joints 301 are disposed may be understood as the front side of the substrate 300 .
  • solder joints 301 can be formed by exposure and development.
  • the material of the solder joint 301 includes copper metal, and of course it may also include other metal materials that can conduct electricity and facilitate welding, which is not limited in this application.
  • Step 1013 Weld multiple passive components 202 to different solder joints 301 respectively to form a passive component assembly.
  • the passive devices mentioned here may include electronic devices such as capacitors, resistors or inductors.
  • the passive device 202 has a front surface with electrical connectors disposed on the front surface.
  • a plurality of passive devices can be respectively soldered to different soldering points through a reflow soldering process.
  • the operation of soldering passive components to the substrate by reflow soldering process makes the soldering of passive components stronger and more stable.
  • Step 1014 Divide the substrate 300 of the passive device assembly to form a passive device with a substrate layer 302 on the front.
  • the dicing can be performed along the cutting line shown by the dotted line in FIG. 4 , and the corresponding substrate portion on the front side of each passive device 202 is formed into the substrate layer 302 .
  • a passive device may also be directly provided.
  • the passive device is soldered to the substrate, and the corresponding substrate layer can be formed without cutting the substrate.
  • step 1014 the method includes the following step 1015:
  • Step 1015 Open the substrate layer opening in the substrate layer 302 .
  • step 1015 the method includes the following step 1016:
  • Step 1016 filling the opening of the substrate layer with a first conductive medium to form a first electrical connection portion 3021 electrically connected to the passive device 202, thereby forming a structure as shown in FIG. 5 .
  • the first electrical connection portion 3021 can be electrically connected to the electrical connection piece on the front side of the passive device 202 through the solder joint 301 .
  • the substrate layer opening can also be formed before the passive device is soldered to the substrate, which is not limited in the present application and can be set according to specific circumstances.
  • a protective layer is formed on the front side of the die.
  • the protective layer can be formed on the front side of the semiconductor wafer before cutting the semiconductor wafer into multiple dies, and then the semiconductor wafer is cut to obtain the front side A die with a protective layer is formed.
  • the semiconductor wafer can also be cut into bare chips, and a protective layer can be formed on the front side of each bare chip, which can be selected according to specific application conditions, and this application does not limited.
  • the front side of the die 201 has solder pads 2011 .
  • the welding pad 2011 is used for electrical connection with the outside world.
  • a protection layer 203 is formed on the front surface of the die 201 .
  • the protective layer 203 is made of insulating material.
  • the material of the protective layer can include BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole (Polybenzoxazole), epoxy resin, ABF (Ajinomoto buildup film), polymer matrix dielectric film, organic polymer film, or other materials with similar insulating and structural properties. It can also be an organic/inorganic composite material, such as a resin polymer with inorganic particles added.
  • the protection layer 203 is preferably selected from a material that can adapt to chemical cleaning, grinding and the like.
  • the protection layer 203 can be formed on the die 201 by lamination, coating, printing and the like.
  • a protective layer opening 2031 is formed on the protective layer 203 .
  • the protective layer opening 2031 at least corresponds to the solder pad on the front of the die 201 or the line drawn from the solder pad, so that the solder pad on the front surface of the die 201 or the line drawn from the solder pad is exposed from the protective layer opening 2031 .
  • the material of the protective layer 203 is a laser reactive material
  • the opening 2031 of the protective layer may be formed by laser patterning.
  • the material of the protection layer 203 is a photosensitive material
  • the opening 2031 in the protection layer can be formed by photolithography and patterning.
  • the shape of the protective layer opening 2031 can be round, and of course it can also be in other shapes such as oval, square, linear and so on.
  • FIGS. 6 to 8 only illustrate the formation of a protective layer on the front surface of a die 201 and the formation of protective layer openings in the protective layer.
  • the formation of the protective layer and protective Layer openings can also be formed by referring to this method.
  • the back side of the semiconductor wafer that is, the back side of the corresponding die, can be ground to reduce the thickness of the die.
  • the backside of the bare chip may not be thinned, and this application does not limit this, and it can be set according to the specific application environment.
  • the semiconductor wafer is cut along the cutting line to obtain a plurality of bare chips with a protective layer on the front side.
  • the cutting process can be machine cutting or laser cutting.
  • a protective layer opening is further formed in the protective layer.
  • the protective layer opening can be formed before dicing the semiconductor wafer, and can also be formed after dicing.
  • step 101 and step 103 do not have a sequence. Step 101 and step 103 can be performed simultaneously. Step 101 can be performed before step 103 or after step 103, which is not limited in this application and can be set according to specific application environments.
  • step 105 the passive device 202 with the substrate layer 302 formed in step 101 and the die 201 with the protective layer 203 formed in step 103 are mounted at intervals according to predetermined arrangement positions.
  • the front side of the die 201 faces the carrier 200
  • the front side of the passive device 202 also faces the carrier 200 .
  • the arrangement position of mounting passive components 202 and the arrangement position of mounting die 201 may be set at intervals.
  • the passive device 202 with the substrate layer 302 can be mounted on the carrier board through an adhesive layer (not shown).
  • the adhesive layer is used to bond the passive device 202 with the substrate layer 302, and the adhesive layer can be made of an easy-to-peel material, so that the carrier board and the passive device 202 with the substrate layer 302 can be peeled off in a subsequent process.
  • thermal release materials that can be rendered non-stick by heating can be used.
  • the adhesive layer can adopt a two-layer structure, a heat-separation material layer and an adhesion layer.
  • the heat-separation material layer is pasted on the carrier 200 and loses its viscosity when heated, so that it can be removed from the
  • the carrier board 200 is peeled off, and the adhesive layer adopts an adhesive material layer, which can be used to paste the passive device 202 having the substrate layer 302 .
  • the adhesive layer thereon can be removed by chemical cleaning.
  • the adhesive layer can be formed on the carrier 200 by lamination, printing and other methods.
  • the die 201 with the protective layer 203 can be mounted on the carrier board in the same way. Reference may be made to the relevant description above, and details are not repeated here.
  • the passive device 202 that is, the passive device 202 with the substrate layer 302 and the bare chip 201 (the bare chip 201 with the protective layer 203) are placed on the On the carrier board 200 , for the convenience of expression, only one passive device 202 and one die 201 are shown in the figure. Actually, there are multiple dies 201 and passive devices 202 arranged on the carrier board 200 according to predetermined positions. Optionally, the passive device 202 and the die 201 are disposed on the carrier 200 at intervals.
  • bare chips and passive devices there can be multiple bare chips and passive devices, that is, multiple passive devices with substrate layers and bare chips with protective layers are mounted on the carrier board at the same time for packaging. And after the packaging is completed, it is cut into multiple packages; a package includes a set of passive devices and bare chips, which can specifically include one or more passive devices and one or more bare chips, and this one or The positions of multiple passive components and one or more bare chips can be set according to the needs of actual products.
  • an encapsulation layer 204 is formed on the carrier 200 , the encapsulation layer encloses at least part of the die and at least part of the passive devices.
  • the encapsulation layer 204 covers the surface of the passive device 202 away from the carrier 200 , the surface of the die 201 away from the carrier 200 and the exposed carrier.
  • the encapsulation layer covers the surface of the passive device 202 away from the carrier, the surface of the die 201 away from the carrier 200 and the exposed adhesive layer.
  • the exposed area is also covered by the encapsulation layer. As shown in FIG.
  • the encapsulation layer 204 completely encapsulates the carrier 200, the passive device 202 with the substrate layer 302 on the front surface, and the bare chip 201 with the protective layer 203, so as to restructure a flat plate structure, so that the After the carrier board 200 is peeled off, rewiring and packaging can be continued on the restructured flat structure.
  • the encapsulation layer 204 can be formed by laminating an epoxy resin film or ABF (Ajinomoto buildup film), or by performing injection molding or compression molding on an epoxy resin compound. molding) or transfer molding (Transfer molding).
  • the upper surface 2041 of the encapsulation layer 204 away from the carrier 200 is substantially flat and parallel or substantially parallel to the surface of the carrier 200 .
  • the thickness of the encapsulation layer 204 can be reduced by grinding or polishing the surface away from the carrier 200 .
  • the encapsulation layer 204 When the encapsulation layer 204 is used for encapsulation, because the encapsulation layer needs high pressure molding during molding, the encapsulation material is easy to penetrate between the carrier 200 and the die 201, or between the carrier 200 and the passive device 202. between.
  • the arrangement of the substrate layer 302 and the protective layer 203 in the present application can prevent the encapsulation material from penetrating into the surface of the die 201 and the passive device 202 without directly contacting the front of the die 201 and the front of the passive device 202, thereby No damage will be caused to the circuit structure and passive devices on the front side of the bare chip 201 .
  • the carrier 200 can be peeled off.
  • the adhesive layer can be heated to reduce its viscosity after being heated, and then the carrier 200 can be peeled off.
  • the carrier 200 can also be directly peeled off mechanically.
  • the lower surface of the encapsulation layer 204 facing the carrier 200, the surface of the substrate layer 302, the surface of the protective layer 203, the surface of the first electrical connection part 3021, and the opening 2031 of the protective layer can be exposed. solder pads.
  • a plate structure including the die 201 , the passive device 202 , the substrate layer 302 , the protection layer 203 and the encapsulation layer 204 can be obtained. Except for the protective layer opening 2031 in the plate structure, the surfaces of the components on the side close to the carrier 200 are in the same plane.
  • wiring can be carried out according to the actual situation, so as to realize the electrical connection between the bare chip 201 and the passive device 202 and the outside world, and the electrical connection between the bare chip 2012 and the passive device 202 .
  • a second conductive medium is filled in the protective layer opening 2031 to form a second electrical connection portion 2032 , and the surface of the substrate layer 302 away from the passive device 202 and the protective layer 203 away from the surface of the die 201 forms a wiring layer 205 .
  • the wiring layer 205 is formed on the surface of the substrate layer 302 , the surface of the protective layer 203 , and the surface of the encapsulation layer 204 on the same side.
  • the wiring layer 205 is electrically connected to the first electrical connection portion 3021 and the second electrical connection portion 2032 .
  • the wiring layer 205 is electrically connected to the electrical connector of the passive device 202 through the first electrical connection portion 3021 , and is electrically connected to the pad 2011 on the front side of the die 201 through the second electrical connection portion 2032 .
  • the second electrical connection portion 2032 and the wiring layer 205 are formed in the same conductive layer process.
  • the two may not be formed in the same conductive layer process.
  • the method further includes filling the opening of the substrate layer with a first conductive medium to form a first electrical connection. Electrical connection part 3021.
  • the first electrical connection part 3021 , the second electrical connection part 2032 and the wiring layer 205 are formed in the same conductive layer process.
  • the first electrical connection part 3021 , the second electrical connection part 2032 and the wiring layer 205 may not be formed in the same conductive layer process.
  • the first electrical connection part 3021 and the second electrical connection part 2032 are formed in the same conductive layer process.
  • the wiring layer 205 is formed in another conductive layer process.
  • the first electrical connection part, the second electrical connection part and the wiring layer may also be formed in different wiring layer processes, which is not limited in the present application and may be set according to specific application environments.
  • the second electrical connection portion 2032 can also be formed before step 105, and correspondingly, after the carrier board is peeled off, the wiring layer can be directly provided.
  • the method includes:
  • Ribs are formed at the outer surface of the passive device 202 spaced from the die 201 .
  • the outer surface of the space between the passive device 202 and the die 201 mentioned here can be understood as the surface of the encapsulation layer 204 at the space between the passive device 202 and the die 201 and the substrate layer 302 near the space between the two is away from the passive device
  • the surface of the die 202 , the protection layer 203 is away from the surface of the die 201 .
  • the material and structure of the reinforcing rib may be the same as or similar to that of the wiring layer 205 .
  • the reinforcing rib is not electrically connected with other electrical structures.
  • the rib can be formed in the same process as the wiring layer 205 .
  • a third electrical connection portion 206 is formed on the surface of the wiring layer 205 away from the die 201 and the passive device 202 .
  • a dielectric layer 207 is formed on the wiring layer 205 to protect the wiring layer 205 and the third electrical connection portion 206 .
  • the dielectric layer 207 covers the exposed wiring layer 205, part of the third electrical connection portion 206, the exposed protective layer 203, and the exposed substrate layer 302, and the surface of the third electrical connection portion 206 away from the wiring layer 205 exposes the dielectric layer 207 .
  • the thickness of the formed dielectric layer 207 can be such that the surface of the third electrical connection portion 206 is just exposed; the dielectric layer 207 can also cover all exposed areas on the encapsulation layer 204, the substrate layer 302, the protective layer 203 and the wiring layer 205. surface, and then thinned down to the surface of the third electrical connection portion 206 .
  • the shape of the third electrical connection portion 206 is preferably circular, and of course other shapes such as rectangle and square are also possible, and the third electrical connection portion 206 is electrically connected to the wiring layer 205 .
  • the third electrical connection portion 206 may be formed on the wiring layer 205 by means of photolithography and electroplating.
  • the dielectric layer 207 can be formed on the wiring layer 205, the exposed substrate layer 302, the protective layer 203 and the encapsulation layer 204, and the dielectric layer 207 has a dielectric layer opening, and then form a third electrical connection portion 206 electrically connected to the wiring layer 205 in the dielectric layer opening of the dielectric layer 207 .
  • the dielectric layer 207 can be formed by lamination, molding or printing, preferably using epoxy compound.
  • repeated rewiring can also be performed outside the third electrical connection, for example, one or more wiring layers can be formed outside the dielectric layer in the same way, so as to realize multi-layer wiring of the product wiring.
  • the method includes:
  • External connection keys 208 are formed on the surface of the third electrical connection portion 206 away from the wiring layer 205 .
  • the material of the external connection key 208 may be tin.
  • the external connection key 208 can be formed by tin plating.
  • the external connection key can also be made of other materials, such as copper, nickel-based alloy or other metal materials that can realize electrical connection, and the external connection key can also be formed in other ways, which is not the subject of this application. It is limited and can be set according to the specific situation.
  • the entire package structure is cut into multiple packages by laser or mechanical cutting, that is, the semiconductor package structure, for example, as shown in FIG. 3 shows the semiconductor package structure.
  • FIG. 15 is a schematic structural diagram of a semiconductor packaging structure 1000 obtained according to a semiconductor packaging method provided by an exemplary embodiment of the present application. Please refer to FIG. 15 and, if necessary, in combination with FIGS. 1-14, the semiconductor package structure 1000 includes:
  • the passive device 202 the front side of the passive device 202 has electrical connectors and the front side of the passive device 202 is provided with a substrate layer 302; the substrate layer 302 is provided with substrate layer openings penetrating through the opposite surfaces of the substrate layer 302, and the substrate layer The layer opening corresponds to the electrical connector; a first electrical connection portion 3021 is formed in the substrate layer opening;
  • Nude chip 201 the front side of bare chip 201 is provided with welding pad and the front side of bare chip 201 is formed with protection layer 203; Form protection layer opening 2031 on the protection layer 203, described protection layer opening 2031 and the welding pad 2011 on the front side of die chip 201 Correspondingly; a second electrical connection portion 2032 is formed in the protective layer opening 2031;
  • the encapsulation layer 204 at least encapsulates the side surfaces of the die 201 and the side surfaces of the passive device 202;
  • the wiring layer 205 is formed on the surface of the substrate layer 302 away from the passive device 202 and the surface of the protective layer 203 away from the bare chip 201, and is electrically connected to the passive device 202 through the first electrical connection part 3021 and through the second electrical connection part 2032 is electrically connected to die 201 .
  • the semiconductor package structure 1000 may further include a dielectric layer 207 .
  • the dielectric layer 207 is formed on the wiring layer 205 and the exposed substrate layer 302 , the protection layer 203 , and the encapsulation layer 204 , and has an opening in the dielectric layer.
  • a third electrical connection portion 206 electrically connected to the wiring layer 205 is disposed in the opening of the dielectric layer.
  • the device embodiment and the method embodiment may be complementary to each other if there is no conflict.

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Abstract

本申请提供一种半导体封装方法及半导体封装结构。其中，半导体封装方法包括：在无源器件的正面设置基板层，无源器件的正面具有电性连接件，基板层中设有贯穿基板层相对两表面的基板层开口，基板层开口与电性连接件相对应；在裸片正面形成保护层，并在保护层上形成保护层开口；裸片正面设有焊垫，保护层开口与裸片正面的焊垫相对应；将无源器件和裸片间隔贴装于载板上；裸片的正面朝向载板，无源器件的正面朝向载板；形成包封层，包封层至少包封裸片和无源器件的侧面。通过预先在无源器件表面设置基板层，解决了部分无源器件锡端子面无法直接封装的技术难题，并且有利于保证无源器件的稳定性及可靠性。裸片正面的保护层有利于保护裸片。

Description

半导体封装方法及半导体封装结构 技术领域
本申请涉及一种半导体技术领域，尤其涉及一种半导体封装方法及半导体封装结构。
背景技术
目前，在半导体封装过程中，常常需要将裸片和无源器件，例如电容、电阻、电感等，封装在一个封装体中，以实现一定的功能。这种具有裸片和无源器件的封装体的封装技术，一直备受关注。
发明内容
本申请的一个方面提供一种半导体封装方法，其包括：
在无源器件的正面设置基板层；所述无源器件的正面具有电性连接件，所述基板层中设有贯穿所述基板层相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应；
在裸片的正面形成保护层，并在所述保护层上形成保护层开口；其中，所述裸片的正面设有焊垫，所述保护层开口与所述裸片的正面的焊垫相对应；
将所述无源器件和所述裸片间隔贴装于载板上；其中，所述裸片的正面朝向所述载板，所述无源器件的正面朝向所述载板；
形成包封层，所述包封层至少包封所述裸片和所述无源器件的侧面。
本申请实施例所达到的主要技术效果是：
本申请实施例提供的上述半导体封装方法及半导体封装结构，通过预先在无源器件表面设置基板层，解决了部分无源器件锡端子面无法直接封装的技术难题，并且有利于保证无源器件的稳定性及可靠性。在裸片的正面分别形成保护层，在塑封过程中能够保护裸片的正面，以免塑封材料渗入而损坏裸片的正面。且基板层开口及保护层开口的形成，使得在后续面板级封装工艺之前，无源器件上的电性连接件及裸片正面的焊垫可以通过对应开口实现精准定位。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是根据本申请一实例性实施例提出的半导体封装方法的流程图。
图2-图15是根据本申请一示例性实施例中半导体封装方法的工艺流程图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“上”和/或“下”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
在半导体封装过程中，常常需要将裸片和无源器件，例如电容、电阻、电感等，封装在一个封装体中，以实现一定的功能。本申请提供了一种半导体封装方法。在封装过程中，首先，在无源器件的正面设置基板层；所述无源器件的正面具有电性连接件，所述基板层中设有贯穿所述基板层相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应；以及在裸片正面形成保护层，并在所述保护层上形成保护层开口；其中，所述裸片正面设有焊垫，所述保护层开口与所述裸片正面的焊垫相对应；继而将所述无源器 件和所述裸片间隔贴装于载板上；其中，所述裸片的正面朝向所述载板，所述无源器件的正面朝向所述载板；最后形成包封层，所述包封层至少包封所述裸片和所述无源器件的侧面。本申请的上述实施方式，通过预先在无源器件表面设置基板层，解决了部分无源器件锡端子面无法直接封装的技术难题，并且有利于保证无源器件的稳定性及可靠性。在裸片的正面分别形成保护层，在塑封过程中能够保护裸片的正面，以免塑封材料渗入而损坏裸片的正面。且基板层开口及保护层开口的形成，使得在后续面板级封装工艺之前，无源器件上的电性连接件及裸片正面的焊垫可以通过对应开口实现精准定位。此外，相对于分别封装裸片和无源器件，再通过引线、铜片等连接结构实现二者的连接的实施方式而言，采用本申请的这种封装方式，有利于减小系统级封装结构的体积，有利于实现产品小型化，且使得裸片和无源器件距离更近，响应时间更短，提升产品电性能。
如图1以及图2至图15，本申请提供一种半导体封装方法及半导体封装结构。
图1是根据本申请一实例性实施例提出的半导体封装方法的流程图。如图1所示，半导体封装方法包括下述步骤101至步骤107：
步骤101：在无源器件的正面设置基板层；所述无源器件的正面具有电性连接件，所述基板层中设有贯穿所述基板层相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应。
步骤103：在裸片正面形成保护层，并在所述保护层上形成保护层开口；其中，所述裸片正面设有焊垫，所述保护层开口与所述裸片正面的焊垫相对应。
步骤105：将所述无源器件和所述裸片间隔贴装于载板上；其中，所述裸片的正面朝向所述载板，所述无源器件的正面朝向所述载板。
步骤107：形成包封层，所述包封层至少包封所述裸片和所述无源器件的侧面。
在一些实施例中，请结合图2至图5所示，步骤101具体可通过如下步骤1011至步骤1014实现：
步骤1011：提供基板300。
该基板300的材质可以为FR-4或玻璃纤维等材质。
步骤1012：在基板300的表面形成多个按照预设位置排布的无源器件202的焊点。该设置焊点301的表面可以理解为基板300的正面。
在一些实施例中，焊点301可以通过曝光显影的方式形成。焊点301的材质包括铜金属，当然也可以包括其他能够导电并有利于焊接的金属材质，本申请对此不做限定。
步骤1013：将多个无源器件202分别对应焊接于不同焊点301，形成无源器件组件。
这里所说的无源器件可以包括电容、电阻或电感等电子器件。无源器件202具有正面，其正面设有电性连接件。将无源器件202对应焊接于焊点301时，具体将无源器件202的正面朝向基板300焊接，并将无源器件202的电性连接件对应焊接于焊点301，以与焊点301实现电连接。
在一些实施例中，可以通过回流焊工艺，将多个无源器件分别对应焊接于不同焊点处。采用回流焊工艺将无源器件焊接于基板的操作，使得无源器件被焊接的更加牢固更加稳定。
步骤1014：对所述无源器件组件的基板300进行切分，形成正面设置有基板层302的无源器件。
在一些实施例中，可沿图4中虚线所示的切割线进行切分，每一无源器件202正面对应的基板部分即形成为基板层302。
需要说明的是，在工艺条件允许的情况下，也可仅直接提供较小的用于焊接一个无源器件的基板。相应地，将无源器件焊接于基板，无需对基板进行切分，即可形成相应的基板层。
进一步，在一些实施例中，在步骤1014之后，所述方法包括如下步骤1015：
步骤1015：在基板层302开设所述基板层开口。
可选的，在步骤1015后，所述方法包括如下步骤1016：
步骤1016：在所述基板层开口内填充第一导电介质，形成与无源器件202电连接的第一电连接部3021，从而形成如图5所示的结构。
该第一电连接部3021具体可通过焊点301与无源器件202正面的电性连接件电连接。
需要说明的是，在工艺条件允许的情况下，基板层开口也可在将无源器件焊接于基板之前形成，本申请对此不做限定，可根据具体情况进行设置。
在步骤103中，在裸片正面形成保护层，所述保护层可以在将半导体晶圆切割成多个裸片之前形成于半导体晶圆的正面上，之后再对半导体晶圆进行切割，得到正面形成有保护层的裸片。当然可以理解的是，在工艺允许的情况下，还可以将半导体晶圆切割成裸片后，在每个裸片的正面形成保护层， 可根据具体应用情况进行选择，本申请对此不做限定。
在一些实施例中，请结合图6所示，裸片201的正面具有焊垫2011。焊垫2011用于和外界进行电连接。
进一步，请结合图7，在裸片201的正面形成保护层203。
保护层203采用绝缘材料。保护层的材料可以包括BCB苯并环丁烯、PI聚酰亚胺、PBO聚苯并恶唑(Polybenzoxazole)、环氧树脂、ABF(Ajinomoto buildup film)、聚合物基质介电膜，有机聚合物膜，或者其它具有相似绝缘和结构特性的材料。也可以为有机/无机复合材料，例如添加无机颗粒的树脂聚合物。可选的，保护层203优先选择能够适应化学清洗、研磨等的材料。保护层203可以通过层压(Lamination)、涂覆(Coating)、印刷(Printing)等方式形成在裸片201上。
进一步，请结合图8所示，在保护层203上形成保护层开口2031。该保护层开口2031至少与裸片201正面的焊垫或者从焊垫引出的线路相对应，使得裸片201正面的焊垫或者从焊垫引出的线路从保护层开口2031暴露出来。对于保护层203的材料是激光反应性材料的，可以采用激光图形化的方式形成保护层开口2031。对于保护层203的材料是光敏材料的，则可以采用光刻图形化方式，形成保护层开口2031。保护层开口2031的形状可以是圆的，当然也可以是其他形状如椭圆形、方形、线形等。
需要说明的是，图6至图8仅示意出在一个裸片201正面形成保护层以及在保护层中形成保护层开口，当然，在半导体晶圆正面(对应裸片正面)形成保护层及保护层开口也可参照这一方法形成。相应地，在半导体晶圆的正面形成保护层之后，可以研磨半导体晶圆的背面即对应裸片的背面，以减薄裸片的厚度。当然，在有些实施例中，也可不对裸片的背面进行减薄，本申请对此不做限定，可根据具体应用环境进行设置。进而，利用切割设备，对半导体晶圆沿着切割道进行切割，得到多个正面具有保护层的裸片。切割工艺可以用机械切割也可以用激光切割。进一步再在保护层中形成保护层开口。该保护层开口可与在对半导体晶圆切割之前形成，也可以在切割之后形成。
需要说明的是，步骤101和步骤103并不具有先后顺序之分。步骤101和步骤103可以同时进行。步骤101可以在步骤103之前进行，也可在步骤103之后进行，本申请对此不做限定，可根据具体应用环境进行设置。
在步骤105中，如图9所示，将步骤101中所形成的具有基板层302的 无源器件202以及步骤103中形成的具有保护层203的裸片201按照预定的排布位置间隔贴装于载板200上，裸片201的正面朝向载板200，无源器件202的正面也朝向载板200。其中，贴装无源器件202的排布位置和贴装裸片201的排布位置可以是间隔设置。将无源器件202和裸片201贴装在载板200上之后，保护层开口2031仍呈中空状态。当然，对于在步骤105之前，未在基板层开口中形成第一电连接部3021的，该基板层开口也同样呈中空状态。
可选的，具有基板层302的无源器件202可通过粘接层(未示出)贴装于载板上。粘接层用以粘结具有基板层302的无源器件202，粘接层可采用易剥离的材料，以便在后续工序中，将载板和具有基板层302的无源器件202剥离开来，例如可采用通过加热能够使其失去粘性的热分离材料。
可选的，在另一些实施例中，粘接层可采用两层结构，热分离材料层和附着层，热分离材料层粘贴在载板200上，在加热时会失去黏性，进而能够从载板200上剥离下来，而附着层采用具有粘性的材料层，可以用于粘贴具有基板层302的无源器件202。而具有基板层302的无源器件202从载板200剥离开来后，可以通过化学清洗方式去除其上的附着层。在一实施例中，可通过层压、印刷等方式，在载板200上形成粘接层。
具有保护层203的裸片201可采用同样的方式贴装于载板上。可参考上述相关描述，此处不予以赘述。
需要说明的是，如图9所示，将无源器件202(即具有基板层302的无源器件202)和裸片201(具有保护层203的裸片201)按照预定的排布位置放置在载板200上，为了方便表达，图中仅示出了一个无源器件202和一个裸片201，实际上载板200上有多个裸片201和无源器件202按照预定的位置排布。可选的，无源器件202与裸片201间隔设置于载板200上。
可以理解的是，一次封装过程中，裸片和无源器件均可以是多个，即在载板上同时贴装多个具有基板层的无源器件和具有保护层的裸片，进行封装，并在完成封装后，再切割成多个封装体；一个封装体包括一组无源器件和裸片，其具体可以包括一个或多个无源器件和一个或多个裸片，而这一个或多个无源器件和一个或多个裸片的位置可以根据实际产品的需要进行设置。
在步骤107中，在载板200上形成包封层204，该包封层包封至少部分裸片和至少部分无源器件。比如，该包封层204包覆无源器件202远离载板200的表面、裸片201远离载板200的表面及露出的载板。对于载板上具有粘结层的，包封层包覆无源器件202远离载板的表面、裸片201远离载板200的 表面以及露出的粘结层。当然，如果载板200靠近裸片201和无源器件202一侧的表面依然有露出区域，该露出区域也被包封层包覆。如图10所示，包封层204将载板200、正面设有基板层302的无源器件202以及具有保护层203的裸片201完全包封住，以重新构造一平板结构，以便在将载板200剥离后，能够继续在重新构造的该平板结构上进行再布线和封装。
在一实施例中，包封层204可采用层压环氧树脂膜或ABF(Ajinomoto buildup film)的方式形成，也可以通过对环氧树脂化合物进行注塑成型(Injection molding)、压模成型(Compression molding)或转移成型(Transfer molding)的方式形成。
包封层204远离载板200的上表面2041基本上呈平板状，且与载板200的表面平行或基本平行。包封层204的厚度可以通过对远离载板200的表面进行研磨或抛光来减薄。
在利用包封层204包封时，由于包封层在成型时需要高压成型，在此过程中包封材料容易渗透到载板200与裸片201之间、或载板200与无源器件202之间。本申请基板层302及保护层203的设置，能够防止包封材料渗透到裸片201和无源器件202的表面，而不会直接接触到裸片201的正面以及无源器件202的正面，从而不会对裸片201的正面的电路结构以及无源器件造成破坏。
进一步，如图11所示，在一些实施例中，在形成包封层204之后，可剥离载板200。对于裸片201和无源器件202与载板200之间具有热分解膜的粘结层的，可以通过加热的方式使得粘接层在遇热后降低黏性，进而剥离载板200。通过加热粘接层剥离载板200的方式，能够将在剥离过程中对裸片201和无源器件202的损害降至最低。当然，在其他实施例中，也可直接机械的剥离载板200。
剥离载板200后，可暴露出原本朝向载板200的包封层204的下表面、基板层302的表面、保护层203的表面、第一电连接部3021的表面，保护层开口2031处的焊垫。如此，在剥离载板200后，可以得到包括裸片201、无源器件202、基板层302、保护层203以及包封层204的板状结构。该板状结构中除了保护层开口2031外，原来靠近载板200一侧的各部件的表面在同一平面内。在形成的板状结构上，可以根据实际情况进行布线，实现裸片201和无源器件202与外界之间的电连接，以及裸片2012和无源器件202之间的电连接。
进一步，如图12所示，在剥离载板200之后，在保护层开口2031内填充第二导电介质，形成第二电连接部2032，以及在基板层302远离无源器件202的表面和保护层203远离裸片201的表面形成布线层205。该布线层205形成于基板层302的表面、保护层203的表面以及在同一侧的包封层204的表面。且该布线层205与第一电连接部3021以及第二电连接部2032电连接。具体的，布线层205通过第一电连接部3021与无源器件202的电性连接件电连接、以及通过第二电连接部2032与裸片201正面的焊垫2011电连接。
需要说明的是，在一些实施例中，第二电连接部2032以及布线层205在同一导电层工艺中形成。当然，在其它实施例中，二者也可不在同一导电层工艺中形成。
需要说明的是，对于在步骤105之前，未在基板层开口中形成第一电连接部的，在剥离载板200之后，该方法还包括在基板层开口内填充第一导电介质，形成第一电连接部3021。
可选的，在一些实施例中，第一电连接部3021、第二电连接部2032以及布线层205在同一导电层工艺中形成。
在另一些实施例中，第一电连接部3021、第二电连接部2032以及布线层205也可不在同一导电层工艺中形成。比如，在一些实施例中，在同一导电层工艺中形成第一电连接部3021和第二电连接部2032。之后，再在另一导电层工艺中形成布线层205。当然，第一电连接部、第二电连接部以及布线层也可分别在不同布线层工艺中形成，本申请对此不做限定，可根据具体应用环境进行设置。
需要说明的是，第二电连接部2032也可在步骤105之前形成，相应地，在剥离载板之后，即可直接设置布线层。
进一步，在一些实施例中，在剥离载板200之后，所述方法包括：
在无源器件202和裸片201间隔的外表面处形成加强筋。
这里所说的无源器件202和裸片201间隔的外表面，可以理解为无源器件202和裸片201间隔处的包封层204的表面以及二者间隔处附近基板层302远离无源器件202的表面、保护层203远离裸片201的表面。可选的，该加强筋的材质及结构可以与布线层205相同或类似。该加强筋不与其他电性结构电连接。在一些实施例中，该加强筋可以与布线层205在同一工艺中形成。
进一步，如图13所示，在形成布线层205之后，在布线层205远离裸片201和无源器件202一侧的表面上形成第三电连接部206。
进一步，如图14所示，在布线层205上形成介电层207，以保护布线层205和第三电连接部206。介电层207包覆露出的布线层205、部分第三电连接部206、露出的保护层203及露出的基板层302，且第三电连接部206远离布线层205的表面露出介电层207。形成的介电层207的厚度可以为刚刚露出第三电连接部206的表面；也可以将介电层207覆盖住包封层204、基板层302、保护层203和布线层205上的所有露出表面，之后再减薄至第三电连接部206的表面。
第三电连接部206形状优选为圆形，当然也可以是长方形、正方形等其他形状，且第三电连接部206与布线层205电连接。具体地，可以通过光刻和电镀方式在布线层205形成第三电连接部206。
在另一实施例中，可以在形成布线层205之后，接续在布线层205以及露出的基板层302、保护层203和包封层204上形成介电层207，且介电层207具有介电层开口，之后在所述介电层207的介电层开口内形成与布线层205电连接的第三电连接部206。
在一实施例中，介电层207可通过层压(Lamination)、成型(Molding)或印刷(Printing)的方式形成，优选采用环氧化合物。
可选的，在一些实施例中，在第三电连接部外还可进行重复再布线，比如可以同样地方式在介电层外形成一层或更多个布线层，以实现产品的多层布线。
进一步，在一些实施例中，在在形成介电层207之后，所述方法包括：
在第三电连接部206远离布线层205的表面形成外连接键208。
外连接键208的材料可以是锡。相应地，外连接键208可以通过镀锡的方式形成。当然，在其它一些实施例中，外连接键还可以是其它材料，比如，铜、镍基合金或其他能够实现电连接的金属材料，外连接键还可以通过其它方式形成，本申请对此不做限定，可根据具体情况进行设置。
进一步，在形成布线外连接键208之后，对于设置有多组裸片和无源器件的，通过激光或机械切割方式将整个封装结构切割成多个封装体，即半导体封装结构，比如，如图3所示的半导体封装结构。
图15是根据本申请一示例性实施例提供的半导体封装方法所得到的半导体封装结构1000的结构示意图。请参照如图15并在必要时结合图1-14所示，该半导体封装结构1000包括：
无源器件202，无源器件202的正面具有电性连接件且无源器件202的正 面设有基板层302；基板层302中设有贯穿基板层302相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应；所述基板层开口中形成有第一电连接部3021；
裸片201，裸片201的正面设有焊垫且裸片201的正面形成有保护层203；保护层203上形成保护层开口2031，所述保护层开口2031与裸片201正面的焊垫2011相对应；保护层开口2031中形成有第二电连接部2032；
包封层204，至少包封裸片201的侧面及无源器件202的侧面；
布线层205，设于基板层302远离无源器件202的表面以及保护层203远离裸片201的表面形成，并通过第一电连接部3021与无源器件202电连接以及通过第二电连接部2032与裸片201电连接。
进一步，该半导体封装结构1000还可包括介电层207。该介电层207形成于布线层205以及露出的基板层302、保护层203、包封层204上，且具有介电层开口。该介电层开口内设有与布线层205电连接的第三电连接部206。
本实施例中半导体封装结构的各结构件均可参照上述半导体封装方法中所对应结构件的相关描述，此处不予以赘述。
在本申请中，所述装置实施例与方法实施例在不冲突的情况下，可以互为补充。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (12)

  1. 一种半导体封装方法，其特征在于，包括：
    提供无源器件并在所述无源器件的正面设置基板层；所述无源器件的正面具有电性连接件，所述基板层中设有贯穿所述基板层相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应；
    提供裸片并在所述裸片的正面形成保护层，并在所述保护层上形成保护层开口；其中，所述裸片的正面设有焊垫，所述保护层开口与所述裸片的正面的焊垫相对应；
    将所述无源器件和所述裸片间隔贴装于载板上；其中，所述裸片的正面朝向所述载板，所述无源器件的正面朝向所述载板；
    形成包封层，所述包封层至少包封所述裸片的侧面和所述无源器件的侧面。
  2. 如权利要求1所述的半导体封装方法，其特征在于，所述在无源器件的正面设置基板层包括：
    提供基板；
    在所述基板的表面形成多个按照预设位置排布的无源器件的焊点；
    将多个无源器件分别对应焊接于不同焊点，形成无源器件组件；
    对所述无源器件组件的基板进行切分，形成正面设置有基板层的无源器件。
  3. 如权利要求2所述的半导体封装方法，其特征在于，在对所述无源器件组件的基板进行切分，形成正面设置有基板层的无源器件后，所述方法还包括：
    在所述基板层开设所述基板层开口。
  4. 如权利要求1所述的半导体封装方法，其特征在于，在形成所述包封层之后，所述方法还包括：
    剥离所述载板；
    在所述基板层开口内填充第一导电介质，形成第一电连接部，在所述保护层开口内填充导电介质，形成第二电连接部，以及在所述基板层远离所述无源器件的表面和所述保护层远离所述裸片的表面形成布线层；所述布线层通过所述第一电连接部与所述无源器件的电性连接件电连接、以及通过所述第二电连接部与所述裸片的正面的焊垫电连接。
  5. 如权利要求1所述的半导体封装方法，其特征在于，在形成所述包封层之后，所述方法还包括：
    剥离所述载板；
    在所述无源器件和所述裸片间隔的外表面处形成加强筋。
  6. 如权利要求1所述的半导体封装方法，其特征在于，将所述无源器件和所述裸片间隔贴装于载板上之前，所述方法还包括：
    在所述基板层开口内填充第一导电介质，形成与所述无源器件的电性连接件电连接的第一电连接部，以及在所述保护层开口内填充导电介质，形成与所述裸片的正面的焊垫电连接的第二电连接部。
  7. 如权利要求6所述的半导体封装方法，其特征在于，在形成所述包封层之后，所述半导体封装方法还包括：
    剥离所述载板；
    在所述基板层远离所述无源器件的表面以及所述保护层远离所述裸片的表面形成布线层，所述布线层通过所述第一电连接部与所述无源器件的电性连接件电连接、以及通过所述第二电连接部与所述裸片的正面的焊垫电连接。
  8. 如权利要求4或7所述的半导体封装方法，其特征在于，在形成布线层之后，所述方法还包括：
    在所述布线层远离所述裸片和所述无源器件一侧的表面上形成第三电连接部。
  9. 如权利要求8所述的半导体封装方法，其特征在于，在形成所述第三电连接部之后，所述方法还包括：
    在所述布线层上形成介电层，所述介电层包覆露出的所述布线层、部分所述第三电连接部、露出的保护层及基板层，且所述第三电连接部远离所述布线层的表面露出所述介电层。
  10. 如权利要求9所述的半导体封装方法，其特征在于，在形成所述介电层之后，所述方法还包括：
    在所述第三电连接部远离所述布线层的表面形成外连接键。
  11. 一种半导体封装结构，其特征在于，包括：
    无源器件，所述无源器件的正面具有电性连接件且所述无源器件的正面设有基板层；所述基板层中设有贯穿所述基板层相对两表面的基板层开口，所述基板层开口与所述电性连接件相对应；
    裸片，所述裸片的正面设有焊垫且所述裸片的正面形成有保护层；所述 保护层上形成有保护层开口，所述保护层开口与所述裸片的正面的焊垫相对应；以及
    包封层，至少包封所述裸片的侧面及所述无源器件的侧面。
  12. 如权利要求11所述的半导体封装结构，其特征在于，所述基板层开口中形成有第一电连接部；所述保护层开口中形成有第二电连接部；
    其中，所述半导体封装结构还包括布线层，设于所述基板层远离所述无源器件的表面以及所述保护层远离所述裸片的表面，并通过所述第一电连接部与所述无源器件电连接以及通过所述第二电连接部与所述裸片电连接。
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