CN102779809A - 晶片封装体及其形成方法 - Google Patents

晶片封装体及其形成方法 Download PDF

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Publication number
CN102779809A
CN102779809A CN2012101436729A CN201210143672A CN102779809A CN 102779809 A CN102779809 A CN 102779809A CN 2012101436729 A CN2012101436729 A CN 2012101436729A CN 201210143672 A CN201210143672 A CN 201210143672A CN 102779809 A CN102779809 A CN 102779809A
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substrate
conductive layer
opening
insulating barrier
encapsulation body
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CN2012101436729A
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CN102779809B (zh
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刘建宏
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其形成方法，该晶片封装体包括：一第一基底；一第二基底，设置于该第一基底之上，其中该第二基底具有贯穿该第二基底之至少一开口，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区；一第一绝缘层，设置于该第一基底之一侧边之上，且填充于该第二基底之该至少一开口之中；一承载基底，设置于该第二基底之上；一第二绝缘层，设置于该承载基底之一表面及一侧壁之上；以及一导电层，设置于该承载基底上之该第二绝缘层之上，且电性接触其中一所述导电区。本发明可有效缩小多晶片封装结构的体积，且节省制作成本。

Description

晶片封装体及其形成方法
技术领域
本发明有关于晶片封装体，且特别是有关于微机电系统晶片封装体(MEMS chip packages)。
背景技术
随着电子产品朝向轻、薄、短、小发展的趋势，半导体晶片的封装结构也朝向多晶片封装(multi-chip package,MCP)结构发展，以达到多功能和高性能要求。多晶片封装结构是将不同类型的半导体晶片，例如逻辑晶片、模拟晶片、控制晶片或存储器晶片，整合在单一封装基底之上。
不同晶片之间可通过焊线而彼此电性连接。然而，随着需整合的晶片数量上升，将多晶片以焊线相连接会造成封装体体积无法有效缩小，且亦会占去过多面积而造成制作成本增加，不利于可携式电子产品的应用。
发明内容
本发明提供一种晶片封装体，包括：一第一基底；一第二基底，设置于该第一基底之上，其中该第二基底具有贯穿该第二基底之至少一开口，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区；一第一绝缘层，设置于该第一基底之一侧边之上，且填充于该第二基底之该至少一开口之中；一承载基底，设置于该第二基底之上；一第二绝缘层，设置于该承载基底之一表面及一侧壁之上；以及一导电层，设置于该承载基底上之该第二绝缘层之上，且电性接触所述导电区中的一导电区。
本发明所述的晶片封装体，该导电层自该承载基底的该表面上的该第二绝缘层沿着该承载基底的该侧壁朝该第二基底延伸。
本发明所述的晶片封装体，还包括：一防焊层，设置于该导电层之上，其中该防焊层具有露出该导电层的一开口；以及一导电凸块，设置于该防焊层的该开口之中，且电性接触该导电层。
本发明所述的晶片封装体，该防焊层包覆该导电层的邻近所述导电区中的一导电区的一部分的一侧边。
本发明所述的晶片封装体，该导电层延伸进入该第二基底之中。
本发明所述的晶片封装体，该承载基底的该侧壁倾斜于该承载基底的该表面。
本发明所述的晶片封装体，还包括一第二导电层，设置于该承载基底及该第二绝缘层之上，且电性接触所述导电区中的一导电区，其中该第二导电层不电性连接该导电层。
本发明所述的晶片封装体，该第一基底的该侧边倾斜于该第一基底的面向该第二基底的一表面。
本发明所述的晶片封装体，该第一绝缘层填充于该第一基底与该第二基底之间的一间隙之中，且覆盖于该第一基底的一底表面之上。
本发明所述的晶片封装体，还包括一支撑基板，设置于该第一基底之下，其中该第一绝缘层夹于该第一基底的该底表面与该支撑基板之间。
本发明提供一种晶片封装体的形成方法，包括：提供一第一基底；将一第二基底设置于该第一基底之上，其中该第二基底具有贯穿该第二基底之至少一开口，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区；将一承载基底设置于该第二基底之上；自该第一基底之一底表面部分移除该第一基底以形成至少一第一沟槽开口，该至少一第一沟槽开口露出该第二基底之该至少一开口及该些导电区；于该至少一第一沟槽开口之一侧壁上形成一第一绝缘层，其中该第一绝缘层填充于该第二基底之该至少一开口之中；自该承载基底之一上表面部分移除该承载基底以形成朝该第二基底延伸之至少一沟槽；于该承载基底之一表面及该至少一沟槽之一侧壁上形成一第二绝缘层；以及于该第二绝缘层之上形成一导电层，其中该导电层电性接触所述导电区中的一导电区。
本发明所述的晶片封装体的形成方法，还包括在形成至少一第一沟槽开口之前，薄化该第一基底。
本发明所述的晶片封装体的形成方法，还包括在形成该至少一沟槽之前，薄化该承载基底。
本发明所述的晶片封装体的形成方法，还包括：于该导电层之上形成一防焊层，该防焊层具有露出该导电层的一开口；以及于该防焊层的该开口中形成一导电凸块，该导电凸块电性接触该导电层。
本发明所述的晶片封装体的形成方法，还包括切割移除部分的该第二绝缘层以于该第二绝缘层中形成一第二沟槽开口，该第二沟槽开口露出该第二基底的该至少一开口及所述导电区。
本发明所述的晶片封装体的形成方法，该第二沟槽开口延伸进入该第二基底之中。
本发明所述的晶片封装体的形成方法，还包括于该第二绝缘层之上形成一第二导电层，其中该第二导电层电性接触所述导电区中的一导电区，且该第二导电层不电性连接该导电层。
本发明所述的晶片封装体的形成方法，该导电层及该第二导电层的形成步骤包括：于该第二绝缘层上形成一导电材料层；以及将该导电材料层图案化以形成该导电层及该第二导电层。
本发明所述的晶片封装体的形成方法，还包括于该第一基底之下设置一支撑基板，其中该第一绝缘层夹于该第一基底与该支撑基板之间。
本发明所述的晶片封装体的形成方法，还包括于该至少一沟槽的一底部进行一切割制程以形成多个彼此分离的晶片封装体。
本发明可有效缩小多晶片封装结构的体积，且节省制作成本。
附图说明
图1A至图1L显示根据本发明一实施例的晶片封装体的制程剖面图。
图2显示相应于图1F的结构的立体示意图。
附图中符号的简单说明如下：
100：基底；102：接垫；104：保护层；106、106a：开口；108：绝缘层；110：支撑基板；200：基底；201a、201b、201c：开口；202：接垫；203a、203b、203c、203d：导电区；204：承载基底；206：绝缘层；208：沟槽；210：绝缘层；212：开口；214a：晶种层；214b：导电层；216：防焊层；218：导电凸块；SC：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。本领域技术人员自本发明的权利要求书所能推及的所有实施方式皆属本发明所欲揭露的内容。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装各种晶片。例如，其可用于封装各种包含有源元件或无源元件(active or passiveelements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optical electronic devices)、微机电系统(Micro ElectroMechanical System;MEMS)、微流体系统(micro fluidicsystems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(waferscale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率晶片(power IC)等半导体晶片进行封装。
上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体。然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
图1A至图1L显示根据本发明一实施例的晶片封装体的制程剖面图。在下述说明中，以采用晶圆级封装制程的实施例为例。然应注意的是，本发明实施例亦可采用有别于晶圆级封装制程的其他适合制程。
如图1A所示，提供基底100。基底100可为半导体基底(例如，硅基底)或半导体晶圆(例如，硅晶圆)。采用半导体晶圆可利于晶圆级封装制程的进行、可确保封装品质、并节省制程成本及时间。在一实施例中，基底100中形成有多个CMO S元件(未显示)。基底100的表面上形成有多个接垫102。这些接垫102分别电性连接至相应的CMOS元件。基底100的表面上还形成有保护层104，其可覆盖基底100的表面，并具有露出接垫102的开口。保护层104的材质例如是氧化物、氮化物、氮氧化物、高分子材料或前述的组合。
如图1A所示，提供基底200。基底200可为半导体基底(例如，硅基底)或半导体晶圆(例如，硅晶圆)。在一实施例中，基底100中形成有多个CMOS元件(未显示)。在一实施例中，基底200中形成有多个MEMS元件。基底200的上表面上可形成有绝缘层206及承载基底204。绝缘层206的材质例如为氧化物、氮化物、氮氧化物、高分子材料或前述的组合。在一实施例中，绝缘层206的材质为氧化硅。承载基底204例如可为半导体基底，例如是硅晶圆。基底200可通过形成于下表面上的接垫202而接合于基底100之上。如图1A所示，接垫202与接垫102彼此接合。在一实施例中，接垫202及接垫102皆为导电材料。因此，接垫202及接垫102还可形成基底100与基底200之间的导电通路。例如，基底100中的CMOS元件与基底200中的MEMS元件可通过接垫202与接垫102而彼此传递电性信号。在一实施例中，可分别对基底100及/或承载基底204进行薄化制程。如图1A所示，在一实施例中，可以承载基底204为支撑，对基底100的下表面进行研磨制程以将基底100薄化至适合的厚度。
在一实施例中，多个预定切割道SC将基底100与基底200的堆叠晶圆划分成多个区域。在后续封装与切割制程之后，每一区域将成为一晶片封装体。在基底200的每一区域之中，可形成有多条贯穿基底200的缝隙(或开口)，其于基底200中划分出多个彼此不电性连接的导电区。每一导电区可电性连接至相应的接垫202。在一实施例中，这些导电区为基底200中的高掺杂区域。
如图1B所示，可部分移除基底100以形成至少一开口106。开口106可为大抵顺着预定切割道SC延伸的沟槽。开口106可露出保护层104。在一实施例中，可通过光刻及蚀刻制程(例如，干式蚀刻)形成开口106。
接着，如图1C所示，例如以蚀刻制程移除部分的保护层104以形成露出基底200的开口106a。开口106a可露出贯穿基底200的开口以及多个彼此电性绝缘的导电区。
如图1D所示，可于基底100的下表面上形成绝缘层108。绝缘层108的材质可为高分子材料，例如是环氧树脂。绝缘层108亦可为氧化物、氮化物、氮氧化物、其他适合高分子材料或前述的组合。绝缘层108的形成方式例如是涂布、气相沉积、喷涂或印刷等。绝缘层108可填入开口106a之中而填充于基底200与基底100之间的间隙。在一实施例中，绝缘层108可仅填充并封住基底200的开口而不填满基底200与基底100之间的间隙。在一实施例中，在形成绝缘层108之后，可选择性于绝缘层108之上设置支撑基板110。支撑基板110可例如为玻璃基板或半导体基板，并可具有相似于基底100的尺寸与形状。
接着，如图1E所示，可选择性对承载基底204进行薄化制程。如图1F所示，可接着部分移除承载基底204以形成至少一沟槽208。沟槽208可大抵沿着其中一预定切割道SC延伸。沟槽208可露出绝缘层206。在一实施例中，可通过光刻及蚀刻制程(例如，干式蚀刻)形成沟槽208。在一实施例中，沟槽208可大抵对齐于开口106a。
图2显示相应于图1F的结构的立体示意图。如图2所示，基底200于沟槽208之下可具有至少一开口，其于基底200中划分出多个彼此不电性连接的导电区。在一实施例中，多个开口201a、201b及201c将沟槽208下的基底200划分成多个导电区203a、203b、203c及203d。这些导电区因开口的隔离而彼此电性绝缘。在一实施例中，基底200的下表面上可形成有多个接垫202，这些接垫202可延着沟槽208(或沿着预定切割道SC)而设置。每一导电区可电性连接至其中一相应的接垫而与基底100中的相应的CMO S元件电性连接。例如，在一实施例中，导电区203a可通过图2所示的接垫202及接垫102而与基底100中的相应的CMOS元件电性连接。
如图1G所示，于承载基底204之上形成绝缘层210。绝缘层210的材质可为高分子材料，例如是环氧树脂。绝缘层210亦可为氧化物、氮化物、氮氧化物、其他适合高分子材料或前述的组合。绝缘层210的形成方式例如是涂布、气相沉积、喷涂或印刷等。绝缘层210可填入沟槽208之中。
接着，如图1H所示，移除部分的绝缘层210以自绝缘层210的表面形成朝基底200延伸的开口212。开口212的形成方式可为切割或蚀刻。开口212露出基底200。在一实施例中，开口212可穿过绝缘层206，并延伸进入基底200之中。开口212可为一沟槽，并顺着沟槽208(或预定切割道SC)而延伸。开口212可露出基底200中的开口(例如，开口201a、201b及201c)及导电区(例如，导电区203a、203b、203c及203d)，其中所露出的开口中填充有先前所形成的绝缘层108。在采用切割制程形成开口212的实施例中，由于先前形成的绝缘层108已填充并封住基底200的开口(例如，开口201a、201b及201c)，因此切割过程所造成的颗粒将不会经由基底200的开口而落至基底200与基底100之间的间隙而影响晶片封装体的运作。
接着，可于承载基底204之上形成图案化导电层。导电层的材质可包括铝、铜、金、镍或前述的组合。导电层的形成方式可包括物理气相沉积、化学气相沉积、涂布、电镀、无电镀或前述的组合。以下，以采用电镀制程为例说明一实施例的图案化导电层的形成过程。
如图1I所示，于承载基底204之上形成晶种层。晶种层的材质例如为铝或铜，其形成方式例如为溅镀。晶种层可沿着开口212的侧壁而延伸于开口212的底部上，并与所露出的导电区(例如，导电区203a、203b、203c及203d)电性接触。接着，例如通过光刻及蚀刻制程而将晶种层图案化以形成图案化晶种层214a。图案化晶种层214a可仅电性接触其中一导电区，例如是导电区203a。晶种层经图案化之后，还可形成出电性连接其他导电区(例如，导电区203b、203c或203d)的图案化晶种层。由于先前所形成之绝缘层108已填充并封住基底200于沟槽208底部处的开口(例如，开口201a、201b及201c)，因此晶种层的图案化过程中所需采用的蚀刻液及/或蚀刻气体将不会经由基底200的开口而到达接垫202与接垫102，可确保基底100与基底200之间的接合与电性连接。
如图1J所示，接着可通过电镀制程而于晶种层214a的表面上电镀导电材料以形成导电层214b。在一实施例中，导电层214b可包括镍、金、铜或前述的组合。
接着，如图1K所示，于导电层214b上形成防焊层216。防焊层216具有露出导电层214b的开口。如图1K所示，可于防焊层216的开口所露出的导电层214b之上形成导电凸块218。
如图1L所示，可沿着预定切割道SC切割显示于图1K的结构而形成多个彼此分离的晶片封装体。在一实施例中，晶片封装体包括：一第一基底100；一第二基底200，设置于该第一基底之上，其中该第二基底具有贯穿该第二基底的至少一开口(例如，开口201a、201b及201c)，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区(例如，导电区203b、203c及203d)；一第一绝缘层108，设置于该第一基底的一侧边之上，且填充于该第二基底的该至少一开口(例如，开口201a、201b及201c)之中；一承载基底204，设置于该第二基底之上；一第二绝缘层210，设置于该承载基底之一表面及一侧壁之上；以及一导电层(214a及214b)，设置于该承载基底上的该第二绝缘层之上，且电性接触其中一导电区。
本发明实施例还可有许多变化。例如，在形成图案化晶种层214a时，可使开口212底部上的图案化晶种层214a不触及预定切割道S C而使后续电镀的导电层214b亦不触及预定切割道SC。换言之，可通过图案化制程的调整使所形成的图案化导电层与预定切割道S C之间隔有间距而不直接接触。在此情形下，所形成的防焊层216将于开口212的底部处包覆导电层的侧边。换言之，防焊层216包覆导电层的邻近所接触导电区的部分的一侧边。如此，在后续切割制程中，切割刀片将不会切割到图案化导电层，可避免导电层因切割制程而受损或脱落。此外，由于防焊层216包覆导电层的侧边，可避免导电层氧化或受损。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一第一基底；
一第二基底，设置于该第一基底之上，其中该第二基底具有贯穿该第二基底的至少一开口，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区；
一第一绝缘层，设置于该第一基底的一侧边之上，且填充于该第二基底的该至少一开口之中；
一承载基底，设置于该第二基底之上；
一第二绝缘层，设置于该承载基底的一表面及一侧壁之上；以及
一导电层，设置于该承载基底上的该第二绝缘层之上，且电性接触所述导电区中的一导电区。
2.根据权利要求1所述的晶片封装体，其特征在于，该导电层自该承载基底的该表面上的该第二绝缘层沿着该承载基底的该侧壁朝该第二基底延伸。
3.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一防焊层，设置于该导电层之上，其中该防焊层具有露出该导电层的一开口；以及
一导电凸块，设置于该防焊层的该开口之中，且电性接触该导电层。
4.根据权利要求3所述的晶片封装体，其特征在于，该防焊层包覆该导电层的邻近所述导电区中的一导电区的一部分的一侧边。
5.根据权利要求1所述的晶片封装体，其特征在于，该导电层延伸进入该第二基底之中。
6.根据权利要求1所述的晶片封装体，其特征在于，该承载基底的该侧壁倾斜于该承载基底的该表面。
7.根据权利要求1所述的晶片封装体，其特征在于，还包括一第二导电层，设置于该承载基底及该第二绝缘层之上，且电性接触所述导电区中的一导电区，其中该第二导电层不电性连接该导电层。
8.根据权利要求1所述的晶片封装体，其特征在于，该第一基底的该侧边倾斜于该第一基底的面向该第二基底的一表面。
9.根据权利要求1所述的晶片封装体，其特征在于，该第一绝缘层填充于该第一基底与该第二基底之间的一间隙之中，且覆盖于该第一基底的一底表面之上。
10.根据权利要求9所述的晶片封装体，其特征在于，还包括一支撑基板，设置于该第一基底之下，其中该第一绝缘层夹于该第一基底的该底表面与该支撑基板之间。
11.一种晶片封装体的形成方法，其特征在于，包括：
提供一第一基底；
将一第二基底设置于该第一基底之上，其中该第二基底具有贯穿该第二基底的至少一开口，该至少一开口于该第二基底之中划分出彼此电性绝缘的多个导电区；
将一承载基底设置于该第二基底之上；
自该第一基底的一底表面部分移除该第一基底以形成至少一第一沟槽开口，该至少一第一沟槽开口露出该第二基底的该至少一开口及所述导电区；
于该至少一第一沟槽开口的一侧壁上形成一第一绝缘层，其中该第一绝缘层填充于该第二基底的该至少一开口之中；
自该承载基底的一上表面部分移除该承载基底以形成朝该第二基底延伸的至少一沟槽；
于该承载基底的一表面及该至少一沟槽的一侧壁上形成一第二绝缘层；以及
于该第二绝缘层之上形成一导电层，其中该导电层电性接触所述导电区中的一导电区。
12.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括在形成至少一第一沟槽开口之前，薄化该第一基底。
13.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括在形成该至少一沟槽之前，薄化该承载基底。
14.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括：
于该导电层之上形成一防焊层，该防焊层具有露出该导电层的一开口；以及
于该防焊层的该开口中形成一导电凸块，该导电凸块电性接触该导电层。
15.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括切割移除部分的该第二绝缘层以于该第二绝缘层中形成一第二沟槽开口，该第二沟槽开口露出该第二基底的该至少一开口及所述导电区。
16.根据权利要求15所述的晶片封装体的形成方法，其特征在于，该第二沟槽开口延伸进入该第二基底之中。
17.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于该第二绝缘层之上形成一第二导电层，其中该第二导电层电性接触所述导电区中的一导电区，且该第二导电层不电性连接该导电层。
18.根据权利要求17所述的晶片封装体的形成方法，其特征在于，该导电层及该第二导电层的形成步骤包括：
于该第二绝缘层上形成一导电材料层；以及
将该导电材料层图案化以形成该导电层及该第二导电层。
19.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于该第一基底之下设置一支撑基板，其中该第一绝缘层夹于该第一基底与该支撑基板之间。
20.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于该至少一沟槽的一底部进行一切割制程以形成多个彼此分离的晶片封装体。
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