CN106960799A - 制造三维扇出结构的方法 - Google Patents

制造三维扇出结构的方法 Download PDF

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Publication number
CN106960799A
CN106960799A CN201610163609.XA CN201610163609A CN106960799A CN 106960799 A CN106960799 A CN 106960799A CN 201610163609 A CN201610163609 A CN 201610163609A CN 106960799 A CN106960799 A CN 106960799A
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substrate carrier
label
semiconductor
hole
semiconductor label
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CN201610163609.XA
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CN106960799B (zh
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高伟
龚志伟
叶德洪
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN201610163609.XA priority Critical patent/CN106960799B/zh
Priority to US15/355,069 priority patent/US10283477B2/en
Publication of CN106960799A publication Critical patent/CN106960799A/zh
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Abstract

制造用于集成电路装置的3D扇出结构的方法，包括：提供衬底载体，其具有相对的第一和第二表面，以及在第一和第二表面之间延伸的孔。将第一半导体片芯接合至衬底载体的第一表面，使得第一片芯覆盖衬底载体的孔。将封装剂和第二片芯沉积放置在衬底载体的孔内，使得第二片芯的有效表面暴露并且与衬底载体的第二表面共面。随后将一个或者多个再分配层施加至衬底载体的第二表面上，来形成3D扇出结构。

Description

制造三维扇出结构的方法
技术领域
本发明一般涉及制造三维扇出结构的方法，并且更具体地，涉及制造用于集成电路装置的三维扇出结构的方法。
背景技术
扇出(fan-out)晶片级封装(WLP)通过在单个集成电路封装内的半导体片芯(die)的纵向集成使得能够实现三维(3D)结构。因此，扇出WLP已经变成增加能够集成在单个集成电路装置内的功能的重要技术。
用于在集成电路装置内制造晶片级扇出的常规技术通常包括诸如面板化(panelization)工艺、封装通孔(through package via)工艺和双面构建(double sidedbuild-up)工艺之类的工艺。对于在集成电路装置内晶片级扇出的制造，这些工艺为增加了大量的成本，带来了可制造性和可靠性问题。
例如，采用常规的FOWLP(扇出晶片级封装)制造工序，片芯和部件常常“正面朝下”放置在临时的载带/载体上(即，“有效”侧与载带/载体接触)，来确保片芯和部件共面。接下来是包封，以将片芯和部件组装成“面板”以供构建。为了在片芯和部件的有效侧上执行构建，面板被翻转并且载带/载体被移除。载带/载体移除工艺常常涉及专门的热、光学和机械处理工艺，这使得产品流程复杂化和成本增加。同时，因为片芯和部件在包封之前进行放置，包封剂的收缩会引起“片芯偏移”，这会导致大的成品率损失。当FOWLP用于大面板尺寸和精细节距(pitch)的产品时，片芯偏移尤其成为问题。
除了工艺流程复杂和片芯偏移的挑战之外，带/载体工艺还会导致面板上不期望的形貌(topography)。这是因为片芯/部件在放置期间穿透进入了带/载体粘附剂中，如图1所示。结果，在后续被包封和带/载体移除时，片芯/部件穿透入粘附剂的区域将从包封剂的表面凸出，造成片芯对模具或者部件对模具的不共面，如图2所示。该不平坦会影响构建层的连续性，并且在再分配层的构建之后产生片芯/部件级的应力，潜在地导致片芯/部件和再分配层的损坏，以及导致粘附剂空隙。
因此，用于在集成电路装置内制造晶片级扇出的、不会导致这种冗长的，高成品率损失和复杂的工艺的技术，将有助于降低成本，并提高这种集成电路装置的可制造性和可靠性。
附图说明
参考以下对优选实施例的描述以及附图，将最佳地理解本发明及其目的和有益效果，在附图中：
图1是在放置期间片芯/部件穿透进入带/载体粘附剂的问题的简化截面视图；
图2是作为其穿透进入带/载体粘附剂的结果，在包封之后片芯/部件不共面问题的简化截面视图。
图3至9示出了一系列简化截面构建视图，该些视图示出了依照本发明实施例的制造用于集成电路装置的3D扇出结构的方法的示例；
图10是具有多个片芯和部件的3D扇出结构的示例的简化截面视图；以及
图11至18示出了一系列简化截面构建视图，该些视图示出了制造用于集成电路装置的3D扇出结构的方法的替代性示例。
具体实施方式
下文中的结合附图的详细描述意在描述本发明的当前优选的实施例，并不意图代表本发明可践行的仅有的形式。应当理解，相同或者等同功能可以由不同的实施例实现，意图将这些不同的实施例包括在本发明的精神和范围内。在附图中，通篇使用相同的附图标记指示相同的元件。此外，术语“包括”、“包含”，或者其任何其它的变形，均意在涵盖非排除性的包含，使得包括一系列元件或者步骤的模块、电路、装置部件、结构和方法步骤不是仅包括这些元件，而是可以包括未明确列出的或这些模块、电路、装置部件或步骤固有的其他的元件或者步骤。以“包括”引述的元件或者步骤，在没有更多的限制的情况下，并不排除包括所述元件或步骤的其他相同元件或步骤的存在。
在一个实施例中，本发明提供了制造用于集成电路装置的3D扇出结构的方法。该方法包括：提供衬底载体，其包括相对的第一和第二表面，以及在第一和第二表面之间贯穿延伸的孔；将第一半导体片芯接合至衬底载体的第一表面，使得第一半导体片芯覆盖衬底载体的孔；在衬底载体的孔内沉积包封剂和第二半导体片芯，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及将至少一个再分配层施加至衬底载体的第二表面上，以形成3D扇出结构。
在另一个实施例中，本发明提供用于集成电路装置的三维扇出结构。该3D扇出结构包括：衬底载体，其包括相对的第一和第二表面，以及在第一和第二表面之间贯穿延伸的孔；第一半导体片芯，接合至衬底载体的第一表面，使得第一半导体片芯覆盖衬底载体的孔；包封剂和第二半导体片芯，位于衬底载体的孔内，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及至少一个再分配层，施加至衬底载体的第二表面上。
在另一个实施例中，本发明提供了包括该用于集成电路装置的3D扇出结构的集成电路装置。
现在参考图3至9，示出了一系列简化的截面构建视图，其示出了制造用于集成电路装置的三维扇出结构的方法的示例。该方法开始于图3，其中提供了衬底载体300。衬底载体300可由任何合适的绝缘材料制成，例如CCL衬底(覆铜叠层衬底)。衬底载体300具有相对的第一和第二表面310、320，和在其间贯穿延伸的孔330。在一些实例中，衬底载体300可以具有导电轨线或者焊盘340，其形成在衬底载体300的表面310、320上或表面310、320中。衬底载体300可以还包括贯穿其(例如在导电接触轨迹/焊盘340之间)延伸的一个或者多个导电通孔(via)350。
如图4所示，将第一半导体片芯400接合至衬底载体300的第一表面310，使得第一半导体片芯400覆盖衬底载体300的孔330。可以适用任何合适的接合技术来将第一半导体片芯400接合至衬底载体300的第一表面310。例如，并且如图4至8所示，可以使用焊球表面安装技术将第一半导体片芯400倒装接合至衬底载体300的第一表面310，其中焊料膏的“球”410用于将位于第一半导体片芯400的有效表面405的外围区域附近的接触焊盘机械和电地接合至位于衬底载体300的第一表面310上或第一表面310中的与孔330的边缘相邻的导电焊盘340。
将第一半导体片芯400接合至衬底载体300的第一表面310后，将衬底载体300“翻转”或者以其他方式重新定向(如果需要的话)，使得第一半导体片芯400位于衬底载体300之下，如图5所示。
在图3至9中示出的示例方法中，将诸如环氧树脂的包封剂600分配至衬底载体300内的孔330中，如图6所示。随后将第二半导体片芯700放置至衬底载体300的孔330内的包封剂中，使得第二半导体片芯700的有效表面705暴露并且与衬底载体300的第二表面320共面，如图7所示。施加至第二半导体片芯700的放置力有助于改善第一半导体片芯400与衬底载体300的第一表面310之间的包封剂600的填充不足720。可以使用“超尺寸”拾取和放置管嘴710来确保第二半导体片芯700的有效表面705与衬底载体300的第二表面320共面。
重要的是，通过最初将第一半导体片芯400接合至衬底载体300的第一表面310使得其覆盖了孔330，当衬底载体随后翻面时，形成了井形结构，其中的包封剂600和第二半导体片芯700能够沉积放置其中而不需要临时带/载体，并因此避免了用于移除带/载体的另外的工序。此外，相较于使用临时的带/载体工艺，能够更容易地实现第二半导体片芯700的有效表面705与衬底载体300的第二表面320的共面。
一旦包封剂600硬化，则将一个或者多个再分配层(诸如图8中的810所一般地示出的)施加(构建)至衬底载体300的第二表面320上，来形成三维扇出结构800。然后，可以执行3D扇出结构800的球附接和单颗化(singulation)，来形成单独的集成电路装置900，如图9所示。
有益的是，如能够从示出的实例中所看出的，半导体片芯400、700中的任何一个均不需要与衬底载体300是等厚度的或者相对于彼此等厚度(这些事很多常规制造技术的限制)，使得在半导体片芯形状和尺寸方面具有更大的灵活性和变化。特别是，制造其中半导体片芯相对于衬底载体300和彼此具有不同的厚度的三维扇出结构的能力，在制造由多个片芯和部件构成的模块(诸如，图10中所示的集成电路模块1000)时是尤为有益的。
因此，提供了用于制造3D扇出结构的简化的低成本的工艺流程，其使得能够实现得到的集成电路装置的良好的可制造性和可靠性。
现在参考图11至18，示出了一系列简化的截面构建视图，其示出了制造用于集成电路装置的3D扇出结构的方法的替代性实例。为理解的清楚和简单起见，适用相同的附图标记来标示与图3至9所示实例中相同的特征。该方法开始于图11，其中提供了衬底载体300。衬底载体300具有相对的第一和第二表面310、320，和贯穿其延伸的孔330。在一些实例中，衬底载体300可以具有导电轨迹或者焊盘340，其形成在衬底载体300的表面310、320上或表面310、320中。衬底载体300可以进一步包括贯穿其(例如，在导电接触轨迹/焊盘340之间)延伸的一个或者多个导电通孔(via)350。
如图12所示，将第一半导体片芯400接合至衬底载体300的第一表面310，使得第一半导体片芯400覆盖衬底载体300的孔330。
将第一半导体片芯400接合至衬底载体300的第一表面310后，将衬底载体300“翻转”或者重新定向(如果需要的话)，使得第一半导体片芯400位于衬底载体300之下，如图13所示。
在图11至18中示出的示例方法中，将粘附剂层1400(诸如，片芯附接膜(DAF)带)施加至暴露在孔330内的第一半导体片芯400的接合表面区域，其在示出的实例中由第一半导体片芯400的有效表面405构成，如图14所示。随后将第二半导体片芯700放置至衬底载体300的孔330内的粘附剂层1400上，使得第二半导体片芯700的有效表面705与衬底载体300的第二表面320共面，如图15所示。替代地，粘附剂层1400可以首先施加至第二半导体片芯700的表面，并且半导体片芯700和粘附剂层1400可以放置在孔330内，使得粘附剂层1400接触并且粘接至第一半导体片芯400的接合表面。
随后将包封剂1600分配至孔330中第二半导体片芯700的周围，来将第二半导体片芯700包封在孔330内，使得第二半导体片芯700的有效表面705保持暴露并且与衬底载体300的第二表面320共面，并且第一半导体片芯400与衬底载体300的第一表面310之间的填充不足720得以改善。
一旦包封剂600硬化，随后将一个或者多个再分配层(诸如，图17中一般性地以810表示的)施加(构建)到衬底载体300的第二表面320上，来形成三维扇出结构1700。之后可以执行三维扇出结构1700的球附接和单颗化，来形成单独的集成电路装置1800，如图18所示。
在前面的说明中，已经参考本发明实施例的特定示例对本发明进行了描述。然而显然，可以在其中做出各种修改和改变，而不脱离如所附权利要求中阐述的本发明的范围，并且权利要求并不限于上述的特定实施例。
因为本发明示出的实施例绝大部分可以使用本领域技术人员已知的电子部件或者电路来实现，因此为了便于理解本发明的主要概念，以及避免模糊或者分散本发明的教导，将不会以超出上面所示例说明的被认为是必要的程度来阐述细节。
例如，说明书和权利要求中的术语“前”、“后”、“顶”、“底”、“上”、“下”等等，如果有的话，用于描述的目的，而并不必然用于描述永久性的相对位置。应当理解，如此使用的术语在适当的情形下是可以互换的，使得再次描述的本发明的实施例例如能够以不同于在此示出的或者以其他方式描述的其它的朝向操作。
此外，本领域技术人员应当理解，上述操作之间的分界仅是示意性的。多个操作可合并至单个操作，单个操作可以分配至另外的操作中，并且操作可以在时间上至少部分重叠地来执行。此外，替代的实施例可以包括特定操作的多个实例，并且在不同的其他实施例中操作的顺序可以变换。
然而，其它的修改、变形和替代也是可能的。因此，说明书和附图应理解为是展示说明性的而非限制性的。
在权利要求中，位于括号内的任何附图标记都不应理解为对权利要求的限定。术语“包括”并不排除权利要求中所列的元件或者步骤之外的其它元件或者步骤的存在。此外，本文所使用的术语“一”(“a”或者“an”)被定义为一个或者多于一个。此外，权利要求中引语(诸如，“至少一个”和“一个或多个”)的使用，不应理解为暗示了：以“一”(不定冠词“a”或者“an”)引入另外的权利要求的项元，将包括如此引入的权利要求项元的任何特定权利要求限定为仅包括一个该项元的发明，即使当同一权利要求包括引语“一个或多个”或者“至少一个”以及“一”(不定冠词“a”或者“an”)时也是如此。这同样适用于“所述”(定冠词)的使用。除非另作说明，否则诸如“第一”和“第二”的术语用于在该术语所描述的项元之间任意地进行区分。因此，这些术语并不必然表示这些项元的时间上的或者其它的优先次序。在互相不同的权利要求中引述了某些特征(measure)的事实并不表示不能使用这些特征的组合来获得有益效果。

Claims (10)

1.一种制造用于集成电路装置的三维(3D)扇出结构的方法，该方法包括：
提供衬底载体，其包括相对的第一和第二表面，以及在第一和第二表面之间贯穿延伸的孔；
将第一半导体片芯接合至衬底载体的第一表面，使得第一半导体片芯覆盖衬底载体的孔；
在衬底载体的孔内沉积封装剂和第二半导体片芯，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及
将至少一个再分配层施加至衬底载体的第二表面上，来形成3D扇出结构。
2.如权利要求1的方法，其中：
第一半导体片芯的有效表面上的接触焊盘接合至位于衬底载体的第一表面上的导电焊盘，以及
第一半导体片芯倒装接合至衬底载体的第一表面。
3.如权利要求1的方法，其中：
在衬底载体的孔内沉积封装剂和第二半导体片芯包括将封装剂分配至孔中，并且随后将第二半导体片芯沉积在孔内的封装剂中，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及
其中使用超尺寸拾取和放置管嘴沉积第二半导体片芯。
4.如权利要求1的方法，其中将封装剂和第二半导体片芯沉积在衬底载体的孔内包括：
将粘附剂层施加至接合至衬底载体的第一表面的第一半导体片芯的表面区域，第一半导体片芯的所述表面区域暴露在衬底载体的孔内；
将第二半导体片芯沉积到在衬底的孔内的粘附剂层上，使得第二半导体片芯的有效表面与衬底载体的第二表面共面；以及
将封装剂分配至孔中在第二半导体片芯的周围。
5.一种用于集成电路装置的三维(3D)扇出结构，该3D扇出结构包括：
衬底载体，其包括相对的第一和第二表面，以及贯穿其延伸的孔；
第一半导体片芯，其接合至衬底载体的第一表面，使得第一半导体片芯覆盖衬底载体的孔；
封装剂和第二半导体片芯，其位于衬底载体的孔内，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及
至少一个再分配层，其施加至衬底载体的第二表面上。
6.如权利要求5的3D扇出结构，其中，第一半导体片芯的有效表面上的接触焊盘接合至位于衬底载体的第一表面上的导电焊盘。
7.如权利要求6的3D扇出结构，其中第一半导体片芯倒装接合至衬底载体的第一表面。
8.一种具有用于集成电路装置的三维(3D)扇出结构的集成电路装置，该3D扇出结构包括：
衬底载体，其具有相对的第一和第二表面，以及在第一和第二表面之间延伸的孔；
第一半导体片芯，其接合至衬底载体的第一表面，使得第一半导体片芯覆盖衬底载体的孔；
封装剂和第二半导体片芯，其位于衬底载体的孔内，使得第二半导体片芯的有效表面暴露并且与衬底载体的第二表面共面；以及
至少一个再分配层，其施加至衬底载体的第二表面上。
9.如权利要求8的集成电路装置，其中，第一半导体片芯的有效表面上的接触焊盘接合至位于衬底载体的第一表面上的导电焊盘。
10.如权利要求9的集成电路装置，其中第一半导体片芯倒装接合至衬底载体的第一表面。
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