JP6249578B2 - 密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ - Google Patents
密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ Download PDFInfo
- Publication number
- JP6249578B2 JP6249578B2 JP2016538925A JP2016538925A JP6249578B2 JP 6249578 B2 JP6249578 B2 JP 6249578B2 JP 2016538925 A JP2016538925 A JP 2016538925A JP 2016538925 A JP2016538925 A JP 2016538925A JP 6249578 B2 JP6249578 B2 JP 6249578B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- build
- wide pads
- pads
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1438—Flash memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims (18)
- キャリアの接着層上にビルドアップ層を形成する段階と、
1より多い半導体ダイを前記ビルドアップ層に圧入する段階であり、前記半導体ダイのそれぞれは前もって機能試験されており、前記機能試験を容易にする複数のワイドパッドを有し、同一のダイ上の前記複数のワイドパッドのうちの少なくとも幾つかは、前記ダイの製造プロセスにより許容される最小距離離間される、段階と、
前記半導体ダイの上にモールドを形成する段階と、
前記キャリアから前記ビルドアップ層を取り外す段階と、
前記複数のワイドパッドの前記少なくとも幾つかの上に複数のビア開口を形成するために、前記複数のワイドパッドのうちの前記少なくとも幾つかの上の前記ビルドアップ層を除去する段階であり、前記複数のビア開口は、テーパ状であり、前記複数のワイドパッドより小さい幅の底を有する、段階と、
前記ビルドアップ層上にメタライゼーション層を形成する段階であり、前記メタライゼーション層は実質的に前記複数のビア開口を埋める、段階と、
埋められた前記複数のビア開口の上に複数のランドおよび前記複数のワイドパッドのうちの前記少なくとも幾つかのそれぞれのランドの間に1より多いワイヤを形成するために前記メタライゼーション層をパターニングする段階と、
前記複数のランド上に複数のはんだボールまたは複数のC4ボールを形成する段階と、
を備える方法。 - 前記圧入する段階の後、ダイの複数のパッドが位置する前記ダイの表面上の複数の凹部領域内の複数のボイドをより適切に埋めるために、前記半導体ダイおよびビルドアップ層の周りの大気圧を上げる段階をさらに備える、請求項1に記載の方法。
- 前記モールドを形成する段階の前に、前記ビルドアップ層を硬化する段階をさらに備える、請求項1または2に記載の方法。
- 前記複数のワイドパッドは、それぞれ約40μm幅である、請求項1から3のいずれか一項に記載の方法。
- 前記ビルドアップ層を除去する段階は、レーザの使用を含む、請求項1から4のいずれか一項に記載の方法。
- ビルドアップ層の下側に圧入された複数のダイのパッドサイドを有する前記ビルドアップ層であり、前記複数のダイは、前記複数のダイのウエハ試験を容易にする複数のワイドパッドを有し、前記複数のワイドパッドは、それぞれのダイを製造するために使用される製造プロセスにより許容される最小距離離間され、前記ビルドアップ層は、前記複数のワイドパッドの上の複数の領域から除去され、前記複数の領域は、テーパ状であり、前記複数のワイドパッドより小さい幅の底を有する、ビルドアップ層と、
前記複数のワイドパッドの上の複数の領域を実質的に埋める、前記ビルドアップ層の上面上のメタライゼーション層であり、前記メタライゼーション層は、前記複数のワイドパッドの上の複数のランドおよび前記複数のワイドパッドの間の複数のワイヤを含む、メタライゼーション層と、
前記複数のランド上に形成される複数のはんだボールまたは複数のC4ボールと、
を備える装置。 - 前記複数のワイドパッドは、それらが前記ビルドアップ層およびメタライゼーション層を用いてパッケージングされる前に、前記ダイの試験による跡をさらす、請求項6に記載の装置。
- 前記複数のワイドパッドに接触する前記メタライゼーション層の底領域は、前記複数のワイドパッドを通る最大定格の電流に耐えるのに十分な幅を有する、請求項6または7に記載の装置。
- 前記ビルドアップ層の厚みは、前記複数の領域の周りの前記ビルドアップ層の複数の側壁に沿うテーパリングの観点から、前記幅を規定する、請求項8に記載の装置。
- 前記ビルドアップ層は、ポリイミド、エポキシ、アクリル、低k材料、シリコーン、およびPBOからなる群から選択される、請求項6から9のいずれか一項に記載の装置。
- 前記ビルドアップ層および前記メタライゼーション層の上に形成される誘電体をさらに備える、請求項6から10のいずれか一項に記載の装置。
- 前記複数のランドの上の前記誘電体内に形成される複数の開口をさらに備える、請求項11に記載の装置。
- プレーナボードと、
前記プレーナボードに付けされたマルチチップモジュールと、を備え、
前記マルチチップモジュールは、
ビルドアップ層の下側に圧入された複数のダイのパッドサイドを有する前記ビルドアップ層であり、前記複数のダイは、前記複数のダイのウエハ試験を容易にする複数のワイドパッドを有し、前記複数のワイドパッドは、それぞれのダイを製造するために使用される製造プロセスにより許容される最小距離離間され、前記ビルドアップ層は、前記複数のワイドパッドの上の複数の領域から除去され、前記複数の領域は、テーパ状であり、前記複数のワイドパッドより小さい幅の底を有する、ビルドアップ層と、
前記複数のワイドパッドの上の複数の領域を実質的に埋める、前記ビルドアップ層の上面上のメタライゼーション層であり、前記メタライゼーション層は、前記複数のワイドパッドの上の複数のランドおよび前記複数のワイドパッドの間の複数のワイヤを含み、前記複数のランド上に複数のはんだボールまたは複数のC4ボールが形成される、メタライゼーション層と、を含む、
システム。 - 前記複数のワイドパッドは、それらが前記ビルドアップ層およびメタライゼーション層を用いてパッケージングされる前に、前記ダイの試験による跡をさらす、請求項13に記載のシステム。
- 前記複数のワイドパッドに接触する前記メタライゼーション層の底領域は、前記複数のワイドパッドを通る最大定格の電流に耐えるのに十分な幅を有する、請求項13または14に記載のシステム。
- 前記システムは、コンピューティングシステムである、請求項13から15のいずれか一項に記載のシステム。
- 前記コンピューティングシステムは、インテリジェントデバイス、スマートフォン、タブレットコンピュータ、ラップトップコンピュータ、デスクトップコンピュータ、およびサーバコンピュータのうちの何れかである、請求項16に記載のシステム。
- 前記システムは、ネットワーキングシステムである、請求項13から17のいずれか一項に記載のシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2014/048510 WO2016018237A1 (en) | 2014-07-28 | 2014-07-28 | A multi-chip-module semiconductor chip package having dense package wiring |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016532302A JP2016532302A (ja) | 2016-10-13 |
JP6249578B2 true JP6249578B2 (ja) | 2017-12-20 |
Family
ID=55217961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016538925A Active JP6249578B2 (ja) | 2014-07-28 | 2014-07-28 | 密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ |
Country Status (9)
Country | Link |
---|---|
US (1) | US10256211B2 (ja) |
EP (1) | EP3175481B1 (ja) |
JP (1) | JP6249578B2 (ja) |
KR (2) | KR20160077010A (ja) |
CN (1) | CN105684146B (ja) |
MY (1) | MY183623A (ja) |
SG (1) | SG11201610675UA (ja) |
TW (1) | TWI593073B (ja) |
WO (1) | WO2016018237A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11171109B2 (en) * | 2019-09-23 | 2021-11-09 | Micron Technology, Inc. | Techniques for forming semiconductor device packages and related packages, intermediate products, and methods |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5866952A (en) * | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
JP3681855B2 (ja) * | 1997-04-02 | 2005-08-10 | シチズン時計株式会社 | Icパッケージの構造 |
JP4045471B2 (ja) * | 1997-04-18 | 2008-02-13 | 日立化成工業株式会社 | 電子部品実装法 |
JP2001015637A (ja) * | 1999-06-30 | 2001-01-19 | Mitsubishi Electric Corp | 回路配線方式及び回路配線方法及び半導体パッケージ及び半導体パッケージ基板 |
US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
JP2004281898A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2006100710A (ja) * | 2004-09-30 | 2006-04-13 | Seiko Epson Corp | 電子部品の実装構造及び、該実装構造を備えた記録装置 |
JP2007115957A (ja) | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US7476563B2 (en) * | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
KR100802995B1 (ko) * | 2007-02-27 | 2008-02-14 | 대덕전자 주식회사 | 웨이퍼 레벨 패키지 제작 방법 |
US8183095B2 (en) * | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
JP2010219489A (ja) * | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2010232616A (ja) * | 2009-03-30 | 2010-10-14 | Nec Corp | 半導体装置及び配線基板 |
US20110110061A1 (en) | 2009-11-12 | 2011-05-12 | Leung Andrew Kw | Circuit Board with Offset Via |
US8901724B2 (en) * | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8482136B2 (en) * | 2009-12-29 | 2013-07-09 | Nxp B.V. | Fan-out chip scale package |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
JP5584011B2 (ja) | 2010-05-10 | 2014-09-03 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
TWI423355B (zh) | 2010-08-04 | 2014-01-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
SG182921A1 (en) * | 2011-01-21 | 2012-08-30 | Stats Chippac Ltd | Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief |
US10388584B2 (en) * | 2011-09-06 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die |
WO2013057949A2 (en) * | 2011-10-19 | 2013-04-25 | Panasonic Corporation | Manufacturing method for semiconductor package, semiconductor package, and semiconductor device |
US9123830B2 (en) * | 2011-11-11 | 2015-09-01 | Sumitomo Bakelite Co., Ltd. | Manufacturing method for semiconductor device |
US8558395B2 (en) * | 2012-02-21 | 2013-10-15 | Broadcom Corporation | Organic interface substrate having interposer with through-semiconductor vias |
US9881894B2 (en) | 2012-03-08 | 2018-01-30 | STATS ChipPAC Pte. Ltd. | Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration |
KR101958831B1 (ko) | 2012-06-08 | 2019-07-02 | 삼성전자주식회사 | 양면 접착성 테이프, 반도체 패키지 및 그 제조 방법 |
JP2014072494A (ja) | 2012-10-01 | 2014-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US9190380B2 (en) * | 2012-12-06 | 2015-11-17 | Intel Corporation | High density substrate routing in BBUL package |
US8866308B2 (en) * | 2012-12-20 | 2014-10-21 | Intel Corporation | High density interconnect device and method |
JP5758374B2 (ja) | 2012-12-27 | 2015-08-05 | 日信工業株式会社 | 負圧ブースタ |
KR101472640B1 (ko) * | 2012-12-31 | 2014-12-15 | 삼성전기주식회사 | 회로 기판 및 회로 기판 제조방법 |
WO2014142075A1 (ja) * | 2013-03-13 | 2014-09-18 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
JP5784775B2 (ja) * | 2014-03-19 | 2015-09-24 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
-
2014
- 2014-07-28 EP EP14873106.0A patent/EP3175481B1/en active Active
- 2014-07-28 KR KR1020157017262A patent/KR20160077010A/ko active Application Filing
- 2014-07-28 JP JP2016538925A patent/JP6249578B2/ja active Active
- 2014-07-28 WO PCT/US2014/048510 patent/WO2016018237A1/en active Application Filing
- 2014-07-28 SG SG11201610675UA patent/SG11201610675UA/en unknown
- 2014-07-28 CN CN201480003718.4A patent/CN105684146B/zh active Active
- 2014-07-28 US US14/655,688 patent/US10256211B2/en active Active
- 2014-07-28 KR KR1020177015715A patent/KR102124691B1/ko active IP Right Grant
- 2014-07-28 MY MYPI2016704844A patent/MY183623A/en unknown
-
2015
- 2015-06-25 TW TW104120577A patent/TWI593073B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR102124691B1 (ko) | 2020-06-18 |
WO2016018237A1 (en) | 2016-02-04 |
CN105684146B (zh) | 2019-01-18 |
SG11201610675UA (en) | 2017-01-27 |
TW201618265A (zh) | 2016-05-16 |
EP3175481A4 (en) | 2018-04-04 |
KR20160077010A (ko) | 2016-07-01 |
MY183623A (en) | 2021-03-03 |
CN105684146A (zh) | 2016-06-15 |
US20160293578A1 (en) | 2016-10-06 |
JP2016532302A (ja) | 2016-10-13 |
KR20170070259A (ko) | 2017-06-21 |
US10256211B2 (en) | 2019-04-09 |
TWI593073B (zh) | 2017-07-21 |
EP3175481A1 (en) | 2017-06-07 |
EP3175481B1 (en) | 2021-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9324626B2 (en) | Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication | |
US9040361B2 (en) | Chip scale package with electronic component received in encapsulant, and fabrication method thereof | |
KR101476894B1 (ko) | 다중 다이 패키징 인터포저 구조 및 방법 | |
CN107808856B (zh) | 半导体封装结构及其制造方法 | |
US9165911B2 (en) | Microelectronic package with stacked microelectronic units and method for manufacture thereof | |
US20140042638A1 (en) | Semiconductor package and method of fabricating the same | |
US8766456B2 (en) | Method of fabricating a semiconductor package | |
CN103779235A (zh) | 扇出晶圆级封装结构 | |
JP2008160084A (ja) | ダイ収容キャビティを備えたウェーハレベルパッケージおよびその方法 | |
KR20160011139A (ko) | Ic 패키지용 고밀도 필름 | |
TW201543586A (zh) | 封裝結構及其製法 | |
KR102647008B1 (ko) | 팬 아웃 패키지 및 이의 형성 방법 | |
US20160189983A1 (en) | Method and structure for fan-out wafer level packaging | |
TW201349399A (zh) | 中介基材及其製作方法 | |
JP6249578B2 (ja) | 密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ | |
TWI766192B (zh) | 電子封裝件及其製法 | |
JP6678196B2 (ja) | 半導体装置及び配線構造体の製造方法 | |
TWM521807U (zh) | 封裝結構及其中介板 | |
US9564391B2 (en) | Thermal enhanced package using embedded substrate | |
KR20100124161A (ko) | 반도체 패키지의 제조방법 | |
KR101579434B1 (ko) | 반도체 패키지 제조 방법 | |
US11894357B2 (en) | System-level packaging structure and method for LED chip | |
KR102457349B1 (ko) | 반도체 패키지들 및 이의 제조 방법들 | |
US20240136297A1 (en) | Multi-chip interconnection package structure with heat dissipation plate and preparation method thereof | |
JP2016213372A (ja) | 半導体装置及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160920 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161212 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170314 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170515 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20171024 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20171120 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6249578 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |