CN105684146B - 具有密集封装布线的多芯片模块半导体芯片封装 - Google Patents

具有密集封装布线的多芯片模块半导体芯片封装 Download PDF

Info

Publication number
CN105684146B
CN105684146B CN201480003718.4A CN201480003718A CN105684146B CN 105684146 B CN105684146 B CN 105684146B CN 201480003718 A CN201480003718 A CN 201480003718A CN 105684146 B CN105684146 B CN 105684146B
Authority
CN
China
Prior art keywords
pad
buildup layer
layer
metallization
tube core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480003718.4A
Other languages
English (en)
Other versions
CN105684146A (zh
Inventor
C.胡
C-P.丘
J.斯旺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN105684146A publication Critical patent/CN105684146A/zh
Application granted granted Critical
Publication of CN105684146B publication Critical patent/CN105684146B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

描述了一种具有内建层的装置。内建层具有按压到内建层的底部侧中的多个管芯的焊盘侧。多个管芯具有宽焊盘以促进多个管芯的晶片上测试。宽焊盘间隔用于制造其相应管芯的制造工艺所准许的最小距离。在宽焊盘上方的内建层被移除。装置还包括大体上填充宽焊盘上方的区域的在内建层的顶部侧上的金属化。金属化包括宽焊盘上方的连接盘和宽焊盘之间的多个接线。

Description

具有密集封装布线的多芯片模块半导体芯片封装
技术领域
本发明的领域一般地关于半导体芯片封装，并且更重要地，关于具有密集封装布线的多芯片模块半导体芯片封装。
具体实施方式
多芯片模块（MCM）是包含多于一个半导体芯片的单个芯片封装。将多个半导体芯片成功地集成到单个封装中呈现出技术挑战以及成本问题。这些中的一些在图1a中描绘的现有技术MCM中被观察到。
图1a示出具有一对半导体管芯（die）101_1和101_2的现有技术MCM 100。每一个管芯的顶表面包括暴露的焊盘102和钝化层103。如在图1中观察到的，在每一个管芯101_1、101_2之上图案化金属化层104。金属化层104提供布线迹线105，其可以形成在管芯101_1、101_2之间以电气耦合它们和/或形成在管芯与焊球106之间以形成封装的I/O。图1b示出在正交于图1a的描绘的方向上的横截面以示出布线迹线到焊盘102的互连。通过这样的互连，相同管芯的焊盘或不同管芯的焊盘可以通过布线迹线105连接。
显然，管芯具有宽焊盘102（例如跨至少40μm）以便在切割之前在以晶片形式时促进管芯的功能测试。通过在将管芯集成到封装中之前对其进行测试，封装“劣质”管芯的成本大幅降低。然而，大的焊盘尺寸对应于管芯之间的封装内的降低的布线密度。
具体地，宽焊盘102导致宽通孔107和对应连接盘（land）113的产生，其进而限制在连接盘113之间可用于布线迹线105的空间。如在图1a中观察到的，存在在连接盘113之间仅用于一个布线迹线的空间。连接盘113之间的有限的布线空间最终限制芯片到芯片接线的数目和/或封装的I/O密度。任一者都可能对应于不切实际的解决方案（例如，其中需要芯片之间的密集布线和/或需要密集封装I/O，或者需要较大尺寸的半导体管芯）。
降低管芯焊盘尺寸以准许较小通孔的形成和连接盘113之间的增加的布线密度实际上并不可取，因为这将会阻碍晶片上测试，从而导致完全封装劣质管芯的增加的风险。
附图说明
可以从结合以下附图的以下详细描述获得对本发明的更好理解，其中：
图1a-b示出现有技术多芯片封装；
图2a-2k示出用于制造改进的多芯片封装的工艺；
图3示出具有改进的多芯片封装的系统。
具体实施方式
图2a至2k描述了用于形成改进的MCM的工艺，其提供接触宽管芯焊盘的通孔上方的连接盘之间的增加的布线密度。所述工艺可以例如实现为晶片级工艺或面板级（panel-level）工艺。由于管芯具有宽焊盘，因此可以在封装之前在晶片上对管芯进行功能测试，从而降低完全封装劣质管芯的风险。此外，连接盘之间的增加的布线密度准许管芯之间的增加的布线和/或增加的封装I/O密度。
如在图2a中所观察到的，并且粘附层202被施加到载体201。载体201可以是具有用于施加粘附层202的平面表面的任何牢固结构。如以下将更加详细地描述的，粘附层202的特性在于其相当易于“分层”或以其它方式从载体201的表面移除。在各种实施例中，粘附层202是聚合物或聚合物状物质。
如在图2b中所观察到的，内建（build-up）层203被施加到粘附层202的表面。如以下将更加详细地描述的，内建层的厚度在实现本说明书力图帮助实现的改进中的至少部分中具有一定重要性。内建层203可以以液相施加并且在粘附层/载体结构上旋涂到适当厚度，或者以较为固相施加，诸如干性薄膜（干性薄膜厚度的控制在本领域中很好地理解）。
用于内建层材料203的一些示例是聚酰亚胺、环氧树脂、丙烯酸、低k材料（例如B阶段（B-staged）双苯并环丁烯（BCB））、硅树脂和聚苯并恶唑（PBO）。如以下将更加详细地讨论的，内建层203应当具有对其的某种软度或者以其它方式在其形成于粘附层202上之后可压缩。
内建层203应当是电介质并且能够在其初始以软化状态形成在粘附层202上之后被“硬化”。在此，同样如以下将进一步更加详细地讨论的，经硬化的内建层203将在生产结束之后保留在封装中。正因为这样，它应当能够充当电绝缘体以及表现出在完成的封装内的耐久性。至少在内建层203的液相施加的情况中，内建层203可以被固化（例如通过光刺激），使得其在施加到粘附层202的表面之后在粘附层202的表面上硬化。
如在图2c中所观察到的，具有宽焊盘205（例如跨大于40μm）以促进之前的晶片上的功能测试的两个或更多经功能测试的半导体管芯204被按压（正面向下）到内建层203中（例如通过拾取和按压（pick-and-press）工艺）以作为将管芯204附着到内建层/粘附层/载体结构的方式。在此，内建层203的前述软度促进管芯到内建层203中的按压以将其粘附到内建层203。内建层203在将管芯按压到内建层203中期间甚至可以处于液相。
所关注的问题是内建层203能够将与凹陷到管芯204的钝化层207中的焊盘205相关联的腔体206“填充”到的程度（如果焊盘如此凹陷的话）。在此，压热器（autoclave）工艺可以用于帮助填充在已经将管芯204按压到内建层203中之后保留在腔体206中的任何空隙。压热器工艺增加在初始将管芯204按压到内建层203中之后围绕结构的周围环境的大气压力，使得柔软/液体内建层203自然地按压得更加深入到腔体206中。在实施例中，初始在真空大气压力或其附近处将管芯204按压到内建层203中，使得压热器工艺的增加的压力可以是常规大气压力。
同样，内建层203的厚度在实现前述布线密度改进中可以具有一定重要性。以下进一步更加详细地描述内建层203厚度。
如在图2d中所观察到的，内建层203被固化以从实现管芯204的按压附着的软化状态转变到对于完成的封装结构而言适当耐久的硬化状态。固化可以利用光照和/或利用较高温度的施加来执行，这取决于用于内建层203的材料。
如在图2e中所观察到的，在内建层203被固化之后，在管芯204和经固化的内建层203的暴露区域之上施加模具化合物或更一般地“模具”208。模塑（molding）工艺的部分包括形成大体平面的模具表面。模具208可以通过压缩模塑、传递模塑、注入模塑中的任一个来施加。模具208物质可以是高度填充的热固性环氧树脂。在实施例中，在较高温度处以大体液相来施加模具。经固化的内建层203应当具有高于模具208在其形成于经固化的内建层203之上时的温度的熔点/或玻璃转变温度。
模具208的厚度应当足以覆盖管芯204的最厚处。在此，尽管图示出相等厚度的多个管芯204，但是可设想到各种管芯204将具有实质上不等的厚度（例如，两个或更多管芯从不同的制造工艺制造）。模具可以容易地使其形式适配于不同的管芯厚度并且仍旧被成形以产生大体平面的表面209。
如在图2f中所观察到的，粘附层202被移除，从而分离载体201并且留下具有作为一个外部平面表面的内建层203和作为另一外部平面表面209的模具208的总体结构。总体结构被翻转，使得内建层203表面面向上以支持随后的金属化和布线工艺。
用于破坏粘附层202使得总体结构可以没有载体201的工艺可以是热诱导的（induced）（例如，粘附层202将响应于提升的温度而在结构上被破坏或者改变成液相）、化学诱导的（例如，粘附层202具有与载体的化学键并且可以通过诱导经过其而释放化学键的化学工艺来使得发生分层）、机械诱导的（例如，粘附层202是脆的并且可以从载体断裂，例如通过将翘曲诱导到载体的表面中）和/或光学诱导的（例如，可以例如通过响应于被用光照射（例如通过透明载体）而从固相转变到液相来使得粘附层202的结构性质改变）。在实施例中，在金属化工艺开始之前将粘附层202的其余部分从内建层203的表面移除（例如经由向最初与载体接触的内建层表面施加压缩空气）。
因此，如图2f，内建层203的大体平面的表面面向上而为金属化工艺作准备。
如在图2g中所观察到的，通孔开口210形成在内建层203中在管芯204的焊盘205上方（例如，借助于利用掩模的激光烧蚀、光致抗蚀剂施加/图案化/蚀刻、或激光束打孔）。如以下更加详细地讨论的，通孔开口210是小的，其准许更高密度的布线。
如在图2h中所观察到的，将金属化层211施加到内建层203的表面。金属化211可以通过诸如溅射、电镀和印刷之类的沉积工艺来施加。可以用于形成金属化层211的其它类型的工艺包括焊膏印刷（paste printing）、烧结、喷墨印刷。金属化层典型地包括铝、镍、银、金和铜中的至少一个。
如在图2i中所观察到的，金属化211被图案化（例如，借助于光致抗蚀剂施加/图案化/蚀刻）以形成布线212和连接盘213。显然，可以在连接盘213之间形成多个接线212。在此，在实施例中，其中最小管芯焊盘间隔217为15μm。可以将具有3/3μm线宽的高达7个接线放置在具有55μm间距的焊球216/连接盘213之间。下表示出附加的示例和对照图1a、b的现有技术方案的比较。
重要的是，相同管芯上的宽焊盘205可以间隔开217管芯的制造工艺所准许的最小距离。这导致同样在它们之间以最小距离间隔开的形成在相同管芯之上的连接盘213的形成。
如在图2j中所观察到的，在已经对布线层图案化之后，电介质层215形成在金属化211之上。电介质层215在连接盘213上方图案化以在电介质层215中形成使连接盘213暴露的开口。焊球或C4球216然后形成在暴露的连接盘213上。作为可选的工艺，随后对封装进行密封（例如，利用密闭地密封封装的内部的盖子）。
参考图2g至2j，要指出的是，内建层203允许管芯204上的宽焊盘205上方的小通孔开口210的形成。小通孔开口210进而提供如与在图1的现有技术方案中观察到的连接盘113相比小得多的连接盘213的形成。更小的连接盘213留下其中可以封装更多接线212的附加的平面空间，即使如以上所讨论的，相同管芯上的宽焊盘间隔开由管芯的制造工艺所准许的最小距离217并且连接盘213对应地也间隔开最小距离。
关于内建层203的厚度，在低端，内建层203应当大于管芯204的表面的最大翘曲容限，使得确保内建层203覆盖管芯204在其被按压到内建层203中时的表面。例如，如果管芯204可以表现出如1-2μm那么多的竖直翘曲（即，管芯的表面上的两个点可以具有在它们之间的如1-2μm那么多的竖直位移），内建层的厚度应当大于1-2μm。
在高端，应当考虑通孔开口210的形成的动态特性连同通过任何通孔汲取的最差情况的电流。一般而言，通孔开口210的形状是圆锥形或锥形的（也就是说，通孔开口的直径通过移动得更加深入到通孔开口中而连续缩小）。正因为这样，一般而言，通孔的最小宽度在与焊盘205的接触点处。如果宽度对于通过焊盘和通孔汲取的电流量而言过小，可能导致电气失效。正因为这样，内建层的厚度不应当超过其中通孔的底部对于要通过它们汲取的电流量而言过窄的厚度。
要指出的是，在被封装之前在管芯上执行测试的同时，焊盘205可能表现出对之前接触焊盘的探测器某种害怕（scaring）。
图2k示出在正交于图2j的描绘的方向上的横截面以示出布线迹线212到焊盘205的互连。通过这样的互连，相同管芯的焊盘或不同管芯的焊盘可以通过布线迹线212连接。
图3示出安装到平面板320的完整封装310。尽管之前的图在所描绘的横截面中仅描绘了两个管芯，但是应当理解的是，可以在封装310内包封多于一个管芯。显然，不同管芯可以包括相同管芯的不同实例（例如两个相同设计的存储器芯片）和/或不同管芯的不同实例（例如芯片上系统管芯和动态随机存取存储器管芯）。在不同管芯的不同实例的情况中，不同管芯可以根据不同的制造工艺技术来制造（例如高密度逻辑、闪存、动态随机存取存储器、相变存储器和开关）。
平面板320和所安装的封装310可以集成到任何更大的计算系统330中，诸如手持设备（例如智能电话）、平板计算机、膝上型计算机、台式计算机或服务器计算机。同样地，平面板320和所安装的封装310可以集成到其它类型的电子装置中，诸如网络路由器、网络交换机、智能设备（例如智能手表、智能眼镜等）。
在前述说明书中，已经参考其特定示例性实施例描述了本发明。然而，将明显的是，可以在不脱离于如随附权利要求中阐述的本发明的更宽的精神和范围的情况下对其做出各种修改和改变。因此，说明书和附图要以说明性而非限制性的含义来看待。

Claims (16)

1.一种用于半导体芯片封装的方法，包括：
在载体的粘附层上形成内建层；
将多于一个半导体管芯按压到内建层中，每一个半导体管芯之前已经被功能测试并且具有焊盘以促进测试，其中，相同管芯上的焊盘的至少一些间隔开所述管芯的制造工艺所准许的最小距离；
在半导体管芯之上形成模塑物；
将内建层从载体分离；
移除焊盘的至少一些上方的内建层以在焊盘的至少一些上方形成通孔开口；
在内建层上形成金属化层，金属化层大体上填充通孔开口；
对金属化进行图案化以形成所填充的通孔开口上方的连接盘和焊盘的至少一些的相应连接盘之间的多于一个接线；以及
在按压之后升高半导体管芯和内建层周围的大气压力以更好地填充管芯的焊盘位于其中的管芯表面上的凹陷区域中的空隙。
2.权利要求1的方法，还包括在模塑物的形成之前使内建层硬化。
3.权利要求1的方法，其中焊盘均跨近似40μm。
4.权利要求1的方法，还包括在连接盘上形成焊球或C4球。
5.权利要求1的方法，其中移除内建层包括使用激光器。
6.一种用于半导体芯片封装的装置，包括：
内建层，其具有按压到内建层的底部侧中的多个管芯的焊盘侧，多个管芯具有焊盘以促进多个管芯的晶片上测试，焊盘被间隔用于制造其相应管芯的制造工艺所准许的最小距离，在焊盘上方的内建层被移除；
在内建层的顶部侧上并且大体上填充在焊盘上方的区域的金属化，金属化包括焊盘上方的连接盘和连接盘之间的多个接线；
其中在按压之后升高半导体管芯和内建层周围的大气压力以更好地填充管芯的焊盘位于其中的管芯表面上的凹陷区域中的空隙。
7.权利要求6的装置，其中与焊盘接触的金属化的底部区域具有足以承受通过所述焊盘的最大额定电流流动的宽度。
8.权利要求7的装置，其中内建层的厚度在所述区域周围沿所述内建层的侧壁成锥形的方面提供所述宽度。
9.权利要求6的装置，其中所述内建层选自包括以下各项的组：
聚酰亚胺；
环氧树脂；
丙烯酸；
低k材料；
硅树脂；
PBO。
10.权利要求6的装置，还包括形成在内建层和金属化之上的电介质。
11.权利要求6的装置，开口形成在连接盘上方的电介质中并且焊球或C4球形成在连接盘上。
12.一种用于半导体芯片封装的系统，包括：
平面板，
附到平面板的多芯片模块，多芯片模块包括：
内建层，其具有按压到内建层的底部侧中的多个管芯的焊盘侧，多个管芯具有焊盘以促进多个管芯的晶片上测试，焊盘被间隔用于制造其相应管芯的制造工艺所准许的最小距离，在焊盘上方的内建层被移除；
在内建层的顶部侧上并且大体上填充焊盘上方的区域的金属化，金属化包括焊盘上方的连接盘和连接盘之间的多个接线；
其中在按压之后升高半导体管芯和内建层周围的大气压力以更好地填充管芯的焊盘位于其中的管芯表面上的凹陷区域中的空隙。
13.权利要求12的系统，其中与焊盘接触的金属化的底部区域具有足以承受通过所述焊盘的最大额定电流流动的宽度。
14.权利要求12的系统，其中所述系统是计算系统。
15.权利要求14的系统，其中所述计算系统是以下中的任何一个：
智能设备；
智能电话；
平板计算机；
膝上型计算机；
台式计算机；
服务器计算机。
16.权利要求12的装置，其中所述系统是联网系统。
CN201480003718.4A 2014-07-28 2014-07-28 具有密集封装布线的多芯片模块半导体芯片封装 Active CN105684146B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/048510 WO2016018237A1 (en) 2014-07-28 2014-07-28 A multi-chip-module semiconductor chip package having dense package wiring

Publications (2)

Publication Number Publication Date
CN105684146A CN105684146A (zh) 2016-06-15
CN105684146B true CN105684146B (zh) 2019-01-18

Family

ID=55217961

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480003718.4A Active CN105684146B (zh) 2014-07-28 2014-07-28 具有密集封装布线的多芯片模块半导体芯片封装

Country Status (9)

Country Link
US (1) US10256211B2 (zh)
EP (1) EP3175481B1 (zh)
JP (1) JP6249578B2 (zh)
KR (2) KR102124691B1 (zh)
CN (1) CN105684146B (zh)
MY (1) MY183623A (zh)
SG (1) SG11201610675UA (zh)
TW (1) TWI593073B (zh)
WO (1) WO2016018237A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11171109B2 (en) * 2019-09-23 2021-11-09 Micron Technology, Inc. Techniques for forming semiconductor device packages and related packages, intermediate products, and methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1555574A (zh) * 2001-05-21 2004-12-15 ض� 利用芯片上焊盘扩大部分封装微电子器件的方法
CN103715151A (zh) * 2012-10-01 2014-04-09 株式会社东芝 半导体器件及其制造方法
US20140191406A1 (en) * 2011-10-19 2014-07-10 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
JP3681855B2 (ja) * 1997-04-02 2005-08-10 シチズン時計株式会社 Ｉｃパッケージの構造
JP4045471B2 (ja) * 1997-04-18 2008-02-13 日立化成工業株式会社 電子部品実装法
JP2001015637A (ja) * 1999-06-30 2001-01-19 Mitsubishi Electric Corp 回路配線方式及び回路配線方法及び半導体パッケージ及び半導体パッケージ基板
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2004281898A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2006100710A (ja) * 2004-09-30 2006-04-13 Seiko Epson Corp 電子部品の実装構造及び、該実装構造を備えた記録装置
JP2007115957A (ja) 2005-10-21 2007-05-10 Seiko Epson Corp 半導体装置及びその製造方法
US7476563B2 (en) * 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
KR100802995B1 (ko) * 2007-02-27 2008-02-14 대덕전자 주식회사 웨이퍼 레벨 패키지 제작 방법
US8183095B2 (en) * 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
JP2010219489A (ja) 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法
JP2010232616A (ja) * 2009-03-30 2010-10-14 Nec Corp 半導体装置及び配線基板
US20110110061A1 (en) * 2009-11-12 2011-05-12 Leung Andrew Kw Circuit Board with Offset Via
US8482136B2 (en) 2009-12-29 2013-07-09 Nxp B.V. Fan-out chip scale package
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20110198762A1 (en) * 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric
JP5584011B2 (ja) 2010-05-10 2014-09-03 新光電気工業株式会社 半導体パッケージの製造方法
TWI423355B (zh) 2010-08-04 2014-01-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
TWI528466B (zh) * 2011-01-21 2016-04-01 史達晶片有限公司 形成沈積在半導體晶粒上用於應力緩和之絕緣層的半導體裝置及方法
US10388584B2 (en) * 2011-09-06 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die
TW201330217A (zh) * 2011-11-11 2013-07-16 Sumitomo Bakelite Co 半導體裝置之製造方法
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
KR101958831B1 (ko) * 2012-06-08 2019-07-02 삼성전자주식회사 양면 접착성 테이프, 반도체 패키지 및 그 제조 방법
US9190380B2 (en) * 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US8866308B2 (en) * 2012-12-20 2014-10-21 Intel Corporation High density interconnect device and method
JP5758374B2 (ja) 2012-12-27 2015-08-05 日信工業株式会社 負圧ブースタ
KR101472640B1 (ko) * 2012-12-31 2014-12-15 삼성전기주식회사 회로 기판 및 회로 기판 제조방법
US9589921B2 (en) * 2013-03-13 2017-03-07 Ps4 Luxco S.A.R.L. Semiconductor device
JP5784775B2 (ja) 2014-03-19 2015-09-24 新光電気工業株式会社 半導体パッケージ及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1555574A (zh) * 2001-05-21 2004-12-15 ض� 利用芯片上焊盘扩大部分封装微电子器件的方法
US20140191406A1 (en) * 2011-10-19 2014-07-10 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
CN103715151A (zh) * 2012-10-01 2014-04-09 株式会社东芝 半导体器件及其制造方法

Also Published As

Publication number Publication date
EP3175481A1 (en) 2017-06-07
US10256211B2 (en) 2019-04-09
TWI593073B (zh) 2017-07-21
EP3175481B1 (en) 2021-07-21
TW201618265A (zh) 2016-05-16
KR102124691B1 (ko) 2020-06-18
WO2016018237A1 (en) 2016-02-04
KR20170070259A (ko) 2017-06-21
JP2016532302A (ja) 2016-10-13
JP6249578B2 (ja) 2017-12-20
MY183623A (en) 2021-03-03
SG11201610675UA (en) 2017-01-27
US20160293578A1 (en) 2016-10-06
EP3175481A4 (en) 2018-04-04
CN105684146A (zh) 2016-06-15
KR20160077010A (ko) 2016-07-01

Similar Documents

Publication Publication Date Title
CN104253115B (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
CN106206529B (zh) 半导体器件和制造方法
KR102591618B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
EP2965353B1 (en) A substrate-less interposer
TWI517343B (zh) 覆晶堆疊封裝結構及其製作方法
US10636715B2 (en) Semiconductor package and method of fabricating the same
CN105374693A (zh) 半导体封装件及其形成方法
US20140042638A1 (en) Semiconductor package and method of fabricating the same
CN108987380A (zh) 半导体封装件中的导电通孔及其形成方法
CN105390455A (zh) 用于晶圆级封装件的互连结构及其形成方法
CN106057760A (zh) 半导体器件及其形成方法
US9859130B2 (en) Manufacturing method of interposed substrate
CN108695269B (zh) 半导体装置封装及其制造方法
CN103378041A (zh) 迹线上凸块芯片封装的方法和装置
CN112352305B (zh) 芯片封装结构及芯片封装方法
US20200303213A1 (en) Method of fabricating semiconductor package structure
CN105684146B (zh) 具有密集封装布线的多芯片模块半导体芯片封装
TWI614814B (zh) 基於薄膜之扇出及多晶粒封裝平台
KR101761502B1 (ko) 반도체 디바이스 및 그 제조 방법
US11270921B2 (en) Semiconductor package including dies having high-modulus dielectric layer and manufacturing method thereof
JP2012178565A (ja) 半導体パッケージ構造の製造方法
WO2011105961A1 (en) Method of stacking chips
KR101579434B1 (ko) 반도체 패키지 제조 방법
CN108346586A (zh) 封装体装置及其制造方法
US11756871B2 (en) Fan-out packaging structure and method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant