TWI593073B - 用於形成半導體封裝的方法、封裝設備以及晶片系統 - Google Patents

用於形成半導體封裝的方法、封裝設備以及晶片系統 Download PDF

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TWI593073B
TWI593073B TW104120577A TW104120577A TWI593073B TW I593073 B TWI593073 B TW I593073B TW 104120577 A TW104120577 A TW 104120577A TW 104120577 A TW104120577 A TW 104120577A TW I593073 B TWI593073 B TW I593073B
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layer
buildup layer
wide
metallization
die
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TW201618265A (zh
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胡釧
嘉平 邱
喬安娜 史旺
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英特爾公司
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Description

用於形成半導體封裝的方法、封裝設備以及晶片系統 發明領域
本發明之領域籠統而言係有關於半導體晶片封裝，及更要緊地，係有關於具有密集封裝佈線的多晶片模組半導體晶片封裝。
發明背景
多晶片模組(MCM)乃含有多於一個半導體晶片的單一晶片封裝。成功地將多個半導體晶片整合入單一封裝內帶來了技術挑戰及成本議題。其中若干者於圖1A描繪的先前技術MCM中觀察得。
圖1A顯示先前技術MCM 100具有一對半導體晶粒101_1及101_2。各個晶粒之頂面包括暴露的襯墊102及一被動層103。如於圖1中觀察，一金屬化層104係於各個晶粒101_1、101_2上方製作圖樣。金屬化層104提供佈線線跡105，其可形成於晶粒101_1、101_2間以電氣耦合之及/或形成於一晶粒與一焊料球106間用以形成該封裝的一I/O。圖1B顯示於圖1A描繪方向之正交方向的剖面圖，以顯示佈線線跡至襯墊102的互連。透過此種互連，同一晶粒的襯墊 或不同晶粒的襯墊可經由佈線線跡105連結。
值得注意地，該晶粒具有寬襯墊102(例如，寬至少40微米)以便在切割晶粒之前當呈晶圓形式時促進晶粒的功能測試。藉由在其整合成封裝體之前測試晶粒，封裝「不良」晶粒的成本大減。襯墊的尺寸大相對應於封裝內部晶粒間的佈線密度減低。
更明確言之，寬襯墊102結果導致形成寬通孔107及相對應連接塊113，其又轉而限制了連接塊113間用於佈線線跡105的可用空間。如於圖1中觀察，連接塊113間只有空間容納一個佈線線跡。連接塊113間之此種有限的佈線空間最終限制了晶片至晶片導線的數目及/或封裝的I/O密度。任一者皆可相對應於一不實際的解決方案(例如，當需要晶片間更密集的佈線及/或需要密集封裝I/O，或需要更大型半導體晶粒時)。
縮小晶粒襯墊的大小以許可形成更小型通孔及增高連接塊113間的佈線密度實際上並非一選項，原因在於其將妨礙晶圓測試，結果導致完全封裝不良晶粒的風險增高。
依據本發明之一實施例，係特地提出一種方法，其包含：在一載體之一黏著層上形成一堆積層；加壓多於一個半導體晶粒至該堆積層內，該半導體晶粒各自先前已經功能測試且具有寬襯墊以輔助該測試，其中，在一相同晶粒上的該等寬襯墊中之至少部分係間隔開由該晶粒的製 程容許的一最小距離；在該等半導體晶粒上方形成一模具；自該載體卸下該堆積層；去除在該等寬襯墊中之至少若干上方的堆積層以在該等寬襯墊中之該等至少若干上方形成通孔開口；在該堆積層上形成一金屬化層，該金屬化層實質上填補該等通孔開口；及，將該金屬化製作圖樣以在該等已填補通孔開口上方形成連接塊及在該等寬襯墊中之該等至少若干的個別連接塊間形成多於一根導線。
100‧‧‧多晶片模組(MCM)
101_1~2、204‧‧‧半導體晶粒
102、205‧‧‧襯墊
103、207‧‧‧被動層
104、211‧‧‧金屬化層
105、212‧‧‧佈線線跡、佈線、導線
106、216‧‧‧焊料球、C4球
107‧‧‧通孔
113、213‧‧‧連接塊
201‧‧‧載體
202‧‧‧黏著層
203‧‧‧堆積層
206‧‧‧空腔
208‧‧‧模具
210‧‧‧通孔開口
215‧‧‧介電層
217‧‧‧最小距離
310‧‧‧封裝、封裝體
320‧‧‧平坦板
330‧‧‧計算系統
從後文詳細說明部分結合附圖將更明白瞭解本發明，附圖中：圖1A-B顯示先前技術多晶片封裝；圖2A-2K顯示用於製造改良之多晶片封裝的一種方法；圖3顯示具有該改良之多晶片封裝的一種系統。
較佳實施例之詳細說明
圖2A至圖2K描述一種用以形成改良的MCM之方法，其提供在接觸寬晶粒襯墊的通孔上方連接塊間提高的佈線密度。該製程例如可作為晶圓層級製程或面板層級製程實施。因晶粒具有寬襯墊，故在封裝之前，晶粒可在晶圓上作功能測試，藉此減低完全封裝不良晶粒的風險。此外，連接塊間提高的佈線密度許可晶粒間之佈線增加及/或封裝I/O密度增高。
如於圖2A中觀察，一黏著層202施用至一載體201。載體201可以是具有平坦表面之任何堅固結構用於黏 著層202之施用。容後詳述，黏著層202之一特性為其合理地容易「離層」或以其它方式自載體201表面移除。於各種實施例中，黏著層202為聚合物或聚合物狀物質。
如於圖2B中觀察，一堆積層203施用至黏著層202表面。容後詳述，堆積層之厚度對本文描述尋求輔助實現的至少若干改良的實現上具有若干重要性。堆積層203可於液相施用，且旋上至黏著層/載體結構至適當厚度，或以較為固相施用，諸如乾薄膜(乾薄膜厚度之控制為技藝界眾所周知)。
堆積層材料203之若干實例為聚醯亞胺、環氧樹脂、丙烯酸系、低k材料(例如，B-階段雙苯并環丁烯(BCB))、聚矽氧及聚苯并噁唑(PBO)。容後詳述，堆積層203須有若干柔軟度或否則在其形成至黏著層202上之後為可壓縮。
堆積層203須為介電質且在初始以軟化態形成於黏著層202上之後能夠「硬化」。此處，再度容後詳述，於製造完成之後硬化堆積層203將維持於封裝體內。如此，其將能夠作為電氣絕緣體，以及在封裝體成品內部將具有耐用性。至少以堆積層203之液相施用為例，堆積層203可經硬化(例如，透過光刺激)，使得在施用其上之後在黏著層202表面上硬化。
如於圖2C中觀察，具有寬襯墊205(例如，大於40微米寬)用以協助在晶圓上的先前功能測試的二或多個功能經測試之半導體晶粒204，係以晶粒204附接至堆積層 /黏著層/載體結構之方式壓製(面向下)入堆積層203內部(例如，藉由撿拾與加壓過程)。此處，前述堆積層203之柔軟度有助於將晶粒加壓入堆積層203內以黏著至堆積層203。晶粒加壓入堆積層203內期間，堆積層203甚至可於液相。
擔憂堆積層203能「填補」凹陷入晶粒204的被動層207的一襯墊205(若襯墊如此凹陷)相關聯的空腔206之程度。此處，在晶粒204已經被加壓入堆積層203內之後，高壓鍋製程可用以輔助填補空腔206內部剩餘的任何空隙。在晶粒204初步加壓入堆積層203內之後，高壓鍋處理增高環繞該結構體周圍的大氣壓，使得柔軟/液體堆積層203自然地加壓深入空腔206內部。於一實施例中，晶粒204初步於真空大氣壓或其附近加壓入堆積層203內，使得高壓鍋製程之增高的壓力可為常規大氣壓。
再度，堆積層203之厚度在實現前述佈線密度改良中具有若干重要性。堆積層203之厚度容後詳述。
如於圖2D中觀察，堆積層203固化，從許可晶粒204加壓附著的軟化態過渡成適合在封裝結構成品耐久的硬化態。取決於用於堆積層203的材料，固化可使用光照進行及/或施用較高溫進行。
如於圖2E中觀察，堆積層203固化之後，模塑化合物或更通稱「模具」208施用至晶粒204及已固化堆積層203之暴露區上方。模塑製程之部件包括形成一實質上平坦的模具表面。模具208可透過壓縮模製、轉印模製、注入模製中之任一者施用。模具208物質可以是經高度填補的熱固性 環氧樹脂。於一實施例中，模具係於較高溫以實質上液相施用。已固化堆積層203須具有熔點/或玻璃轉換溫度，其係高於模具208形成於已固化堆積層203上方之溫度。
模具208之厚度須足夠遮蓋晶粒204的最厚的部分。此處，雖然附圖顯示具有相等厚度的多個晶粒204，但須瞭解各種晶粒204將具有實質上不等厚度(例如，晶粒中之二或多者係自不同製程製造)。模具容易調整其形式適應不同晶粒厚度而仍然被成形而產生實質上平坦表面。
如於圖2F中觀察，黏著層202被移除藉此卸除載體201，而留下整體結構具有堆積層203作為一個外平坦表面，而模具208作為另一個外平坦表面。整體結構經翻轉，讓堆積層203表面面向上以支援隨後金屬化及佈線過程。
用以崩解黏著層202使得整體結構能夠脫離載體201的製程可經熱誘生(例如，回應於升溫，黏著層202將結構崩解或改變成液相)，經化學誘生(例如，黏著層202與載體有化學鍵，而藉由誘生化學鍵被釋放的化學製程可出現離層)，經機械誘生(例如，黏著層202為脆性而可從載體裂縫，例如藉在載體表面誘生翹曲)，及/或經光誘生(例如，可使得黏著層202之結構性質改變，例如通過一透明載體，回應於照光而自固相轉變成液相)。於一實施例中，在金屬化製程開始之前，黏著層202之剩餘部分自堆積層203表面去除(例如，透過施用壓縮空氣至原先接觸載體的堆積層表面)。
如同，如同圖2F，堆積層203之實質上平坦化表面面向上準備用於金屬化製程。
如於圖2G中觀察，通孔開口210形成於晶粒204的襯墊205上方的堆積層203內(例如，藉由使用遮罩的雷射燒蝕、光阻劑施用/製作圖樣/蝕刻、或雷射束鑽孔)。容後詳述，通孔開口210的尺寸小，許可更高密度的佈線。
如於圖2H中觀察，一金屬化211層施用至堆積層203表面。金屬化211可藉沈積處理施用，諸如濺鍍、鍍覆、及印刷。可用以形成金屬化層211的其它類型的製程包括膏印、燒結、噴墨印刷。金屬化層典型地包括鋁、鎳、銀、金、及銅中之至少一者。
如於圖2I中觀察，金屬化211係經製作圖樣(例如，藉光阻劑施用/製作圖樣/蝕刻)以形成佈線212及連接塊213。值得注意地多個佈線212可形成於連接塊213間。此處，於一實施例中，晶粒襯墊之最小間隔217為15微米。具有3/3微米線寬的至多7導線可配置於具有55微米節距的焊料球216/連接塊213間。下表顯示額外實施例及相對於圖1A、B之先前技術辦法的比較。
要緊地，在同一個晶粒上的寬襯墊205可隔開217由晶粒製程許可的最小距離。如此導致在同一個晶粒上形成的連接塊213也係以其間之最小間距形成。
如於圖2J中觀察，在佈線層已經製作圖樣之後，一介電層215形成於金屬化211上方。介電層215係在連接塊213上方製作圖樣而在介電層215中形成開口而暴露出連接塊213。焊料球或C4球216然後形成於暴露的連接塊213上。作為一選擇性製程，封裝體隨後經密封(例如，使用一蓋氣 密式密封封裝體內部)。
參考圖2G至圖2J，注意堆積層203允許小型通孔開口210形成於晶粒204上的寬襯墊205上方。比起於圖1先前技術辦法中觀察的連接塊113，小型通孔開口210又轉而提供遠更小型連接塊213的形成。更小型連接塊213留下額外平坦空間，於該處可堆積更多導線212，即便如前文討論，在同一顆晶粒上的寬襯墊隔開由晶粒製程許可的最小距離217，及連接塊213也相對應地間隔一最小距離配置亦復如此。
至於堆積層203之厚度，於低端，堆積層203須大於晶粒204表面之最大翹曲裕度，使得當被加壓入堆積層203內時，保證堆積層203覆蓋晶粒204表面。舉例言之，若晶粒204可具有高達1-2微米之垂直翹曲度(亦即在一晶粒表面上的兩點間具有多達1-2微米的垂直位移)，堆積層之厚度須大於1-2微米。
於高端，通孔開口210形成之動力學須連同電流被汲取通過任何通孔的最惡劣情況一起考慮。概略言之，通孔開口210的形狀為圓錐形或錐狀(換言之，移動更深入通孔開口，通孔開口直徑連續縮小)。如此，通常，通孔的最小寬度係在與襯墊205的接觸點。若該寬度過小不足以讓足量電流汲取通過襯墊及通孔，則將導致電氣故障。因此，堆積層之厚度不應超過通孔底部對欲通過其中汲取的電流量而言為太窄的厚度。
注意在被封裝之前，當在晶粒上進行測試期間， 襯墊205可能出現來自於先前接觸襯墊的探針帶來的若干傷痕。
圖2K顯示於正交於圖2J之描繪方向的橫剖面圖，顯示佈線線跡212與襯墊205之互連。經由此種互連，同一個晶粒之襯墊或不同晶粒之襯墊可透過佈線線跡212連結。
圖3顯示安裝於平坦板320的完整封裝310。雖然先前各圖在所描繪的剖面圖中只描繪兩個晶粒，但須瞭解封裝310內部可罩住多於一個晶粒。值得注意地，不同晶粒可包括相同晶粒的不同情況(例如，兩個相同設計的記憶體晶片)及/或不同晶粒的不同情況(例如，一個單晶片系統晶粒及一個動態隨機存取記憶體晶粒)。以不同晶粒的不同情況為例，不同晶粒可根據不同製造程序技術製造(例如，高密度邏輯、快閃記憶體、動態隨機存取記憶體、相變記憶體及交換器)。
平坦板320及安裝的封裝310可整合成為任何更大型計算系統330，諸如手持式裝置(例如，智慧型電話)、平板電腦、膝上型電腦、桌上型電腦或伺服器電腦。同理，平坦板320及安裝的封裝310可整合成為其它類型的電子設備，諸如網路路由器、網路交換器、智慧型裝置(例如，智慧型手錶、智慧型眼鏡等)。
於前文說明書中，已經參考其特定具體實施例描述本發明。但顯然可不背離如隨附之申請專利範圍陳述之本發明的廣義精髓及範圍而於其中做出各種修改及變更。 據此，說明書及附圖須視為例示性意義而非限制性意義。
203‧‧‧堆積層
205‧‧‧襯墊
211‧‧‧金屬化
213‧‧‧連接塊
215‧‧‧介電層
216‧‧‧焊料球
217‧‧‧最小距離

Claims (16)

  1. 一種用於形成半導體封裝的方法，其包含下列步驟：在一載體之一黏著層上形成一堆積層；將多於一個的半導體晶粒壓入至該堆積層內，該等半導體晶粒各已經歷功能測試且具有用於輔助該測試的數個寬襯墊，其中，在同一個晶粒上的該等寬襯墊中之至少幾者係以由該晶粒之製程所容許的一最小距離間隔開；在該等半導體晶粒上方形成一模塑化合物；在形成該模塑化合物之後硬化該堆積層；將該堆積層自該載體卸下；移除該堆積層之在該等寬襯墊中之至少幾者上方的一部分以形成在該等寬襯墊中之該等至少幾者上方的通孔開口；在該堆積層上形成一金屬化層，該金屬化層實質上填補該等通孔開口；以及圖樣化該金屬化層以在經填補的該等通孔開口上方形成連接塊及在該等寬襯墊中之該等至少幾者個別的連接塊之間的多於一根的導線。
  2. 如請求項1之方法，其進一步包含下列步驟：在加壓之步驟之後提升在該等半導體晶粒及該堆積層周圍的氣壓，以更佳地填補在該等晶粒表面上之該等晶粒之襯墊所在的凹陷區域內之空隙。
  3. 如請求項1之方法，其中，該等寬襯墊各寬約40微米。
  4. 如請求項1之方法，其進一步包含下列步驟：在該等連接塊上形成焊料球或C4球。
  5. 如請求項1之方法，其中，移除該堆積層之該部份的步驟包括對雷射的使用。
  6. 一種封裝設備，其包含：一堆積層，多個晶粒之襯墊側被壓入該堆積層之一底側內，該等多個晶粒具有用於輔助該等多個晶粒之晶圓上測試的數個寬襯墊，該等寬襯墊以用來製造該等晶粒的個別製程所許可的最小距離間隔開，該堆積層之在該等寬襯墊上方之一部份被移除；以及在該堆積層之一頂側上的金屬化物，該金屬化物實質上填補在該等寬襯墊上方的區域，該金屬化物包括在該等寬襯墊上方的數個連接塊及在該等寬襯墊之間的多條導線，其中，該金屬化物之接觸該等寬襯墊的一底區域具有足以耐受流經該等寬襯墊之最大額定電流的寬度。
  7. 如請求項6之設備，其中，該等寬襯墊在與該堆積層及該金屬化物一起被封裝之前具有來自對該等晶粒之測試的傷痕。
  8. 如請求項6之設備，其中，該堆積層之厚度在環繞該等區域沿著該堆積層之側壁錐形傾斜這方面可供應該寬度。
  9. 如請求項6之設備，其中，該堆積層係選自於由下列所 組成之組群：聚醯亞胺；環氧樹脂；丙烯酸系；一低k材料；聚矽氧；以及聚苯并噁唑(PBO)。
  10. 如請求項6之設備，其進一步包含：形成於該堆積層及該金屬化物上方的介電質。
  11. 如請求項10之設備，其進一步包含：在該介電質內形成於該等連接塊上方的開口，以及形成於該等連接塊上的焊料球或C4球。
  12. 一種晶片系統，其包含：一平坦板；固定至該平坦板的一多晶片模組，該多晶片模組包含：一堆積層，多個晶粒之襯墊側被壓入該堆積層之一底側內，該等多個晶粒具有用於輔助該等多個晶粒之晶圓上測試的數個寬襯墊，該等寬襯墊以由用來製造該等晶粒的個別製程所許可的最小距離間隔開，該堆積層之在該等寬襯墊上方的一部分被移除；在該堆積層之一頂側上的金屬化物，該金屬化物實質上填補該等寬襯墊上方之區域，該金屬化物 包括在該等寬襯墊上方的數個連接塊及在該等寬襯墊之間的多條導線，其中，該金屬化物之接觸該等寬襯墊的一底區域具有足以耐受流經該等寬襯墊之最大額定電流的寬度。
  13. 如請求項12之系統，其中，該等寬襯墊在與該堆積層及該金屬化物一起被封裝之前具有來自對該等晶粒之測試的傷痕。
  14. 如請求項12之系統，其中，該系統為一計算系統。
  15. 如請求項14之系統，其中，該計算系統係下列中之任一者：一智慧型裝置；一智慧型電話；一平板電腦；一膝上型電腦；一桌上型電腦；以及一伺服器電腦。
  16. 如請求項12之系統，其中，該系統為網路系統。
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