TWI758072B - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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TWI758072B
TWI758072B TW110101712A TW110101712A TWI758072B TW I758072 B TWI758072 B TW I758072B TW 110101712 A TW110101712 A TW 110101712A TW 110101712 A TW110101712 A TW 110101712A TW I758072 B TWI758072 B TW I758072B
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Taiwan
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layers
forming
redistribution
dielectric
package
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TW110101712A
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TW202201578A (zh
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鄧博元
余振華
蔡豪益
潘國龍
郭庭豪
賴昱嘉
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台灣積體電路製造股份有限公司
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Abstract

一種形成封裝的方法包含形成多個介電層，製程包含： 形成具有第一厚度的第一多個介電層；以及形成具有小於第一厚度的第二厚度的第二多個介電層。第一多個介電層及第二多個介電層交替地佈置。方法更包含形成連接以形成導電路徑的多個重佈線路，製程包含：形成第一多個重佈線路，第一多個重佈線路各自為第一多個介電層中的一者；以及形成第二多個重佈線路，第二多個重佈線路各自為第二多個介電層中的一者。

Description

封裝及其形成方法
本發明的實施例是有關於一種半導體封裝及其形成方法，且特別是關於一種具有交替堆疊的厚重佈線路及薄重佈線路的半導體封裝及其形成方法。
隨著半導體技術的發展，一些半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中，此亦使得其他半導體晶粒及所得封裝變得愈來愈大。
重佈線路(redistribution line)形成於封裝基底中以用於在封裝中路由功率及訊號。隨著封裝變得愈來愈大以容納諸如人工智慧(Artificial Intelligence；AI)應用的更多功能，重佈線路變得極長，有時長達數十毫米。長的重佈線路具有較高電阻值且導致大量插入損耗(insertion loss)，尤其是對於高速訊號來說。
根據一些實施例，一種形成封裝的方法包括形成多個介電層以及形成連接以形成導電路徑的多個重佈線路。形成多個介電層包括形成具有第一厚度的第一多個介電層及形成具有小於所述第一厚度的第二厚度的第二多個介電層，其中所述第一多個介 電層及所述第二多個介電層交替地佈置。形成所述多個重佈線路包括形成第一多個重佈線路，所述第一多個重佈線路各自為所述第一多個介電層中的一者及形成第二多個重佈線路，所述第二多個重佈線路各自為所述第二多個介電層中的一者。
根據一些實施例，一種形成封裝的方法包括形成多個聚合物層、形成多個模製化合物層、形成第一多個重佈線層及形成第二多個重佈線層。所述多個聚合物層及所述多個模製化合物層交替地配置，其中所述多個模製化合物層中的每一者藉由製程形成，所述製程包括施配模製化合物及執行平坦化製程以使所述模製化合物的頂面水平。所述第一多個重佈線層各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層。所述第二多個重佈線層各自在所述多個模製化合物層中的一者中，其中所述第二多個重佈線層為水平佈線層。
根據一些實施例，一種封裝包括多個聚合物層、多個模製化合物層、第一多個重佈線層及第二多個重佈線層。所述多個聚合物層具有第一厚度，所述多個聚合物層及所述多個模製化合物層交替地安置，其中所述多個模製化合物層具有大於所述第一厚度的第二厚度，各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層，各自在所述多個模製化合物層中的一者中，其中所述第二多個重佈線層為水平佈線層。
20:載體
22:離型膜
24:介電緩衝層
26、40、46、46L、56、60、60L、66、66B、78、82、106A、110A:重佈線路
26A、40A、46A、66A:金屬晶種層
26B、40B、46B:電鍍金屬區
28、34:電鍍罩幕
30、36、44、92、109:開口
32、46V、50、60V、62:通孔
38、42、52、58、64:介電層
38A:基材
38B:球形顆粒
47:虛線
67:內連線結構
68:金屬柱
70:晶粒貼合膜
72、84、72A:封裝元件
72B:IVR晶粒
72C:IPD晶粒
74:密封體
75:重佈線結構
76、80:層
84A、84C:SoC封裝
84B:HBM
85:焊料區
87:底部填充物
88:膠帶
90:框架
94:電連接件
96:插座
97:區域
98:連接件
100:重構晶圓
100'、102:封裝
106A'、108A':較長RDL
106B、108、108B、110B:虛設接墊
108A:金屬接墊
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236:製程
thick-1、thick-2:厚RDL層
thin-1:薄RDL層
H1、H2:高度
L1、L2:平均長度
T1、T2、T3、T4:厚度
α、β:傾斜角
當結合隨附圖式閱讀以下具體描述時將最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按 比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1至圖22示出根據一些實施例的在封裝的形成中的中間階段的剖視圖。
圖23示出根據一些實施例的相鄰厚RDL及薄RDL的實例佈局的平面視圖。
圖24及圖25示出根據一些實施例的一些封裝的剖視圖。
圖26示出根據一些實施例的在封裝中的區域的放大視圖。
圖27示出根據一些實施例的用於形成封裝的製程流程。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述元件及配置的具體實例以簡化本揭露內容。當然，此等實例僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或在第二特徵上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例，亦可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及明晰的目的且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為易於描述，可在本文中使用例如「在......之下」、「在......下方」、「下部」、「上覆」、「上部」以及類似物的空間相對術語，以描述如圖中所示出的一個部件或特徵與另一部件或特徵的關係除了圖中描繪的定向以外，空間相對術語亦意欲涵蓋元件 在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)且本文中使用的空間相對描述詞可同樣相應地進行解釋。
根據一些實施例，提供一種具有與薄介電層及薄重佈線路(Redistribution Line；RDL)交替地佈置的厚介電層及厚重佈線路的封裝及其形成方法。亦示出形成製程中的中間階段。本文中所論述的實施例將提供使得能夠製造或使用本揭露內容的主題的實例且所屬技術領域中具有通常知識者將易於理解可在保持於不同實施例的所涵蓋範圍內的同時進行的修改。在各種視圖及示出性實施例中，相同附圖標號用以指明相同部件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖22示出根據一些實施例的在封裝的形成中的中間階段的剖視圖。如圖27中所繪示的製程流程200中亦示意性地反映對應的製程。參考圖1，設置載體20且將離型膜22塗佈於載體20上。載體20由透明材料形成且可為玻璃載體、陶瓷載體、有機載體或類似者。離型膜22與載體20的頂面實體接觸。離型膜22可由光熱轉換(Light-To-Heat-Conversion；LTHC)塗佈材料形成，所述材料經由塗佈施加於載體20上。根據本揭露內容的一些實施例，LTHC塗佈材料能夠在光/輻射(諸如雷射)的熱能下分解，因此可自形成於其上的結構剝離載體20。根據一些實施例，如亦在圖1中所繪示，介電緩衝層24形成於LTHC塗佈材料22上。根據一些實施例，介電緩衝層24由聚合物類材料形成。舉例而言，介電緩衝層24可由聚苯并噁唑(polybenzoxazole；PBO)、 聚醯亞胺(polyimide)、苯環丁烷(benzocyclobutene；BCB)或其他可適用聚合物形成。
圖2及圖3示出介電緩衝層24上的重佈線路(RDL)26的形成中的製程的部分。各別的製程在圖27中所繪示的製程流程200中示出為製程202。參考圖2，形成金屬晶種層26A。根據一些實施例，金屬晶種層26A形成為毯覆層，所述毯覆層可包含黏著層及含銅層。黏著層可由鈦、氮化鈦、鉭、氮化鉭或類似者形成。含銅層可由實質上純淨的銅或銅合金形成。金屬晶種層26A的形成方法可包含物理氣相沉積(Physical Vapor Deposition；PVD)、電漿增強化學氣相沉積(Plasma Enhance Chemical Vapor Deposition；PECVD)、原子層沉積(Atomic Layer deposition；ALD)或類似者。可由光阻或另一可適用材料形成的圖案化電鍍罩幕28隨後形成於金屬晶種層26A上方。形成開口30以暴露金屬晶種層26A的一些部分。接著，金屬區(RDL)26B例如經由電化學電鍍形成於開口30中。RDL 26B可由銅或銅合金、鋁、鎳、鈀、其合金或其多個層形成。在RDL 26B的形成之後，移除電鍍罩幕28，從而暴露出下面的金屬晶種層26A的部分。圖3中繪示所得結構。
圖4至圖6示出根據本揭露內容的一些實施例的在通孔32的形成中的中間階段的剖視圖。各別的製程在圖27中所繪示的製程流程200中示出為製程204。通孔32的形成可共用相同金屬晶種層26A或可使用另一金屬晶種層執行。當待使用另一金屬晶種層時，蝕刻未由電鍍RDL 26B覆蓋的金屬晶種層26A的被暴露出的部分，接著形成另一金屬晶種層(未繪示)，其形成方法及材料可由圖2中所繪示的金屬晶種層26A的候選方法及候選材料的 相同群組中選出。新形成的金屬晶種層覆蓋RDL 26B的頂面及側壁且在介電緩衝層24的頂面上延伸。
圖4示出金屬晶種層26A未經蝕刻且用作用於形成通孔的金屬晶種層的實施例。形成可由光阻形成的圖案化電鍍罩幕34，其中開口36形成於電鍍罩幕34中且交疊RDL 26的一些部分。
接著，如圖5中所繪示，通孔32例如經由電鍍形成於開口36中。通孔32可由銅、鎳、其合金或類似者形成。通孔32及RDL 26B可由相同材料或不同材料形成且通孔32與RDL 26B之間的界面可為或可不為可區分的。在通孔32的形成之後，移除電鍍罩幕34，從而暴露RDL 26B及下面的金屬晶種層26A的部分。接著，蝕刻金屬晶種層26A的被暴露出的部分且剩餘部分亦標示為26A。在圖6中繪示所得結構。將金屬晶種層26A的剩餘部分視為RDL的部分，下文中將RDL 26B及金屬晶種層26A的剩餘部分統稱為RDL 26。歸因於電鍍製程，通孔32的邊緣為實質上豎直且筆直的，例如具有在約85度與90度之間的範圍內且可在約88度與90度之間的範圍內的傾斜角α。
參考圖7，形成介電層38以將RDL 26及通孔32兩者密封於其中。各別的製程在圖27中所繪示的製程流程200中示出為製程206。將介電層38填充至高於通孔32的頂面的水平面，隨後固化。根據一些實施例，介電層38包括或為模製化合物、模製底部填充物、環氧樹脂及/或樹脂。如所施配的介電層38的頂面高於通孔的頂端。當由模製化合物或模製底部填充物形成時，介電層38可包含基材及基材中的填料顆粒(未繪示，參考圖26)，所述基材可為聚合物、樹脂、環氧樹脂或類似者。填料顆粒可為SiO2、 Al2O3、矽石(silica)或類似者的介電顆粒且可具有球形形狀。另外，球形填料顆粒可具有多個不同直徑。由於介電層38可包含諸如基材及填料顆粒的不同材料，故將介電層38稱為由異質材料形成。
根據替代性實施例，介電層38由同質材料形成。同質材料可為感光性材料或非感光性材料。舉例而言，同質材料可為或包括PBO、聚醯亞胺、樹脂、環氧樹脂或類似者。形成製程可包含施配呈可流動形式的同質介電層38且固化介電層38。介電層38亦可由諸如氧化矽、氮化矽或類似者的無機材料形成，所述無機材料可藉由化學氣相沉積(Chemical Vapor Deposition；CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)或類似者形成。
在後續製程中，如圖8中所繪示，執行諸如化學機械研磨(Chemical Mechanical Polish；CMP)製程或機械研磨(grinding)製程的平坦化製程以使介電層38平坦化，直至暴露出通孔32。歸因於平坦化製程，通孔32的頂端與介電層38的頂面實質上齊平(共面)。
圖9示出可包含金屬晶種層40A及電鍍金屬區(RDL)40B的RDL 40的形成。各別的製程在圖27中所繪示的製程流程200中示出為製程208。根據本揭露內容的一些實施例，RDL 40的形成可包含沉積毯覆金屬晶種層、在毯覆金屬晶種層上方形成圖案化電鍍罩幕、電鍍金屬區40B、移除電鍍罩幕以及蝕刻金屬晶種層的被暴露出的部分。RDL 40的材料可由用於形成RDL 26的候選材料的相同群組中選出且不在本文中重複。
圖10示出介電層42的塗佈及圖案化。各別的製程在圖27中所繪示的製程流程200中示出為製程210。根據一些實施例，介電層42由感光性材料形成或包括感光性材料及/或可由聚合物形成或包括聚合物，所述聚合物由聚醯亞胺、PBO或類似者形成或包括聚醯亞胺、PBO或類似者。介電層42可呈可流動形式施配且隨後固化。歸因於塗佈製程，可不用執行用以使介電層42的頂面平坦化的平坦化製程。因此，介電層42為整體平面的，並且位於RDL 40正上方的介電層42的部分的頂面可略微高於RDL 40旁邊的介電層42的部分的頂面。形成製程包含塗佈介電層42、對介電層42執行曝光製程(例如使用經圖案化微影罩幕)以及使介電層42顯影。在顯影製程中移除介電層42的一些部分以形成開口44。歸因於形成製程，開口44的邊緣可為傾斜且筆直的。
參考圖11，沉積金屬晶種層46A且在金屬晶種層46A上電鍍金屬區46B。各別的製程在圖27中所繪示的製程流程200中示出為製程212。金屬晶種層26A延伸至開口44(圖10)中。經圖案化電鍍罩幕(未繪示)隨後形成於金屬晶種層46A上方且在經圖案化電鍍罩幕中的開口中電鍍金屬區46B。隨後例如經由灰化製程移除電鍍罩幕。先前由電鍍罩幕覆蓋的金屬晶種層46A的部分可保留作為用於在其上形成通孔的金屬晶種層，或可在此時經蝕刻。電鍍金屬區46B的材料可由用於形成電鍍金屬區26B的候選材料的相同群組中選出且不在本文中重複。
圖12示出通孔50的形成，所述通孔50可使用金屬晶種層46A作為其晶種層來電鍍，或可藉由使用單獨金屬晶種層形成。各別的製程在圖27中所繪示的製程流程200中示出為製程 214。根據一些實施例，用於形成通孔50的形成製程包含形成經圖案化電鍍罩幕(未繪示)、電鍍通孔50、移除電鍍罩幕以及蝕刻金屬晶種層(金屬晶種層46A或另外形成的金屬晶種層)的被暴露出的部分。通孔50的材料可由用於形成通孔32的候選材料(諸如銅、鎳或其合金)的相同群組中選出，因此不在本文中重複。通孔50及電鍍金屬區46B可由相同材料或不同材料形成且通孔50與電鍍金屬區46B之間的界面可為或可不為可區分的。在描述中，電鍍金屬區46B(圖11)及金屬晶種層46A的剩餘部分統稱為RDL 46。
如圖12中所繪示，RDL 46包含介電層42上方的線路部分46L及延伸至介電層42中的通孔部分46V。根據本揭露內容的一些實施例，位於通孔46V正上方的RDL 46的頂面的一些部分可因由開口44引起的拓撲(topology)而凹陷。根據一些實例實施例，由虛線47示出RDL 46的凹陷頂面。根據其他實施例，調整電鍍製程，使得位於通孔部分46V正上方的線路部分46L的頂面為平面的或甚至高於交疊介電層42的線路部分46L的部分的頂面。歸因於形成製程，通孔46V的邊緣為傾斜的，例如具有小於約85度或小於約80度或約75度的傾斜角β。
如圖10及圖11中所繪示，由於介電層42可由同質材料形成，故使介電層42(如圖10中所繪示)圖案化以形成開口44為可能的。線路部分46L及通孔部分46V因此可在同一製程中形成。作為比較，由於介電層38可為異質的，其中的基材及填料顆粒具有不同蝕刻速率，故難以蝕刻介電層38。因此，通孔32及RDL 40可形成於單獨的製程中，而引起製造成本增加。然而，由 於能夠調整介電層38的厚度以具有期望值的優點來補償所增加的成本，所述期望值可大於15微米，並可在約150微米與約80微米之間的範圍內。作為比較，當介電層42由感光性材料形成時，由於曝光的限制，介電層42的厚度受限於例如小於約15微米。
接著，亦如在圖中12所繪示，形成介電層52以將RDL線路部分46L及通孔50密封於其中。各別的製程在圖27中所繪示的製程流程200中示出為製程216。介電層52可由自用於形成介電層38的相同候選材料中選出的材料形成，並可由模製化合物、模製底部填充物、環氧樹脂、樹脂、無機介電材料或類似者形成或包括模製化合物、模製底部填充物、環氧樹脂、樹脂、無機介電材料或類似者。隨後執行諸如CMP製程或機械研磨製程的平坦化製程以使介電層52平坦化，直至暴露出通孔50。各別的製程亦在圖27中所繪示的製程流程200中示出為製程216。歸因於平坦化製程，通孔50的頂端與介電層52的頂面齊平(共面)或與介電層52的頂面實質上齊平。
圖13示出包含RDL 56及RDL 60、通孔62以及介電層58及介電層64的更多上覆特徵的形成。各別的製程在圖27中所繪示的製程流程200中示出為製程218。由省略號表示的上覆層中的一些可表示類似於包含介電層42及介電層52以及導電特徵40、導電特徵46以及導電特徵50的結構的分層結構。上覆結構中的導電特徵亦可採用RDL 40及RDL 46以及通孔50的結構。
根據一些實施例，介電層38、介電層42、介電層52、介電層58以及介電層64以及介電層52與介電層58之間的介電層共同採用交替佈局，其中層中的一些由同質材料形成且因具有厚 度T2而更薄，其他層由異質材料形成且因具有厚度T1而更厚，厚度T1大於厚度T2。由同質材料形成的每一層可插設於由異質材料形成的兩個層之間並接觸所述兩個層，並且由異質材料形成的每一層可插設於由同質材料形成的兩個層之間並接觸所述兩個層。舉例而言，層42及層58可由同質材料形成，而層38、層52及層64可由異質材料形成。介電層38、介電層52及介電層64可由與介電層42及介電層58相同的材料或不同的材料形成。舉例而言，介電層38、介電層42、介電層52、介電層58及介電層64可均由模製化合物或模製底部填充物形成或包括模製化合物或模製底部填充物，或均由聚醯亞胺、PBO或類似者形成。做為另一種選擇，介電層38、介電層52及介電層64可由模製化合物、模製底部填充物或類似者形成，而介電層42及介電層58可由PBO、聚醯亞胺或類似者形成。
根據一些實施例，比例T1/T2(其為更厚的介電層的厚度與更薄的介電層的厚度的比例)大於約1.5，並且可在約1.5與10之間的範圍內，可進一步在約2與5之間的範圍內。舉例而言，更厚的介電層38、更厚的介電層52及更厚的介電層64等的厚度T1可在約10微米與約80微米之間的範圍內，更薄的介電層24、更薄的介電層42及更薄的介電層58的厚度T2可在約4微米與約25微米之間的範圍內。
更厚的介電層38、更厚的介電層52及更厚的介電層64中的RDL(如RDL 26、RDL 46L及RDL 60L)的厚度T3大於更薄的介電層(如更薄的介電層42及更薄的介電層58)中的RDL(如RDL 40及RDL 56)的厚度T4。根據一些實施例，比例T3/T4 大於約1.5，並且可在約1.5與約10之間的範圍內，可進一步在約2與5之間的範圍內。舉例而言，厚度T3可在約5微米與約40微米之間的範圍內，厚度T4可在約1微米與約10微米之間的範圍內。在本文中，處於相同水平面處的所有重佈線路及虛設金屬接墊統稱為重佈線層或RDL層。
此外，更厚的介電層38、更厚的介電層52及更厚的介電層64中的通孔(如通孔32、通孔50以及通孔62)的高度H1大於更薄的介電層(如更薄的介電層42及更薄的介電層58)中的通孔(如通孔46V及通孔60V)的厚度H2。根據一些實施例，比例H1/H2大於約1.5且可在約1.5與約10之間的範圍內，可進一步在約2與5之間的範圍內。舉例而言，高度H1可在約5微米與約40微米之間的範圍內，高度H2可在約3微米與約15微米之間的範圍內。
在本文中，離型膜22上方的特徵統稱為內連線結構67。根據一些實施例，執行探測製程(probing process)以探測內連線結構67的功能。內連線結構67包含多個相同部件(晶粒)，所述多個相同部件可在後續製程中彼此鋸切開(圖21)。可例如使用探針卡測試此等晶粒且量測內連線結構67中的電連接以判定晶粒是否有缺陷。有缺陷的晶粒不用於後續接合製程，並且沒有元件晶粒會被直接置放於有缺陷的晶粒上。
圖14及圖15示出RDL 66(其亦為金屬接墊)及金屬柱68在內連線結構67上方且電連接至內連線結構67的形成。各別的製程在圖27中所繪示的製程流程200中示出為製程220。製程可包含沉積金屬晶種層66A、形成第一電鍍罩幕(未繪示)以電 鍍RDL 66B、移除第一電鍍罩幕、形成第二電鍍罩幕(未繪示)、電鍍金屬柱68、移除第二電鍍罩幕以及剝離未被RDL 66B覆蓋的金屬晶種層66A的部分。電鍍RDL 66B及金屬晶種層66A的剩餘部分在下文中統稱為RDL 66，其繪示於圖15中。
接著，參考圖16，將封裝元件72例如經由晶粒貼合膜70(黏著膜)貼合至介電層64。各別的製程在圖27中所繪示的製程流程200中示出為製程222。所示出的封裝元件72表示例如像圖24及圖25中所繪示的多個封裝元件。經接合的封裝元件包含但不限於橋接晶粒、邏輯晶粒、被動元件、積體電壓調節器(Integrated Voltage Regulator；IVR)以及類似者。橋接晶粒可使兩個或大於兩個封裝元件84(圖22)進行內連。被動元件可為可包含電容器、電感器、電阻器及/或類似者的整合式被動元件(Integrated Passive Device；IPD)且可為元件晶粒或包含元件晶粒的封裝。
接著，亦如在圖16中所繪示，施配密封體74且隨後固化以將金屬柱68及封裝元件72密封於其中。各別的製程在圖27中所繪示的製程流程200中示出為製程224。密封體74可包含模製化合物、模製底部填充物、樹脂、環氧樹脂及/或類似者。根據一些實施例，密封體74包含諸如聚合物、環氧樹脂、樹脂或類似者的基材，以及基材中的填料顆粒。
參考圖17，在密封體74的施配及固化之後，執行諸如CMP製程或機械研磨製程的平坦化製程以移除過量材料，直至暴露出封裝元件72的金屬柱68及表面導電特徵(如金屬柱)。下文中將金屬柱68替代地稱為穿孔。
圖18示出重佈線結構75的形成，所述重佈線結構75包含如層76及層80的多個介電層以及如RDL 78及RDL 82的多個RDL。各別的製程在圖27中所繪示的製程流程200中示出為製程226。根據一些實施例，使用類似於用於形成介電層42及RDL 46的方法的方法來形成重佈線結構75中的所有介電層及RDL。根據替代性實施例，重佈線結構75亦採用具有更厚的介電層及更薄的介電層(及對應更厚及更薄重佈線路)的交替佈局。金屬凸塊可形成於RDL 82上。
參考圖19，經由焊料區85將封裝元件84接合至重佈線結構75。各別的製程在圖27中所繪示的製程流程200中示出為製程228。隨後施配及固化底部填充物87。所示出的封裝元件84表示如圖24及圖25中所繪示的多個封裝元件。舉例而言，經接合的封裝元件包含但不限於含核心的元件封裝(如系統晶片(System-on-Chip；SoC)封裝)、記憶體晶粒或記憶體封裝(如高頻寬記憶體(High-Bandwidth Memory；HBM)立方體)及類似者。根據本揭露內容的一些實施例，SoC封裝中的每一者包含接合在一起以形成系統的單一元件晶粒或多個元件晶粒。SoC封裝中的元件晶粒可包含核心元件晶粒，如中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒、特殊應用積體電路(Application Specific Integrated Circuit；ASIC)晶粒、現場可程式化閘陣列(Field Programmable Gate Array；FPGA)晶粒或類似者或其組合。記憶體封裝可包含堆疊記憶體晶粒，如動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒、靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒、磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory；MRAM)晶粒、電阻式隨機存取記憶體(Resistive Random Access Memory；RRAM)晶粒或其他類型的記憶體晶粒。在本文中，將離型膜22上方的結構稱為重構晶圓(reconstructed wafer)100。
接著，參考圖20，將重構晶圓100置放於貼合至框架90的膠帶88上。根據本揭露內容的一些實施例，封裝元件84與膠帶88接觸。接著，藉由將光投影於LTHC塗佈材料22上自載體20剝離重構晶圓100(圖19)。各別的製程在圖27中所繪示的製程流程200中示出為製程230。由於經受曝光(如雷射掃描)而使離型膜22分解，使得載體20可自緩衝介電層24脫離，因此自載體20剝離(卸下)重構晶圓100。
參考圖21，開口92形成於介電緩衝層24中，因此暴露RDL 26。根據本揭露內容的一些實施例，經由雷射鑽孔形成開口92。各別的製程在圖27中所繪示的製程流程200中示出為製程232。可將預焊料區(未繪示)塗敷於RDL 26的被暴露出的部分上。
接著，進一步參考圖21，執行單體化(晶粒鋸切)製程以將經重構晶圓100分成彼此相同的單體封裝100'。各別的製程在圖27中所繪示的製程流程200中示出為製程234。單體化可使用刀片執行或可使用雷射光束執行預開槽而形成凹槽，隨後使用刀片切開凹槽來執行。
圖22示出單體化封裝100'經由電連接件94與插座(socket)96及連接件98的接合，而形成封裝102。各別的製程在 圖27中所繪示的製程流程200中示出為製程236。插座96及連接件98可用於在封裝100'與外部元件之間提供功率及訊號路由。
圖23示出厚RDL(如圖22中的RDL 26、RDL 46L及RDL 60L)及薄RDL(如圖22中的RDL 40及RDL 56)的實例佈線方案及實例佈局。標記為thin-1的薄RDL層為同一層中所有薄RDL及虛設接墊的集合。標記為thick-1及thick2的厚RDL層中的每一者為同一層中所有厚RDL及虛設接墊的集合。薄RDL層thin-1包夾於厚RDL層thick-1與厚RDL層thick-2之間，其中厚RDL層thick-1可高於或低於厚RDL層thick-2。根據一些實施例，諸如thin-1的薄RDL層主要用於提供電磁界面(Electromagnetic Interface；EMI)屏蔽，以減小如層thick-1及層thick-2的不同佈線層之間的訊號路由線(routing line)的干擾。薄RDL層包含用於內連其上覆RDL層及之下RDL層中的路由線的金屬接墊。薄RDL層中的金屬接墊(如金屬接墊108A)較短，因此薄RDL層中的金屬接墊並不用於橫向佈線目的。虛設接墊(如虛設接墊108B)形成於薄RDL層中且可連接至用於EMI屏蔽的電接地。虛設接墊108可在其中包含開口109以減小圖案負載效應(loading effect)。
厚RDL層包含用於橫向佈線的金屬接墊及路由線。厚RDL層中的RDL長於薄RDL層中的金屬接墊/線。厚RDL層中的金屬接墊較厚，因此串列電阻(serial resistance)較低，使得厚RDL層中的RDL適於橫向佈線目的。虛設接墊(如虛設接墊106B及虛設接墊110B)亦形成於厚RDL層中，以進一步改良相鄰RDL之間的EMI屏蔽。虛設接墊106B及虛設接墊108B可電接地以用 於EMI屏蔽。虛設接墊106B及虛設接墊108B亦可在其中包含開口109以減小圖案負載效應。
根據一些實施例，假定厚RDL層中的RDL的平均長度為L1且薄RDL層中的RDL的平均長度為L2，則比例L1/L2大於1.0且可大於約50,000。比例L1/L2亦可在約1與約1,000之間的範圍內。另外，薄RDL層中的所有RDL線路及接墊可具有約300,000微米(300毫米)的最大長度。另一方面，厚RDL層中的RDL中的至少一些(可能是全部)長於薄RDL中的RDL的最大長度。厚RDL層中的RDL的長度可長於薄RDL中的RDL的最大長度2倍、5倍、10倍或100倍。因此，所有較長的橫向佈線(例如具有大於約300,000微米(300毫米)的距離)配置於厚RDL中。亦示出較長RDL 106A'及較長RDL 108A'以繪示分別由虛設金屬接墊106B及虛設金屬接墊108B彼此屏蔽的較長的路由線。
圖23示出實例傳送訊號/功率佈線方案。訊號或功率經由(厚RDL thick-1中的)RDL 106A橫向地傳導較長距離，隨後經由通孔(未繪示)傳導至薄RDL層thin-1中的金屬接墊108A。訊號或功率隨後經由另一通孔(未繪示)傳導至厚RDL層thick-2中的RDL 110A。金屬接墊108A用於RDL線路106A與RDL線路110A之間的內連，但並不用於橫向佈線。厚RDL層thick-2中的RDL 110A亦可較長。
圖22及圖23中所繪示的佈線方案可用於形成高速傳輸線(如差動傳輸電路(differential transmission line))且可用於大型封裝，其中傳輸線較長，因此插入損耗(insertion loss)較高。為了減少插入損耗，較佳地增加厚RDL中的傳輸線的線寬(例如 增加為大於約15微米或約20微米)，使得傳輸線的電阻可減小。然而，傳輸線的寬度增加導致傳輸線的阻抗不利地減小，從而導致封裝的不同零件之間的阻抗值不匹配。根據本揭露內容的一些實施例，傳輸線與相鄰薄RDL(EMI屏蔽)層中的一者之間的高度H1(圖22)增加，使得當厚RDL層中的傳輸線的線寬增加時，阻抗並不減小且可保持在期望值(例如100歐姆)。因此，使更厚的介電層及更薄的介電層交替不僅減少較長水平傳輸線的插入損耗，亦平衡保持傳輸線的阻抗的需求。
圖24示出根據一些實施例的封裝102，其中一些更多細節未在所示的圖22中繪示。根據一些實施例，經接合封裝元件84包含SoC封裝84A及SoC封裝84C及HBM 84B。封裝元件72A可為用於內連封裝元件84A及封裝元件84B且內連封裝元件84B及封裝元件84C的橋接晶粒。亦示出IVR晶粒72B及IPD晶粒72C。
圖25示出根據替代性實施例的封裝102。在此等實施例中，示出封裝元件84的多個群組，所述群組可各自經由內連線結構75及封裝元件72中的橋接晶粒進行內連。
圖26示出圖22中的區域97的放大視圖，所述放大視圖示出更厚的介電層38的部分、更薄的介電層42的部分及RDL 40的部分。如上所述，介電層38可包含諸如環氧樹脂、樹脂、聚合物或類似者的基材38A及球形顆粒38B。歸因於平坦化製程，一些球形顆粒38B的頂部部分可移除以形成部分顆粒(partial particle)，所述部分顆粒具有與基材38A的平面頂面共面的平面頂面。介電層42的底面接觸部分顆粒38B及基材38A的平面頂面。 另一方面，介電層42可由同質材料形成，其中並不包含顆粒。
在上文所示出的實施例中，根據本揭露內容的一些實施例論述一些製程及特徵以形成三維(three-dimensional；3D)封裝。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試接墊，所述基底允許對3D封裝或3DIC的測試、探針及/或探針卡的使用以及類似者。可對中間結構以及最終結構執行校驗測試。另外，本文中所揭露的結構及方法可與併入有對已知良好晶粒的中間驗證的測試方法結合使用，以提高良率且降低成本。
本揭露內容的實施例具有一些有利特徵。藉由減小薄介電層及薄RDL層的厚度，可增加RDL層(包含厚RDL及薄RDL層)的總數並改善路由能力。然而，由於所有介電層的總厚度並未增加，故所得的封裝及重構晶圓的翹曲並未增大。由於可在接合元件晶粒之前測試佈線層的功能，故對應製程的良率較高。
根據本揭露內容的一些實施例，一種方法包括：形成多個介電層，包括：形成具有第一厚度的第一多個介電層；形成具有小於所述第一厚度的第二厚度的第二多個介電層，其中所述第一多個介電層及所述第二多個介電層交替地佈置；以及形成連接以形成導電路徑的多個重佈線路，其中所述形成所述多個重佈線路包括：形成第一多個重佈線路，所述第一多個重佈線路各自為所述第一多個介電層中的一者；以及形成第二多個重佈線路，所述第二多個重佈線路各自為所述第二多個介電層中的一者。在實施例中，所述第一多個介電層由模製化合物形成，所述第二多個 介電層由感光性聚合物形成。在實施例中，所述方法更包括形成多個通孔，所述方法包括：施配所述第一多個介電層中的一者以嵌入所述多個通孔中的一者；以及對所述第一多個介電層中的所述一者及所述多個通孔中的所述一者執行平坦化製程。在實施例中，所述方法更包括形成多個通孔，所述多個通孔各自在所述第一多個介電層中的一者中，其中所述多個通孔中的每一者及所述第一多個重佈線路中的各別之下一者經電鍍以共用相同金屬晶種層。在實施例中，所述方法更包括在所述多個介電層中的頂部介電層上方形成金屬接墊；在所述金屬接墊上方且接觸所述金屬接墊形成金屬柱；將元件晶粒貼合至所述頂部介電層；以及密封所述金屬接墊、所述金屬柱以及所述元件晶粒。在實施例中，所述第一厚度與所述第二厚度的比例大於約1.5。在實施例中，所述第一多個重佈線路具有第三厚度，所述第二多個重佈線路具有小於所述第三厚度的第四厚度。在實施例中，所述第一多個介電層中的每一者包括基材及所述基材中的填料顆粒，所述第二多個介電層中的每一者由同質材料形成。
根據本揭露內容一些實施例，一種方法包括：形成多個聚合物層；形成多個模製化合物層，其中所述多個聚合物層及所述多個聚合物層交替地配置，其中所述多個模製化合物層中的每一者藉由製程形成，所述製程包括：施配模製化合物；以及執行平坦化製程以使所述模製化合物的頂面水平；形成第一多個重佈線層，所述第一多個重佈線層各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層；以及形成第二多個重佈線層，所述第二多個重佈線層各自在所述多個模製化合物 層中的一者中，其中所述第二多個重佈線層為水平佈線層。在實施例中，所述多個模製化合物層中的一者厚於所述多個聚合物層中的第一聚合物層及第二聚合物層兩者，其中所述第一聚合物層上覆且接觸所述多個模製化合物層中的所述一者，所述第二聚合物層在所述多個模製化合物層中的所述一者之下且接觸所述多個模製化合物層中的所述一者。在實施例中，所述多個聚合物層未藉由平坦化製程平坦化。在實施例中，所述封裝更包括形成多個通孔，所述多個通孔各自在所述多個模製化合物層中的一者中，其中所述多個通孔中的每一者及對應的之下重佈線路形成於單獨電鍍製程中。在實施例中，所述多個通孔中的每一者藉由對應平坦化製程平坦化。在實施例中，藉由共用相同金屬晶種層形成所述多個通孔中的每一者及第二多個重佈線層中的對應的之下一者。
根據本揭露內容的一些實施例，一種封裝包括，多個聚合物層，其中所述多個聚合物層具有第一厚度；多個模製化合物層，其中所述多個聚合物層及所述多個模製化合物層交替地安置，其中所述多個模製化合物層具有大於所述第一厚度的第二厚度；第一多個重佈線層，各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層；以及第二多個重佈線層，各自在所述多個模製化合物層中的一者中，其中所述第二多個重佈線層為水平佈線層。在實施例中，所述第一多個重佈線層薄於所述第二多個重佈線層。在實施例中，所述第一多個重佈線層包括具有最大長度的第一重佈線路且所述第二多個重佈線層包括長於所述最大長度的第二重佈線路。在實施例中，所述第一多 個重佈線層具有第三厚度且所述第二多個重佈線層具有大於所述第三厚度的第四厚度。在實施例中，所述第二厚度與所述第一厚度的比例大於約1.5。在實施例中，所述多個模製化合物層中的每一者包括基材及所述基材中的填料顆粒且所述多個聚合物層由同質材料形成。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可更佳地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236:製程

Claims (10)

  1. 一種形成封裝的方法，包括：形成多個介電層，包括：形成具有第一厚度的第一多個介電層；形成具有小於所述第一厚度的第二厚度的第二多個介電層，其中所述第一多個介電層及所述第二多個介電層交替地佈置；形成連接以形成導電路徑的多個重佈線路，其中所述形成所述多個重佈線路包括：形成第一多個重佈線路，所述第一多個重佈線路各自為所述第一多個介電層中的一者；以及形成第二多個重佈線路，所述第二多個重佈線路各自為所述第二多個介電層中的一者；在形成所述多個介電層及所述多個重佈線路之後，將元件晶粒的背側貼合至所述多個介電層中的頂部介電層；以及在所述頂部介電層上形成密封體以密封所述元件晶粒。
  2. 如請求項1所述之形成封裝的方法，其中所述第一多個介電層由模製化合物形成，所述第二多個介電層由感光性聚合物形成。
  3. 如請求項1所述之形成封裝的方法，更包括形成多個通孔，所述方法包括：施配所述第一多個介電層中的一者以嵌入所述多個通孔中的一者；以及對所述第一多個介電層中的所述一者及所述多個通孔中的所 述一者執行平坦化製程。
  4. 如請求項1所述之形成封裝的方法，更包括：在所述多個介電層中的所述頂部介電層上方形成金屬接墊；在所述金屬接墊上方且接觸所述金屬接墊形成金屬柱以及在所述密封體中密封所述金屬接墊、所述金屬柱以及所述元件晶粒。
  5. 一種形成封裝的方法，包括：形成多個聚合物層；形成多個模製化合物層，其中所述多個聚合物層及所述多個模製化合物層交替地配置，其中所述多個模製化合物層中的每一者藉由製程形成，所述製程包括：施配模製化合物；以及執行平坦化製程以使所述模製化合物的頂面水平；形成第一多個重佈線層，所述第一多個重佈線層各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層；形成第二多個重佈線層，所述第二多個重佈線層各自在所述多個模製化合物層中的一者中，其中所述第二多個重佈線層為水平佈線層；在形成所述第一多個重佈線層及所述第二多個重佈線層之後，將元件晶粒的背側貼合至所述所述多個聚合物層及所述多個模製化合物層的交替疊層中的最頂層；以及在所述交替疊層中的所述最頂層上形成密封體以密封所述元件晶粒。
  6. 如請求項5所述之形成封裝的方法，更包括形成多個通孔，所述多個通孔各自在所述多個模製化合物層中的一者中，其中所述多個通孔中的每一者及對應的之下重佈線路形成於單獨電鍍製程中。
  7. 一種封裝，包括：多個聚合物層，其中所述多個聚合物層具有第一厚度；多個模製化合物層，其中所述多個聚合物層及所述多個模製化合物層交替地安置，其中所述多個模製化合物層具有大於所述第一厚度的第二厚度；第一多個重佈線層，各自在所述多個聚合物層中的一者中，其中所述第一多個重佈線層為電磁屏蔽層；第二多個重佈線層，各自在所述多個模製化合物層中的一者中，其中所述第二多個重佈線層為水平佈線層；元件晶粒，所述元件晶粒的背側貼合至所述所述多個聚合物層及所述多個模製化合物層的交替疊層中的最頂層；以及密封體，設置在所述交替疊層中的所述最頂層上並密封所述元件晶粒。
  8. 如請求項7所述之封裝，其中所述第一多個重佈線層具有第三厚度且所述第二多個重佈線層具有大於所述第三厚度的第四厚度。
  9. 如請求項7所述之封裝，其中所述第二厚度與所述第一厚度的比例大於約1.5。
  10. 如請求項7所述之封裝，其中所述多個模製化合物層中的每一者包括基材及所述基材中的填料顆粒且所述多個聚合 物層由同質材料形成。
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