TW201715670A - 半導體封裝結構 - Google Patents
半導體封裝結構 Download PDFInfo
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- TW201715670A TW201715670A TW105113049A TW105113049A TW201715670A TW 201715670 A TW201715670 A TW 201715670A TW 105113049 A TW105113049 A TW 105113049A TW 105113049 A TW105113049 A TW 105113049A TW 201715670 A TW201715670 A TW 201715670A
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Abstract
本發明提供了一種具有一半導體封裝的一半導體封裝結構。該半導體封裝包括:一重分佈層結構,具有一第一表面及相對於該第一表面的一第二表面;一半導體晶粒,設置在該重分佈層結構的該第一表面上;一模塑料,設置在該重分佈層結構的該第一表面上且圍繞該半導體晶粒;以及一金屬間介電結構,設置在該第一模塑料和該第一半導體晶粒上,其中,該金屬間介電結構包括:具有一天線圖案的一導電層或者一金屬遮罩層。
Description
本發明涉及半導體封裝結構,特別涉及一種具有整合了的天線的扇出封裝結構。
為了確保電子產品及通訊設備的持續小型化及多功能性,期望一種小尺寸、支持多引腳連接、高速運行以及具有高功能性的半導體封裝。另外,在高頻應用中,諸如RF SiP(Radio Frequency System-in-Package,射頻系統級封裝)組件,天線一般用於使能無線通訊。
在此種傳統SiP結構中,分離的天線元件係單獨地被密封或安裝在PCB(Printed Circuit Board,印刷電路板)或封裝上。可是,PCB需要為安裝於其上的天線元件提供額外的區域。如此,難以降低設備尺寸。另外,當天線元件安裝在封裝上時,增加了SiP結構的整體高度。此外,在此情形中,由於天線元件一般經由SMT(Surface Mount Technology,表面貼裝技術)製程安裝在封裝上,因此差的SMT製程控制可能引起天線元件與下面的封裝之間的脫層。如此,降低了半導體封裝結構的穩定性、良品率及生產量。
如此,期望一種創新的半導體封裝結構。
因此,本發明之主要目的即在於提供一種半導體封裝結構,可以提高半導體封裝結構的穩定性、良品率及生產量。
根據本發明至少一個實施例提供了一種半導體封裝結構,包括:一第一半導體封裝,包括:一第一重分佈層結構,具有一第一表面及相對於該第一表面的一第二表面;一第一半導體晶粒,設置在該第一重分佈層結構的該第一表面上;一第一模塑料,設置在該第一重分佈層結構的該第一表面上且圍繞該第一半導體晶粒;以及一金屬間介電結構,設置在該第一模塑料和該第一半導體晶粒上;其中,該金屬間介電結構包括:具有一天線圖案的一導電層,電性耦接至該第一重分佈層結構,或者該該金屬間介電結構包括:一金屬遮罩層,覆蓋該第一半體晶粒。
本發明實施例之半導體封裝結構,其金屬間介電結構包括:具有一天線圖案的一導電層或者一金屬遮罩層,從而實現了天線或金屬遮罩之整合,並且該結構兼容半導體封裝結構的製程,無需執行形成天線設備或金屬遮罩的SMT製程,從而使得半導體封裝結構的可靠性、良品率和生產量均得到提高。
10、20、30、40、50、60‧‧‧半導體封裝結構
134、134’‧‧‧IMD結構
160‧‧‧第一導電結構
132’‧‧‧金屬遮罩層
110‧‧‧第一半導體晶粒
106‧‧‧第一RDL結構
109、209‧‧‧接墊
111、211‧‧‧導電結構
101‧‧‧第一表面
103‧‧‧第二表面
100、300‧‧‧IMD層
104、304‧‧‧第一導電線路
102、302‧‧‧第二導電線路
100a、300a‧‧‧第一次介電層
100b、300b‧‧‧第二次介電層
100c、300c‧‧‧第三次介電層
450‧‧‧電子元件
452‧‧‧主體
454‧‧‧第一電極層
456‧‧‧第二電極層
120‧‧‧第一模塑料
122‧‧‧第一通孔
132‧‧‧導電層
130‧‧‧介電層
140‧‧‧鈍化層
210‧‧‧第二半導體晶粒
360‧‧‧第二導電結構
310‧‧‧第三半導體晶粒
306‧‧‧第二RDL結構
309‧‧‧接墊
311‧‧‧導電結構
301‧‧‧第三表面
303‧‧‧第四表面
320‧‧‧第二模塑料
322‧‧‧第二通孔
通過閱讀接下來的詳細描述以及參考所附的圖式所做的示例,可以更好地理解本發明,其中:
第1A圖為根據本發明一些實施例的典型的半導體封裝結
構的剖面示意圖。
第1B圖為第1A圖中所示的半導體封裝結構中的IMD(Inter-Metal Dielectric,金屬間介電)結構的平面示意圖。
第2圖為根據本發明一些實施例的典型的半導體封裝結構的剖面示意圖,其中該半導體封裝結構具有兩顆並排設置的晶粒(die)。
第3圖為根據本發明一些實施例的典型的半導體封裝結構的剖面示意圖,該半導體封裝結構為PoP(Package on Package,封裝上封裝)結構。
第4A圖為根據本發明一些實施例的典型的半導體封裝結構的剖面示意圖。
第4B圖為第4A圖所示的半導體封裝結構中的IMD結構的平面示意圖。
第5圖為根據本發明一些實施例的典型的半導體封裝結構的剖面示意圖,該半導體封裝結構具有兩顆並排設置的晶粒。
第6圖為根據本發明一些實施例的典型的半導體封裝結構的剖面示意圖,該半導體封裝結構為PoP結構。
以下描述為實現本發明的最佳預期模式。該描述是出於說明本發明一般原理的目的而做出,並且不應該認為有任何限制意義。本發明的範圍可參考所附的申請專利範圍而確定。
本發明將參考特定實施例及參考確定的圖式來描述,但是本發明不限制於此,並且本發明僅由申請專利範圍限
定。描述的圖式僅為原理圖而非限制。在圖式中,出於說明目的,而夸大了某些元件的尺寸,並且這些元件並非按比例繪制。圖式中的尺寸及相對尺寸不對應本發明實踐中的真實尺寸。
第1A圖為根據本發明一些實施例的一半導體封裝結構10的剖面示意圖。第1B圖為第1A圖中所示的半導體封裝結構10中的一IMD結構134的平面示意圖。在一些實施例中,半導體封裝結構10為一晶圓級半導體封裝結構,例如覆晶半導體封裝結構。
參考第1A圖,該半導體封裝結構10包括:一第一半導體封裝,諸如晶圓級半導體封裝,該第一半導體封裝可以安裝在一基底(未示出)上。在一些實施例中,該第一半導體封裝可以包括:一SOC(System-On-Chip,系統單晶片)封裝。另外,該基底可以包括:一PCB並且該基底可以由PP(polypropylene,聚丙烯)形成。在一些實施例中,該基底可以包括:一封裝基板。該半導體封裝結構10中的該第一半導體封裝通過接合製程安裝於該基底上。例如,該第一半導體封裝包括:複數個第一導電結構160,通過接合製程安裝並電性耦接至該基底。
該第一半導體封裝包括:一第一半導體晶粒110及一第一RDL結構106。該第一半導體晶粒110例如可以包括:一MCU(microcontroller,微控制器)、一MPU(microprocessor,微處理器)、一RAM(Random Access Memory,隨機訪問記憶體)、一PMIC(Power Management Integrated Circuit,電源管理積體電路)、一快閃記憶體、一GPS(Global Positioning
System,全球定位系統)設備、一RF(射頻)設備或者他們的任意組合。另外,第一導電結構160例如可以包括:一導電凸塊結構(諸如銅凸塊或焊錫凸塊結構)、一導電柱結構、一導電線結構或者一導電膏(conductive paste)結構。
如第1A圖所示,第一半導體晶粒110可以經由覆晶技術裝配。第一半導體晶粒110之接墊109係電性連接至第一半導體晶粒110之電路(未示出)。在一些實施例中,接墊109屬於第一半導體晶粒110的互連結構(未示出)中的最上層金屬層。第一半導體晶粒110之接墊109接觸對應的導電結構111,例如導電凸塊、柱(post)或焊錫膏。需要注意的是,整合於半導體封裝結構10中的半導體晶粒的數量不限制於公開的實施例。
第一RDL結構106(也被稱為扇出結構)具有一第一表面101和相對該第一表面101的一第二表面103。第一半導體晶粒110設置在第一RDL結構106的第一表面101上。第一半導體晶粒110通過導電結構111連接至第一RDL結構106。
在本實施例中,第一RDL結構106包括:一個或複數個導電線路,設置在一IMD層100中。例如,複數個第一導電線路104設置在第一層位的IMD層100以及至少一個第一導電線路104係電性耦接至該第一半導體晶粒110。另外,複數個第二導電線路102設置在第二層位的IMD層100,其中該第二層位不同於該第一層位。在此情形中,IMD層100可以包括:第一、第二和第三次介電層100a、100b和100c,從
第一RDL結構106的第二表面103向第一RDL結構106的第一表面101依序堆疊,使得第一導電線路104設置在第三次介電層100c上,且第二導電線路102設置在第二次介電層100b上並且由第一次介電層100a覆蓋。另外,通過第二次介電層100b把第一導電線路104與第二導電線路102分隔開。在一些實施例中,IMD層100可以由有機材料或非有機材料形成,其中有機材料包括:聚合物基(polymer base)材料,非有機材料包括:氮化錫(SiNx)、氧化錫(SiOx)、石墨烯,等等。例如,第一、第二、第三次介電層100a、100b和100c均可以由聚合物基材料制成。
在一些實施例中,IMD層100為高k值介電層(k為介電層的介電常數)。在其他一些實施例中,IMD層100可以由光敏材料形成,其中光敏材料包括:乾膜光阻(dry film photoresist)或者貼膜(taping film)。
第二導電線路102的接墊部分從第一次介電層100a的開口露出並連接至設置在第一RDL結構106的第二表面103上的第一導電結構160。另外,需要注意的是,第1A圖所示的第一RDL結構中的導電線路的數量以及次介電層的數量僅為示例,而不是對本發明的限制。
在本實施例中,第一半導體封裝進一步包括:至少一個電子元件450,諸如IPD(Integrated Passive Device,整合被動器件),設置在第一RDL結構106的第二表面103上。IPD通過第一RDL結構106電性耦接至第一半導體晶粒110。在一些實施例中,IPD可以包括:電容、電感、電阻或者他們
的組合。另外,IPD包括:至少一個電極,電性耦接至該等第二導線102之一。例如,電子元件450可以為電性耦接至第一半導體晶粒110的電容。在此情形中,該電容包括:一主體452以及分別設置在該主體452兩端的第一與第二電極層454、456。另外,第一和第二電極層454和456係分別電性耦接至該等導電線路102中的至少兩個。
在本實施例中,如第1A圖所示,第一半導體封裝進一步包括:一第一模塑料(molding compound)120,設置在第一RDL結構106的第一表面101上,並且圍繞在第一半導體晶粒110的周圍。在一些實施例中,第一模塑料120可以由環氧樹脂、樹脂、可塑聚合物等形成。第一模塑料120可以在大致為液體時應用,然後通過化學反應固化,諸如在環氧樹脂或樹脂中。在其他一些實施例中,該第一模塑料120可以是UV(ultraviolet,紫外)或熱固化聚合物,作為能夠設置在第一半導體晶粒110周圍的凝膠或可塑固體而應用,然後通過UV或熱固化製程而固化。第一模塑料120可以按照模型(未示出)固化。
在本實施例中,第一模塑料120包括:複數個穿過第一模塑料120的第一通孔122。該等第一通孔122係電性耦接至第一RDL結構106中的第一導電線路104。另外,該等第一通孔122可以圍繞該第一半導體晶粒110。在一些實施例中,該等第一通孔122可以包括:由銅形成的TPV(Through Package Vias,貫穿封裝通孔)。
第一導電結構160通過第一RDL結構106與第一
模塑料120分開。換言之,第一導電結構160免於與第一模塑料120接觸。在一些實施例中,第一導電結構160可以包括:導電凸塊結構(諸如銅或焊錫凸塊結構),導電柱結構,導電線結構或者導電膏結構。
在本實施例中,如第1A圖所示,第一半導體封裝進一步包括:一IMD結構134,設置在第一模塑料120及第一半導體晶粒110上。用於形成IMD結構134的材料和方法可以相同或類似於形成第一RDL結構106的材料和方法。換言之,形成第一RDL結構106的製程可以用於形成IMD結構134。在本實施例中,IMD結構134可以包括:一導電層132,具有一天線圖案,該導電層132設置在一介電層130之上並且通過第一通孔122電性耦接至第一RDL結構106。在一些實施例中,該具有天線圖案的導電層132可以嵌入於介電層130中。形成具有天線圖案的導電層132的材料和方法可以相同於或類似於形成第一導電線路104和第二導電線路102的材料和方法。另外,介電層130可以是單層或多層結構。另外,形成介電層130的材料和方法可以相同或類似於形成第一、第二或第三次介電層100a、100b或100c的材料和方法。
在本實施例中,如第1B圖所示,於俯視圖中,導電層132的天線圖案為一柵欄(fence)圖案。但是,發明所屬領域具有通常知識者能夠理解的是,各種各樣的圖案可以用作導電層132的天線圖案。具有天線圖案的導電層132使能半導體封裝結構10的無線通訊。
在本實施例中,如第1A圖所示,第一半導體封裝
進一步包括:一可選的鈍化層140,覆蓋IMD結構134,從而保護具有天線圖案的導電層132免於損傷。鈍化層140可以由相同或不同於介電層130的材料構成。例如,鈍化層140可以包括:環氧樹脂、阻焊劑(solder mask)、無機材料(如,氮化錫(SiNx)、氧化錫(SiOx)、石墨烯等)或者有機聚合物基材料。在具有天線圖案的導電層132嵌入於介電層130的情形中,可以省略鈍化層140。
第2圖為根據本發明一些實施例的半導體封裝結構20的剖面示意圖,該半導體封裝結構20具有並排設置的第一和第二半導體晶粒110和210。出於簡潔,以下實施例中的元件,若有相同或相似於第1A圖的元件,則可參考前述描述,在此則省略其相關描述。在本實施例中,除了半導體封裝結構20中的第一半導體封裝進一步包括第二半導體晶粒210之外,該半導體封裝結構20類似於第1A圖所示的半導體封裝結構10,其中該第二半導體晶粒210設置在第一RDL結構106的第一表面101上並且被第一模塑料120及第一通孔122圍繞。在本實施例中,第一和第二半導體晶粒110和210為並排佈置。第二半導體晶粒210的接墊209係電性連接至第二半導體晶粒210的電路(未示出)。在一些實施例中,接墊209屬於第二半導體晶粒210的互連結構(未示出)的最上層金屬層。第二半導體晶粒210的接墊209接觸對應的導電結構211,例如導電凸塊,柱或焊錫膏。第二半導體晶粒210通過接墊209、導電結構211及第一RDL結構106電性耦接至第一半導體晶粒110。需要注意的是,整合於半導體封裝結構20中的半導體晶粒的
數量不限制於公開的實施例。
在一些實施例中,第二半導體晶粒210可以包括:MCU、MPU、RAM、PMIC、快閃記憶體、GPS設備、RF設備或者他們的任意組合。在一些實施例中,第一和第二半導體晶粒110和210中至少之一為SOC晶粒。例如,第一和第二半導體晶粒110和210均為SOC晶粒。可選地,第一半導體晶粒110為SOC晶粒,第二半導體晶粒210為記憶體晶粒。因此,半導體封裝結構20中的第一半導體封裝可以為一純SOC封裝或者一混合SOC封裝。但是,半導體晶粒的數量和佈置方式不限制於公開的實施例。
第3圖為根據本發明一些實施例的半導體封裝結構30的剖面示意圖,該半導體封裝結構30為PoP結構。出於簡潔,以下實施例中的元件,若有相同或相似於第1A圖和第2圖的元件,則可參考前述描述,在此省略相關描述。在本實施例中,除了半導體封裝結構30進一步包括:一堆疊在半導體封裝結構20中的第一半導體封裝下方的第二半導體封裝之外,半導體封裝結構30類似於第2圖的半導體封裝結構20。
在本實施例中,第二半導體封裝之結構類似於第1A圖所示的半導體封裝結構10中的第一半導體封裝的結構。該第二半導體封裝(諸如為晶圓級半導體封裝)可以安裝在基底(未示出)上。在一些實施例中,第二半導體封裝可以包括:一SOC封裝。另外,半導體封裝結構30中的第二半導體封裝使用接合製程而經由複數個第二導電結構360安裝於基底上。第二導電結構360可以相同或類似於第一導電結構160。
第二半導體封裝包括:一第三半導體晶粒310及一第二RDL結構306。第三半導體晶粒310例如可以包括:MCU、MPU、RAM、PMIC、快閃記憶體、GPS設備、RF設備或者他們的任意組合。類似地,第三半導體晶粒310可以通過覆晶技術裝配。第三半導體晶粒310的接墊309係電性連接至第三半導體晶粒310的電路(未示出)。在一些實施例中,接墊309屬於第三半導體晶粒310的互連結構(未示出)的最上層金屬層。第三半導體晶粒310的接墊309接觸對應的導電結構311,例如導電凸塊,柱或焊錫膏。需要注意的是,整合於第二半導體封裝中的半導體晶粒的數量不限制於公開的實施例。
第二RDL結構306(也被稱為扇出結構)具有一第三表面301和相對第三表面301的一第四表面303。第三半導體晶粒310設置在第二RDL結構306的第三表面301上。第三半導體晶粒310通過導電結構311連接至第二RDL結構306。
在本實施例中,第二RDL結構306的結構相同或類似於第一RDL結構106的結構。例如,複數個第一導電線路304設置在第一層位的IMD層300以及至少一個第一導電線路304係電性耦接至第三半導體晶粒310。另外,複數個第二導電線路302設置在第二層位的IMD層300,其中第二層位不同於第一層位。在此情形中,IMD層300可以包括:第一、第二和第三次介電層300a、300b和300c,從第二RDL結構306的第四表面303向第二RDL結構306的第三表面301依序
堆疊,使得第一導電線路304係置於第三次介電層300c上,以及第二導電線路302係置於第二次介電層300b上並且由第一次介電層300a覆蓋。另外,通過第二次介電層300b把第一導電線路304與第二導電線路302分開。在一些實施例中,形成IMD層300的材料可以相同或類似於形成IMD層100的材料。
第二導電線路302的接墊部分從第一次介電層300a的開口露出並連接至設置在第二RDL結構306的第四表面303上的第二導電結構360。另外,需要注意的是,第3圖所示的第二RDL結構的導電線路的數量以及次介電層的數量僅為示例,而不是對本發明的限制。
在本實施例中,第二半導體封裝進一步包括:一電子元件450,設置在第二RDL結構306的第四表面303上。電子元件450(諸如電容)包括:一主體452以及分別設置在主體452兩端的第一和第二電極層454和456,並且該第一和第二電極層454和456分別電性耦接至該等第二導電線路302中的至少兩個。
在本實施例中,如第3圖所示,第二半導體封裝進一步包括:一第二模塑料320,設置在第二RDL結構306的第三表面301上,並且圍繞第三半導體晶粒310。在一些實施例中,第二模塑料320可以由相同或類似第一模塑料120的材料形成。
在本實施例,第二模塑料320可以包括:複數個穿過第二模塑料320的第二通孔322。該等第二通孔322係電
性耦接至該第二RDL結構306的第一導電線路304,以便於形成第一和第二RDL結構106和306之間的電性連接。另外,該等第二通孔322圍繞第三半導體晶粒310。在一些實施例中,第二通孔322可以包括:由銅形成的TPV。另外,第二導電結構360通過第二RDL結構306與第二模塑料320分開。
根據前述實施例,設計半導體封裝結構以製造整合於第一半導體封裝中的天線。該天線提供無線通訊以及兼容半導體封裝結構的製程。相應地,無需執行形成天線設備的SMT製程。如此,半導體封裝結構的可靠性、良品率和生產量均得到提高,同時半導體封裝結構的製造成本得到下降。另外,整合的天線可以為半導體封裝結構的系統集成提供靈活的設計。
第4A圖為根據本發明一些實施例的半導體封裝結構40的剖面示意圖。第4B圖為第4A圖所示的半導體封裝結構40中的IMD結構134’的平面示意圖。出於簡潔,以下實施例中的元件,若有相同或相似於第1A和1B圖的元件,則可參考前述描述,在此省略相關描述。在本實施例中,除了半導體封裝結構40的IMD結構134’具有金屬遮罩層132’之外,半導體封裝結構40類似於第1A圖所示的半導體封裝結構10,其中該金屬遮罩層132’覆蓋第一半導體晶粒110並且可以被鈍化層140或者不被任何鈍化層所覆蓋。如第4B圖所示,不同於第1A圖所示的具有天線圖案的導電層132,金屬遮罩層132’為其中不具有任何圖案或開口的固體/連續層。金屬遮罩層132’設置在介電層130的整個上表面上並且大致上覆蓋
介電層130的整個上表面。另外,金屬遮罩層132’進一步沿介電層130、第一模塑料120及IMD層100的側壁延伸至第一RDL結構106的第二表面103,使得金屬遮罩層132’大致上覆蓋半導體封裝結構40的側壁。在本實施例中,金屬遮罩層132’係電性耦接至至少一個第一通孔122。金屬遮罩層132’用於減少電子噪聲對信號的影響,以及減少可能乾擾其他設備的電磁輻射。
在本實施例中,形成IMD結構134’的方法和材料相同或類似於形成第1A圖所示的IMD結構134的方法和材料。換言之,形成金屬遮罩層132’的材料和方法相同或類似於形成第1A圖所示的具有天線圖案的導電層132的材料和方法。
第5圖為根據本發明一些實施例的半導體封裝結構50的剖面示意圖,其中該半導體封裝結構具有並排設置的第一和第二半導體晶粒110和210。出於簡潔,以下實施例中的元件,若有相同或相似於第4A圖和第2圖的元件,則可參考前述描述,在此省略相關描述。在本實施例中,除了半導體封裝結構50中的IMD結構134’具有金屬遮罩層132’之外,半導體封裝結構50類似於第2圖所示的半導體封裝結構,其中該金屬遮罩層132’覆蓋第一和第二半導體晶粒110和210並且該金屬遮罩層132’可以被鈍化層140或者不被任何鈍化層所覆蓋。另外,如第5圖所示,金屬遮罩層132’進一步沿介電層130、第一模塑料120和IMD層100的側壁延伸至第一RDL結構106的第二表面103,使得金屬遮罩層132’大致上
覆蓋半導體封裝結構50的側壁。在本實施例中,金屬遮罩層132’係電性耦接至至少一個第一通孔122,以減少電子噪聲對信號的影響,以及降低可能乾擾其他設備的電磁輻射。
第6圖為根據本發明一些實施例的半導體封裝結構60的剖面示意圖,該半導體封裝結構60為PoP結構。出於簡潔,以下實施例中的元件,若有相同或相似於第4A圖和第3圖的元件,則可參考前述描述,在此省略相關描述。在本實施例中,除了半導體封裝結構60中的IMD結構134’具有金屬遮罩層132’之外,半導體封裝結構60類似於第3圖所示的半導體封裝結構30,其中該金屬遮罩層132’覆蓋第一和第二半導體晶粒110和210並且該金屬遮罩層132’可以被鈍化層140或者不被任何鈍化層所覆蓋。相似地,如第6圖所示,金屬遮罩層132’進一步沿介電層130、第一模塑料120、IMD層100、第二模塑料320和IMD層300的側壁延伸至第二RDL結構306的第四表面303,使得金屬遮罩層132’大致上覆蓋半導體封裝結構60的側壁。在本實施例中,金屬遮罩層132’係電性耦接至至少一個第一通孔122,以減少電子噪聲對信號的影響,以及降低可能乾擾其他設備的電磁輻射。
根據前述實施例,設計半導體封裝結構以製造整合於半導體封裝中的遮罩層。該遮罩層提供減少電子噪聲和電磁輻射的功能,並且兼容用於半導體封裝結構的製程。相應地,不需要執行額外製程來形成遮罩設備。如此,半導體封裝結構的可靠性、良品率和生產量均得到提高,同時半導體封裝結構的製造成本得到下降。相應地,整合的天線可以為半導體封裝
結構的系統集成提供靈活的設計。
以上所述僅為本發明的較佳實施例而已,並不用以限制本發明,凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等,均應包含在本發明的保護範圍之內。
10‧‧‧半導體封裝結構
134‧‧‧IMD結構
160‧‧‧第一導電結構
110‧‧‧第一半導體晶粒
106‧‧‧第一RDL結構
109‧‧‧接墊
111‧‧‧導電結構
101‧‧‧第一表面
103‧‧‧第二表面
100‧‧‧IMD層
104‧‧‧第一導電線路
102‧‧‧第二導電線路
100a‧‧‧第一次介電層
100b‧‧‧第二次介電層
100c‧‧‧第三次介電層
450‧‧‧電子元件
452‧‧‧主體
454‧‧‧第一電極層
456‧‧‧第二電極層
120‧‧‧第一模塑料
122‧‧‧第一通孔
132‧‧‧導電層
130‧‧‧介電層
140‧‧‧鈍化層
Claims (15)
- 一種半導體封裝結構,包括:一第一半導體封裝,包括:一第一重分佈層結構,具有一第一表面及相對於該第一表面的一第二表面;一第一半導體晶粒,設置在該第一重分佈層結構的該第一表面上;一第一模塑料,設置在該第一重分佈層結構的該第一表面上且圍繞該第一半導體晶粒;以及一金屬間介電結構,設置在該第一模塑料和該第一半導體晶粒上,其中,該金屬間介電結構包括:一導電層,其中該導電層具有一天線圖案並且電性耦接至該第一重分佈層結構,或者該金屬間介電結構包括:一金屬遮罩層,該金屬遮罩層覆蓋該第一半體晶粒。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,該第一半導體封裝進一步包括:一電子元件,設置在該第一重分佈層結構的該第二表面上並且電性耦接至該第一重分佈層結構。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,該第一半導體封裝進一步包括:複數個第一導電結構,設置在該第一重分佈層結構的該第二表面上,並且電性耦接至該第一重分佈層結構。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,該 第一半導體封裝進一步包括:一鈍化層,覆蓋該金屬間介電結構。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,該第一半導體封裝進一步包括:複數個第一通孔,穿過該第一模塑料並且電性耦接至該第一重分佈層結構,其中該等第一通孔還電性耦接該導電層或該金屬遮罩層。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,進一步包括:一第二半導體封裝,堆疊在該第一半導體封裝下方,並且包括:一第二重分佈層結構,電性耦接至該第一重分佈層結構並且具有一第三表面和相對於該第三表面的一第四表面;一第三半導體晶粒,設置在該第二重分佈層結構的該第三表面和該第一重分佈層結構的該第二表面之間;以及一第二模塑料,設置在該第二重分佈層結構的該第三表面和該第一重分佈層結構的該第二表面之間,並且圍繞該第三半導體晶粒。
- 如申請專利範圍第1或者5項所述的半導體封裝結構,其中,該第一半導體封裝進一步包括:一第二半導體晶粒,設置在該第一重分佈層結構的該第一表面之上,並且該第一半導體晶粒和該第二半導體晶粒並排佈置。
- 如申請專利範圍第7項所述的半導體封裝結構,其中,該半導體封裝結構中的半導體晶粒包括:微控制器、微處理器、隨機訪問記憶體、電源管理積體電路、快閃記憶體、 全球定位系統設備或者射頻設備。
- 如申請專利範圍第6項所述的半導體封裝結構,其中,該第二半導體封裝進一步包括:一電子元件,設置在該第二重分佈層結構的該第四表面上,並且電性耦接至該第二重分佈層結構。
- 如申請專利範圍第2或9項所述的半導體封裝結構,其中,該電子元件包括:一電容、一電感、一電阻或他們的組合。
- 如申請專利範圍第6項所述的半導體封裝結構,其中,該第二半導體封裝進一步包括:複數個第二導電結構,設置在該第二重分佈層結構的該第四表面上,並且電性耦接至該第二重分佈層結構。
- 如申請專利範圍第6項所述的半導體封裝結構,其中,該第二半導體封裝進一步包括:複數個第二通孔,穿過該第二模塑料,以形成該第一和第二重分佈層結構之間的電連接。
- 如申請專利範圍第12項所述的半導體封裝結構,其中,該第一半導體封裝進一步包括:複數個第一通孔,穿過該第一模塑料並且電性耦接至該第一重分佈層結構,其中該等第一通孔還電性耦接該導電層或該金屬遮罩層;該等第二通孔中至少一個垂直對齊該等第一通孔中至少一個。
- 如申請專利範圍第7項所述的半導體封裝結構,其中,當該金屬間介電結構包括:該金屬遮罩層時,該金屬遮罩層還覆蓋該第二半導體晶粒。
- 如申請專利範圍第1項所述的半導體封裝結構,其中,該導電層或者該金屬遮罩層位於金屬間介電結構中的介電層之上且通過通孔電性耦接至該第一重分佈層結構。
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EP3091571B1 (en) | 2019-06-12 |
EP3091571A2 (en) | 2016-11-09 |
US20190252351A1 (en) | 2019-08-15 |
CN106129020A (zh) | 2016-11-16 |
CN106129020B (zh) | 2019-04-05 |
US20160329299A1 (en) | 2016-11-10 |
EP3091571A3 (en) | 2017-01-25 |
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