WO2023070581A1 - 扇出型芯片封装结构和制备方法 - Google Patents

扇出型芯片封装结构和制备方法 Download PDF

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Publication number
WO2023070581A1
WO2023070581A1 PCT/CN2021/127671 CN2021127671W WO2023070581A1 WO 2023070581 A1 WO2023070581 A1 WO 2023070581A1 CN 2021127671 W CN2021127671 W CN 2021127671W WO 2023070581 A1 WO2023070581 A1 WO 2023070581A1
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Prior art keywords
chip
conductive
electromagnetic shielding
layer
redistribution layer
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PCT/CN2021/127671
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English (en)
French (fr)
Inventor
朱森林
熊林亮
陈光跃
王福刚
宗佩
Original Assignee
华为技术有限公司
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Priority to PCT/CN2021/127671 priority Critical patent/WO2023070581A1/zh
Priority to CN202180099626.0A priority patent/CN117546288A/zh
Publication of WO2023070581A1 publication Critical patent/WO2023070581A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a fan-out chip packaging structure and manufacturing method.
  • the industry proposes to use a substrate-less packaging structure to package multiple chips together to improve the electrical performance of the packaged chips.
  • the fan-out package (Fan-out Package) structure can provide more I/O connection points and become the mainstream direction.
  • the fan-out packaging structure and preparation method provided in the present application can reduce electromagnetic interference in the fan-out packaging structure.
  • the application adopts the following technical solutions:
  • the embodiment of the present application provides a fan-out packaging structure
  • the fan-out packaging structure includes: a first redistribution layer, the first redistribution layer includes a first electromagnetic shielding layer connected to a common ground ;
  • the second redistribution layer, the second redistribution layer includes a second electromagnetic shielding layer connected to the common ground;
  • the first chip is arranged between the first redistribution layer and the second redistribution layer , the orthographic projection of the first electromagnetic shielding layer and the second electromagnetic shielding layer to the first chip at least partially covers the first chip;
  • the first molding material the first molding material is filled in the first redistribution layer and the second The area between the redistribution layers, where the first chip and the conductive structure are not provided, is used to wrap the first chip.
  • an electromagnetic shielding structure formed by the first electromagnetic shielding layer, the conductive structure and the second electromagnetic shielding layer is formed around the first chip, so as to confine the first chip within the electromagnetic shielding structure.
  • the electromagnetic shielding structure is connected to the common ground, so that the electromagnetic interference signal is transmitted to the common common ground through the electromagnetic shielding structure, thereby reducing the electromagnetic interference of the conductive lines on the redistribution layer and other chips to the first chip, and avoiding the first The distortion of the signal processed or transmitted by the chip, thereby improving the reliability of the first chip; or, similarly, the related electromagnetic shielding structure can also reduce the electromagnetic interference of the first chip to other chips or conductive lines, and improve the fan-out packaging structure. The reliability of the packaged chips.
  • the fan-out packaging structure further includes a second chip, and the second chip is arranged on the first rewiring device along the thickness direction of the first chip. layer above.
  • the first redistribution layer further includes a first conductive line connected to the first chip; the second redistribution layer further includes a first conductive line connected to the second The second conductive circuit for chip connection; a plurality of conductive pillars are also arranged between the first redistribution layer and the second redistribution layer, and the plurality of conductive pillars are arranged in the peripheral area of the conductive structure; The first conductive circuit is communicated with the second conductive circuit through the plurality of conductive columns.
  • the first conductive line includes a third conductive line at least partially covered by a projection of the first electromagnetic shielding layer, and the third conductive line and the first conductive line
  • An electromagnetic shielding layer is disposed on a different layer of the first redistribution layer, and the first electromagnetic shielding layer is disposed on a side away from the first chip corresponding to the third conductive circuit.
  • the second conductive line includes a fourth conductive line at least partially covered by the projection of the second electromagnetic shielding layer, and the fourth conductive line and the first Two electromagnetic shielding layers are disposed on different layers of the second redistribution layer, and the second electromagnetic shielding layer is disposed on a side away from the first chip relative to the fourth conductive circuit.
  • the first redistribution layer further includes a third electromagnetic shielding layer, and the third shielding layer is connected to the first conductive line and the first electromagnetic shielding layer They are all arranged in different layers; relative to the first conductive circuit and the first electromagnetic shielding layer, the third electromagnetic shielding layer is arranged on a side close to the second chip.
  • the fan-out packaging structure further includes a second molding material; the second molding material wraps the second chip.
  • the fan-out packaging structure further includes a third chip, and the third chip is disposed between the first redistribution layer and the second redistribution layer Between, the peripheral area of the conductive structure, and wrapped by the first molding material; the third chip communicates with the first chip through the second conductive circuit.
  • the fan-out packaging structure further includes a plurality of conductive bumps; the plurality of conductive bumps are disposed on the second redistribution layer, away from the The surface of the first chip; the plurality of conductive bumps include a ground conductive bump used to be connected to the common ground on the printed circuit board, the conductive circuit on the first electromagnetic shielding layer and the second electromagnetic shielding layer The conductive lines on the shielding layer are connected to the ground conductive bumps.
  • the embodiment of the present application provides a method for preparing a fan-out packaging structure, the preparation method includes: providing a carrier board, forming a first redistribution layer on the carrier board, and the first redistribution layer Including a first electromagnetic shielding layer connected to the common ground; forming a conductive structure on the first redistribution layer; mounting a first chip on the surface of the first redistribution layer and the area surrounded by the conductive structure; On the surface of the first redistribution layer, the gap between the first chip and the conductive structure is filled with a first molding material; on the active surface of the first chip, the surface of the conductive structure and the A second redistribution layer is formed on the surface of the first molding material, the second redistribution layer includes a second electromagnetic shielding layer connected to the common ground, and the second electromagnetic shielding layer is connected to the conductive structure through the conductive structure The first electromagnetic shielding layer is connected; the carrier board is removed.
  • the manufacturing method further includes: mounting a second chip on the exposed first redistribution layer.
  • FIG. 1 is a schematic structural diagram of a fan-out packaging structure provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the relative positional relationship between the electromagnetic shielding layer and the chip 10 in the fan-out packaging structure shown in FIG. 1 provided by the embodiment of the present application;
  • 3A and 3B are top views of the fan-out packaging structure shown in FIG. 1 after the redistribution layer 21 is removed;
  • FIG. 4 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application.
  • FIG. 5 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application.
  • FIG. 6 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application.
  • FIG. 7 is a flowchart of a method for preparing the fan-out packaging structure shown in FIG. 1 provided in the embodiment of the present application;
  • FIG. 8A-8H are schematic diagrams of various structures during the preparation process of the fan-out packaging structure shown in FIG. 1 .
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or descriptions. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • “plurality” means two or more. For example, a plurality of chips refers to two or more chips.
  • the fan-out packaging structure provided in the embodiment of the present application may be a system-in-package (system in package), that is, multiple chips may be packaged in the same package.
  • the fan-out packaging structure may be a fan-out-package on package (FO-PoP, fan out-package on package) packaging structure, that is, a part of the chips is stacked on another part of the chips.
  • the chip described in the embodiment of the present application may be a bare chip (Die), or a chip formed by simple packaging of a bare chip and other chips or components (active devices or passive devices, etc.), or may be packaged
  • the subsequent chip packaging structure is not limited here.
  • the fan-out packaging structure described in the embodiments of the present application will be described below through the embodiments shown in FIGS. 1-6 .
  • FIG. 1 is a schematic structural diagram of a fan-out packaging structure provided by an embodiment of the present application.
  • a fan-out packaging structure 100 includes a chip 10 , a chip 11 , a redistribution layer 20 , a redistribution layer 21 , a conductive structure 30 and a molding material 40 .
  • the chip 10 is disposed between the redistribution layer 20 and the redistribution layer 21
  • the chip 11 is disposed on the redistribution layer 20 .
  • the conductive structure 30 surrounds the chip 10 , and extends from the redistribution layer 20 to the redistribution layer 21 along the thickness direction of the chip 10 , that is, the direction z shown in FIG. 1 .
  • An electromagnetic shielding layer 201 is arranged on the rewiring layer 20, an electromagnetic shielding layer 211 is arranged on the rewiring layer 21, and the conductive structure 30 communicates with the electromagnetic shielding layer 201 and the electromagnetic shielding layer 211, thereby forming an electromagnetic shielding layer 201 around the chip 10.
  • the conductive structure 30 the electromagnetic shielding layer 211 to the electromagnetic shielding structure of the conductive structure 30 , so as to confine the chip 10 within the electromagnetic shielding structure.
  • the electromagnetic shielding structure is connected to the common ground, so that the electromagnetic interference signal is transmitted to the common common ground through the electromagnetic shielding structure, thereby reducing the number of conductive lines on the chip 11, the redistribution layer 20, and the pair of conductive lines on the redistribution layer 21.
  • the electromagnetic interference of the chip 10 avoids the distortion of the signal processed or transmitted by the chip 10 , thereby improving the reliability of the chip 10 .
  • the relevant electromagnetic shielding structure can also reduce the interference of the chip 10 to other parts, such as the chip 11 .
  • the molding material 40 may include, for example, one or more combinations of epoxy resin (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, and polyimide.
  • the rewiring layer 20 may include multiple wiring layers.
  • FIG. 1 schematically shows that the rewiring layer 20 includes a wiring layer close to the chip 10 and a wiring layer far away from the chip 10 .
  • the electromagnetic shielding layer 201 is disposed on a wiring layer close to the chip 10 in the redistribution layer 20 .
  • the orthographic projection of the electromagnetic shielding layer 201 onto the chip 10 at least partially covers the chip 10 , for example, fully covering the chip 10 as shown in the figure helps to improve the electromagnetic shielding effect.
  • FIG. 2 schematically shows the structure of the electromagnetic shielding layer 201 and its relative positional relationship with the chip 10 .
  • the electromagnetic shielding layer 201 includes conductive lines for conducting the above-mentioned electromagnetic interference signals to the common ground and insulating materials for isolating the conductive lines.
  • the conductive circuit can be metal, for example, it can include one or more combinations of copper (Cu), silver (Ag), aluminum (Al), etc.
  • the insulating material can be an organic polymer material, and the organic polymer material It may include but not limited to: polyimide (PI, Polyimide), polybenzoxazole (ploybenzoxazole, PBO), benzocyclobutene (BCB), or epoxy molding compound (Epoxy Molding Compound, EMC), etc.
  • the pattern formed by the electromagnetic shielding layer 201 may be in the form of a grid as shown in FIG.
  • the conductive lines 2011 divide the insulating material into a plurality of grids 2012 .
  • the thermal expansion coefficient of the wiring layer will increase, thereby causing the chip to be in an environment with alternating cold and hot temperatures and a large temperature difference between cold and hot. As a result, the chip is deformed due to thermal expansion and contraction, which in turn leads to damage to the chip due to excessive deformation.
  • the pattern formed by the electromagnetic shielding layer 201 in a grid shape, that is, avoiding that the area ratio of the electromagnetic shielding layer 201 occupied by the conductive lines 2011 is too high, thereby avoiding chip deformation or damage.
  • the electromagnetic interference signal cannot be effectively shielded. Therefore, preferably, the width of each grid along the x direction or the width along the y direction is less than 1/10 of the wavelength of the interference signal, so as to effectively shield the interference signal.
  • a conductive circuit 202 for connecting to the chip 10 is also provided.
  • the conductive circuit 202 may be disposed in a wiring layer on a side farther away from the chip 10 than the electromagnetic shielding layer 201 .
  • the redistribution layer 20 is also provided with vias (Via) 203 , the vias 203 are filled or plated with conductive material, and the leading end of the chip 10 communicates with the conductive circuit 202 through the vias 203 .
  • the redistribution layer 21 may also include multilayer wiring layers.
  • FIG. 1 schematically shows that the redistribution layer 21 includes a wiring layer close to the chip 10 and a wiring layer far away from the chip 10 , which are two wiring layers.
  • the electromagnetic shielding layer 211 is disposed on a wiring layer close to the chip 10 in the redistribution layer 21 .
  • the orthographic projection of the electromagnetic shielding layer 211 onto the chip 10 at least partially covers the chip 10 , for example, fully covering the chip 10 as shown in the figure helps to improve the electromagnetic shielding effect.
  • the structure and formed pattern of the electromagnetic shielding layer 211 may be the same as the structure and formed pattern of the electromagnetic shielding layer 201 shown in FIG. 2 , which will not be repeated in detail.
  • the conductive circuit 212 for connecting with the chip 11 .
  • the conductive circuit 212 may be disposed in a wiring layer on a side farther away from the chip 10 than the electromagnetic shielding layer 211 .
  • the lead-out end of the chip 11 communicates with the conductive circuit 212 .
  • FIG. 1 schematically shows that the conductive circuit 212 is disposed on the electromagnetic shielding layer 211 and in the wiring layer on the side away from the chip 10 .
  • the conductive circuit 212 may also be disposed in the same wiring layer as the electromagnetic shielding layer 211 , for example, be horizontally spaced apart from the electromagnetic shielding layer 211 and isolated from each other.
  • the conductive structure 30 may be a continuous structure surrounding the chip 10 or a discontinuous structure surrounding the chip 10 .
  • the conductive structure 30 may be, for example, a plurality of conductive pillars surrounding the chip 10 .
  • 3A and 3B are top views of the fan-out packaging structure 100 shown in FIG. 1 after the redistribution layer 21 is removed. FIG. It schematically shows the case where the conductive structure 30 is a continuous structure.
  • the top surface of the conductive structure 30 is connected to the conductive circuit on the shielding layer 211, and the bottom surface of the conductive structure 30 is connected to the conductive circuit on the shielding layer 201, thereby forming the electromagnetic shielding layer 201, the conductive structure 30, the electromagnetic shielding layer 201 to The electromagnetic shielding structure of the conductive structure 30 .
  • a conductive circuit 202 on the redistribution layer 20 and a conductive circuit on the redistribution layer 21 are also provided.
  • the conductive pillar 50 connected by the line 212 .
  • the conductive pillar 50 can be a metal pillar formed of a metal material, such as a copper pillar, an aluminum pillar, a silver pillar, or a palladium pillar, or a pillar formed of other conductive materials.
  • the pillar is preferably a cylinder. The embodiment of the application does not limit this. Therefore, the leads of the chip 11 can be connected to the conductive lines 202 on the redistribution layer 20 through the conductive lines 212 and the conductive posts 50 on the redistribution layer 21 , so as to realize the interconnection between the chip 11 and the chip 10 . It can be seen from FIG. 1 , FIG. 3A and FIG.
  • the redistribution layer 20 shown in FIG. 1 is away from the surface S1 of the chip 10 and further includes a plurality of conductive bumps 204 for connecting with conductive lines on a printed circuit board (PCB, printed circuit board).
  • the material of the conductive bump 204 may include but not limited to: tin material or tin-silver mixed material and the like.
  • the plurality of conductive bumps 204 include a ground conductive bump used to connect to the common ground on the PCB, and the conductive circuit on the shielding layer 201 communicates with the ground conductive bump through the via hole on the redistribution layer 20, thereby Connect to the common ground on the PCB.
  • the common ground terminal of the chip 10 can also be connected to the above-mentioned ground conductive bump through the conductive line 202 ;
  • the other conductive bumps are all connected to the conductive line 202 on the redistribution layer 20, and the lead-out ends of the chip 10 and the chip 11 are all connected through the conductive line 202 and the lead-out end of the chip 11.
  • the conductive bumps 204 are connected to the conductive traces on the PCB.
  • the chip 11 disposed on the redistribution layer 21 can be a chip after simple packaging, and then disposed on the surface of the redistribution layer 21 through a surface mount process, as shown in FIG. Figure 1 shows. In other possible implementation manners, the chip 11 may also be a bare chip. When the chip 11 is a bare chip, a plastic encapsulation material 60 is also provided around the chip 11 , as shown in FIG. 4 . In the fan-out packaging structure 200 shown in FIG. 4 , the molding material 60 is deposited on the surface of the redistribution layer 21 and the chip 11 to wrap the chip 11 and provide support and protection for the chip 11 .
  • the molding compound 60 can be the same material as the molding compound 40 .
  • the redistribution layer 21 may also be provided with an electromagnetic shielding layer 213 , As shown in Figure 5.
  • the electromagnetic shielding layer 213 is disposed in the redistribution layer 21 on a side closer to the chip 11 than the electromagnetic shielding layer 211 and the conductive circuit 212 . That is, the conductive circuit 212 is disposed between the electromagnetic shielding layer 211 and the electromagnetic shielding layer 213 .
  • the structure and the formed pattern of the electromagnetic shielding layer 213 may be the same as the structure and the formed pattern of the electromagnetic shielding layer 201 shown in FIG. Go into details.
  • FIG. 1 In the fan-out packaging structure shown in FIG. 1 , FIG. 4 and FIG. 5 , it is shown that a chip is packaged between the redistribution layer 20 and the redistribution layer 21 .
  • multiple chips can also be arranged between the redistribution layer 20 and the redistribution layer 21, as shown in FIG.
  • the fan-out packaging structure 600 shown in FIG. A chip 12 is provided.
  • the chip 12 and the chip 10 are arranged at intervals along the direction x shown in FIG. 6 (that is, the horizontal direction shown in FIG. 6 ).
  • the conductive circuit 202 in the redistribution layer 20 includes not only a conductive circuit disposed in a different wiring layer from the electromagnetic shielding layer 201 , but also a conductive circuit disposed in the same wiring layer as the electromagnetic shielding layer 201 .
  • the conductive circuit disposed on the same layer as the electromagnetic shielding layer 201 is disposed on a side of the electromagnetic shielding layer 201 and is isolated from the electromagnetic shielding layer 201 .
  • the lead-out end of chip 10 and the lead-out end of chip 12 are both connected to the conductive circuit 202 in the redistribution layer 20 through the via hole on the redistribution layer 20, and the chip 10 and the chip 12 are connected to each other through the conductive circuit 202.
  • the chip 10 and the chip 12 are also connected to the conductive bump 204 through the via hole on the redistribution layer 20 and the conductive line 202 .
  • the conductive circuit 212 in the redistribution layer 21 includes not only a conductive circuit arranged in a wiring layer different from the electromagnetic shielding layer 211, but also a conductive circuit arranged in the same wiring layer as the electromagnetic shielding layer 211; the conductive circuit 212 passes through the conductive circuit
  • the post 50 communicates with the conductive circuit 202, so that the chip 11 communicates with the chip 10 and the chip 12 through the conductive circuit 212, the conductive post 50 and the conductive circuit 202; in addition, the chip 11 also passes the conductive circuit 212, the conductive post 50 and the conductive circuit 202, communicate with the conductive bump 204 .
  • an electromagnetic shielding layer similar to that formed by the electromagnetic shielding layer 201, the electromagnetic shielding layer 211 and the conductive structure 30 around the chip 10 can also be provided around the chip 10.
  • the structure, and the specific setting method refer to the description of the relevant structure in FIG. 1 , and will not be repeated here.
  • a chip is disposed on the redistribution layer 21 as shown in FIG. 1 , FIG. 4 , FIG. 5 and FIG. 6 .
  • more chips (such as 2 or 3, etc.) can also be arranged on the redistribution layer 21; chip, which is not specifically limited in this embodiment of the present application.
  • the chip packaged in the fan-out packaging structure shown in the embodiment of the present application may include but not limited to: System on chip (System on chip) , memory (Memory), discrete devices, application processing chip (Application Processor, AP), micro-electro-mechanical system (Micro-Electro-Mechanical System, MEMS), microwave radio frequency chip, application-specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) and other chips .
  • System on chip System on chip
  • memory Memory
  • AP application processing chip
  • MEMS micro-electro-mechanical system
  • microwave radio frequency chip Application-specific integrated circuit
  • ASIC Application Specific Integrated Circuit
  • the above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, for example, a neural network processor (Network Processing Unit, NPU), etc.
  • the memory may be a cache memory (cache), a random access memory (Random Access Memory, RAM), a read-only memory (Read Only Memory, ROM), or other memory.
  • Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, and the like, for example. For example, when the fan-out packaging structure shown in FIG. 1, FIG. 4 or FIG.
  • the chip 10 packaged in the fan-out packaging structure may be an analog chip (such as a discrete device, an integrated operational amplifier, a filter, etc.)
  • the chip 11 can be a digital chip (such as a memory, a processor, etc.); for another example, when the fan-out packaging structure shown in FIG. 6 is adopted, the chip 10 and the chip 11 packaged in the fan-out packaging structure can be respectively Analog chip and memory, the chip 12 can be a processor.
  • the fan-out packaging structure described in the above embodiments can be prepared by various fan-out packaging processes, including but not limited to: chip-first forward packaging process, chip-later forward packaging process, flip-chip first process or post-chip flip-chip process.
  • chip forward packaging process is taken as an example. Taking the structure of the prepared fan-out packaging structure as shown in FIG. 1 as an example, and combining the process 700 shown in FIG. describe.
  • the process flow 700 includes the following steps:
  • a carrier a is provided, and a redistribution layer 21 is formed on the surface of the carrier a.
  • the material of the carrier a may include, but not limited to: silicon material, glass material, or a mixture of the two materials, etc., and the carrier a may have a wafer-level or board-level size.
  • the surface of the carrier a is coated with bonding glue.
  • An insulating material is deposited on the surface coated with the bonding glue.
  • one or more standard processes such as photolithography, development, etching, deposition and electroplating can be used to prepare multi-layer wiring layers on the insulating material, and via holes connecting the wiring layer and the surface of the insulating material to form rewiring Layer 21.
  • each wiring layer includes patterned conductive lines.
  • the conductive circuit formed on the redistribution layer away from the carrier a is grid-shaped as shown in FIG. 2 , and the grid-shaped conductive circuit and the insulating material in the grid form an electromagnetic shielding layer 211;
  • the surface of the insulating material extends to the redistribution layer away from the carrier a, and communicates with the conductive line on the electromagnetic shielding layer 211;
  • the conductive lines 212 on the redistribution layer of board a are connected. Conductive material may be deposited or plated in the vias.
  • Step 702 forming the conductive structure 30 and the conductive column 50 on the redistribution layer 21 .
  • a metal material is firstly deposited on the surface of the rewiring layer 21 by vapor deposition (such as physical vapor deposition or chemical vapor deposition).
  • the metal material may include, but is not limited to: materials such as copper, aluminum, silver, gold, or metal alloy materials.
  • a photoresist is deposited on the surface of the metal material.
  • the conductive structure 30 can be a plurality of conductive columns surrounding the area for disposing the chip 10 , or a continuous conductive structure surrounding the area for disposing the chip 10 , which is determined based on the pattern of the mask.
  • a plurality of conductive pillars 50 can be formed on the surface of the redistribution layer 21 and the peripheral region of the conductive structure 30 by using the same mask and through the same photolithography and development process.
  • the plurality of conductive pillars 50 communicate with the via holes 12 .
  • Step 703 mounting the backside of the chip 10 on the surface of the redistribution layer 21 .
  • the back surface of the chip 10 can be mounted on the redistribution layer 21 through an insulating medium (such as insulating glue) and other materials.
  • the chip 10 is disposed within the area defined by the conductive structure 30 , as shown in FIG. 8C .
  • the active side of chip 10 is exposed to the outside.
  • Step 704 filling the gaps of the redistribution layer 21 , the chip 10 , the conductive structure 30 and the conductive pillar 50 with an insulating material 40 .
  • an insulating material 40 is deposited on the exposed surface of the redistribution layer 21 and the surface of the chip 10 .
  • the molding material is processed by a planarization process to expose the active surface of the chip 10 , the surface of the conductive structure 30 and the surface of the conductive pillar 50 .
  • the resulting structure after this step is shown in Figure 8D.
  • Step 705 forming the redistribution layer 20 on the exposed active surface of the chip 10 , the surface of the conductive structure 30 , the surface of the conductive pillar 50 and the surface of the chip 10 .
  • one or more standard processes such as photolithography, development, etching, deposition, and electroplating can be used to form the active surface of the chip 10, the surface of the conductive structure 30, the surface of the conductive pillar 50, and the surface of the chip 10.
  • On the horizontal surface formed on the surface prepare multi-layer wiring layers and via holes connecting the wiring layers and the active surface of the chip 10 , the wiring layers and the conductive structure 30 , and the wiring layers and the conductive pillars 50 , thereby forming the rewiring layer 20 .
  • each wiring layer includes patterned conductive lines.
  • the pattern presented by the redistribution layer close to the chip 10 is grid-like as shown in FIG.
  • the structure 30 is connected, and the conductive line 202 formed on the redistribution layer away from the chip 10 is connected to the plurality of conductive columns 50 through via holes.
  • Step 706 depositing a plurality of conductive bumps 204 on the surface of the redistribution layer 20 away from the chip 10 for welding with the PCB.
  • the conductive circuit 202 is also connected to the conductive bump 204 through a via hole. Therefore, the leading end of the chip 10 communicates with the conductive bump 204 through the via hole and the conductive circuit 202 .
  • the structure formed after this step is shown in Figure 8F
  • Step 707 deposit the temporary bonding glue 13 on the surface of the redistribution layer 20 and the conductive bump 204 to cover the conductive bump 204 .
  • Step 708 paste the loading board b on the temporary bonding glue 13 .
  • the resulting structure after this step is shown in Figure 8G.
  • Step 709 removing the carrier a to expose the surface of the redistribution layer 21 .
  • Step 710 etching the redistribution layer 21 to form a plurality of via holes for connecting the surface of the redistribution layer 21 and the conductive lines 212 .
  • Step 711 flip-chip the chip 11 on the surface of the redistribution layer 21 . Therefore, the leading end of the chip 11 communicates with the conductive circuit 212 on the redistribution layer 21 . The leading end of the chip 11 communicates with the chip 10 through the via hole in the redistribution layer 21 and the conductive circuit 212 , the conductive column 50 , the via hole on the redistribution layer 20 and the conductive circuit 202 .
  • the resulting structure after this step is shown in Figure 8H.
  • Step 712 removing the carrier board b and the temporary bonding glue 13 .
  • the fan-out packaging structure as shown in FIG. 1 can be prepared.
  • the method includes the following steps: depositing an insulating material 60 on the back surface of the chip 11 and the exposed surface of the rewiring layer 21 to provide support and protection for the chip 11 .
  • an electromagnetic shielding layer 213 is also formed on the redistribution layer close to the carrier a. Layer 213 communicates with electromagnetic shielding layer 211 through vias in redistribution layer 21 .
  • step 703 it also includes the step of mounting the backside of the chip 12 on the surface of the redistribution layer 21; in the above step 704, it also includes A step of filling the periphery of the chip 12 with an insulating material 40 .

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Abstract

本申请实施例提供了一种扇出型封装结构和制备方法，该扇出型封装结构包括第一重布线层，第一重布线层中包括与公共地连接的第一电磁屏蔽层；第二重布线层，第二重布线层中包括与公共地连接的第二电磁屏蔽层；第一芯片，设置于第一重布线层和第二重布线层之间，第一电磁屏蔽层和第二电磁屏蔽层向第一芯片的正投影至少部分覆盖第一芯片；环绕第一芯片的导电结构，沿第一芯片的厚度方向，导电结构连通第一电磁屏蔽层和第二电磁屏蔽层；塑封材料，塑封材料填充于第一重布线层和第二重布线层之间、未设置第一芯片和导电结构的区域，用于包裹第一芯片，该扇出型封装结构可以降低扇出型封装结构中的电磁干扰。

Description

扇出型芯片封装结构和制备方法 技术领域
本申请实施例涉及半导体封装技术领域，尤其涉及一种扇出型芯片封装结构和制备方法。
背景技术
随着通信、人工智能等技术的发展，大量的数据流动与转移的需求越来越大，支持诸如5G应用、人工智能等应用的硬件需要具有高速计算、低延时、多带宽以及系统集成等功能。为了满足硬件设备的功能需求，业界提出采用无载板封装结构将多个芯片封装在一起来提高封装芯片的电学性能。当前无载板封装结构中，扇出型封装(Fan-out Package)结构可以提供更多的I/O连接点数量，成为主流方向。
当采用扇出型封装结构在一个封装体内封装多个芯片时，该多个芯片之间通常存在电磁干扰；此外，导电线路上的寄生电容和寄生电感也会对芯片造成电磁干扰。该电磁干扰有可能降低所封装的某些芯片(例如模拟芯片)的信号处理质量(例如导致信号畸变、信号延迟严重)。由此，如何降低扇出型封装结构中电磁干扰对芯片的影响成为需要解决的问题。
发明内容
本申请提供的扇出型封装结构和制备方法，可以降低扇出型封装结构中电磁干扰。为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种扇出型封装结构，该扇出型封装结构包括：第一重布线层，所述第一重布线层中包括与公共地连接的第一电磁屏蔽层；第二重布线层，所述第二重布线层中包括与公共地连接的第二电磁屏蔽层；第一芯片，设置于所述第一重布线层和所述第二重布线层之间，所述第一电磁屏蔽层和所述第二电磁屏蔽层向所述第一芯片的正投影至少部分覆盖所述第一芯片；环绕所述第一芯片的导电结构，沿所述第一芯片的厚度方向，所述导电结构连通所述第一电磁屏蔽层和所述第二电磁屏蔽层；第一塑封材料，所述第一塑封材料填充于所述第一重布线层和所述第二重布线层之间、未设置所述第一芯片和所述导电结构的区域，用于包裹所述第一芯片。
本申请实施例中，在第一芯片的周围形成由第一电磁屏蔽层、导电结构以及第二电磁屏蔽层所形成的电磁屏蔽结构，以将第一芯片限制于该电磁屏蔽结构内。此外，该电磁屏蔽结构与公共地连接，从而电磁干扰信号通过电磁屏蔽结构传输至共公共地，由此可以降低重布线层上的导电线路以及其他芯片对第一芯片的电磁干扰，避免第一芯片所处理或传输的信号的畸变，从而提高第一芯片的可靠性；或者，类似地，相关电磁屏蔽结构也可以降低第一芯片对其他芯片或者导电线路的电磁干扰，提高扇出型封装结构所 封装的芯片的可靠性。
基于第一方面，在一种可能的实现方式中，所述扇出型封装结构还包括第二芯片，沿所述第一芯片的厚度方向，所述第二芯片设置于所述第一重布线层之上。
基于第一方面，在一种可能的实现方式中，所述第一重布线层还包括与所述第一芯片连接的第一导电线路；所述第二重布线层还包括与所述第二芯片连接的第二导电线路；所述第一重布线层和所述第二重布线层之间还设置有多个导电柱，所述多个导电柱设置于所述导电结构的外围区域；所述第一导电线路和所述第二导电线路之间通过所述多个导电柱连通。
基于第一方面，在一种可能的实现方式中，所述第一导电线路包括被所述第一电磁屏蔽层的投影至少部分覆盖的第三导电线路，所述第三导电线路和所述第一电磁屏蔽层设置于所述第一重布线层中的不同层，所述第一电磁屏蔽层相对应所述第三导电线路设置于远离所述第一芯片的一侧。
基于第一方面，在一种可能的实现方式中，所述第二导电线路包括被所述第二电磁屏蔽层的投影至少部分覆盖的第四导电线路，所述第四导电线路和所述第二电磁屏蔽层设置于所述第二重布线层中的不同层，所述第二电磁屏蔽层相对于所述第四导电线路设置于远离所述第一芯片的一侧。
基于第一方面，在一种可能的实现方式中，所述第一重布线层还包括第三电磁屏蔽层，所述第三屏蔽层与所述第一导电线路以及所述第一电磁屏蔽层均不同层设置；相对于所述第一导电线路以及所述第一电磁屏蔽层，所述第三电磁屏蔽层设置于靠近所述第二芯片的一侧。
基于第一方面，在一种可能的实现方式中，所述扇出型封装结构还包括第二塑封材料；所述第二塑封材料包裹所述第二芯片。
基于第一方面，在一种可能的实现方式中，所述扇出型封装结构还包括第三芯片，所述第三芯片设置于所述第一重布线层和所述第二重布线层之间、所述导电结构的外围区域，并被所述第一塑封材料所包裹；所述第三芯片通过所述第二导电线路与所述第一芯片连通。
基于第一方面，在一种可能的实现方式中，所述扇出型封装结构还包括多个导电凸块；所述多个导电凸块设置于所述第二重布线层上、远离所述第一芯片的表面；所述多个导电凸块中包括用于与印刷电路板上的公共地相连接的接地导电凸块，所述第一电磁屏蔽层上的导电线路和所述第二电磁屏蔽层上的导电线路与所述接地导电凸块连接。
第二方面，本申请实施例提供一种扇出型封装结构的制备方法，该制备方法包括：提供一载板，在所述载板上形成第一重布线层，所述第一重布线层中包括与公共地连接的第一电磁屏蔽层；在所述第一重布线层上形成导电结构；在所述第一重布线层的表面、导电结构所环绕的区域，贴装第一芯片；在所述第一重布线层的表面之上、所述第一芯片与所述导电结构的间隙填充第一塑封材料；在所述第一芯片的有源面、所述导电结构的表面以及所述第一塑封材料的表面之上形成第二重布线层，所述第二重布线层中包括与公共地连接的第二电磁屏蔽层，所述第二电磁屏蔽层通过所述导电结构与所述第一电磁屏蔽层连通；移除所述载板。
基于第二方面，在一种可能的实现方式中，所述移除所述载板之后，所述制备方法还包括：在暴露出的所述第一重布线层之上贴装第二芯片。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的扇出型封装结构的一个结构示意图；
图2是本申请实施例提供的如图1所示的扇出型封装结构中、电磁屏蔽层与芯片10之间的相对位置关系示意图；
图3A和图3B是如图1所示的扇出型封装结构去除重布线层21后的俯视图；
图4是本申请实施例提供的扇出型封装结构的又一个结构示意图；
图5是本申请实施例提供的扇出型封装结构的又一个结构示意图；
图6是本申请实施例提供的扇出型封装结构的又一个结构示意图；
图7是本申请实施例提供的如图1所示的扇出型封装结构的制备方法流程图；
图8A-图8H是如图1所示的扇出型封装结构制备过程中的各结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。
在本申请实施例中，“示例性的”或者“例如”等词用于表示例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个芯片是指两个或两个以上的芯片。
本申请实施例提供的扇出型封装结构，可以为系统级封装(system in package)，也即可以在同一封装体内封装多个芯片。具体实现中，该扇出型封装结构可以为扇出型构装堆叠(FO-PoP，fan out-package on package)封装结构，也即多个芯片中一部分芯片堆叠于另外一部分芯片之上。本申请实施例中所述的芯片可以为裸芯片(Die)，也可以是裸芯片与其他芯片或部件(有源器件或无源器件等)通过简单封装后形成的芯片，还可以是经过封装之后形成的芯片封装结构，此处不作限定。下面通过图1-图6所示的实施例，对本申请实施例中所述的扇出型封装结构进行描述。
请参考图1，图1是本申请实施例提供的扇出型封装结构的一个结构示意图。在图1中，扇出型封装结构100包括芯片10、芯片11、重布线层20、重布线层21、导电结构30以及塑封材料40。芯片10设置于重布线层20和重布线层21之间，芯片11设置于重布线层20之上。导电结构30环绕在芯片10的周围，沿芯片10的厚度方向，也即图1所示的方向z，导电结构30由重布线层20延伸至重布线层21。重布线层20上设置有电磁屏蔽层201，重布线层21上设置有电磁屏蔽层211，导电结构30连通电磁屏蔽层201和电磁屏蔽层211，从而在芯片10的周围形成由电磁屏蔽层201、导电结构30、电磁屏蔽层211至导电结构30的电磁屏蔽结构，以将芯片10限制于该电磁屏蔽结构内。此外，该电磁屏蔽结构与公共地连接，从而电磁干扰信号通过电磁屏蔽结构传输至共公共地，由此可以降低芯片11、重布线层20上的导电线路以及重布线层21上的导电线路对芯片10的电磁干扰，避免芯片10所处理或传输的信号的畸变，从而提高芯片10的可靠性。或者，类似地，相关电磁屏蔽结构也可减轻芯片10对其他部分，如芯片11的干扰。另外，在重布线20和重布线层21之间、未设置芯片10和导电结构30的区域，被塑封材料40填充，以对芯片10和导电结构30提供保护。塑封材料40例如可以包括环氧树脂(Epoxy Molding Compound,EMC)、聚乙烯、聚丙烯、聚烯烃、聚酰胺、聚亚氨酣中的一种或多种的组合。
重布线层20可以包括多层布线层，图1中示意性的示出了重布线层20包括靠近芯片10的布线层和远离芯片10的布线层该两层布线层。电磁屏蔽层201设置于重布线层20中靠近芯片10的布线层。此外，电磁屏蔽层201向芯片10的正投影至少部分覆盖芯片10，例如，如图所示的全部覆盖芯片10有助于提升电磁屏蔽效果。如图2所示，图2示意性的示出了电磁屏蔽层201的结构以及与芯片10之间的相对位置关系。电磁屏蔽层201包括用于传导上述电磁干扰信号至公共地的导电线路以及隔离导电线路的绝缘材料。该导电线路可以是金属，例如可以包括铜(Cu)、银(Ag)、铝(Al)等中的一种或多种的组合，该绝缘材料可以是有机聚合物材料，该有机聚合物材料可以包括但不限于：聚酰亚胺(PI，Polyimide)、聚苯并唑(ploybenzoxazole，PBO)、苯并环丁烯(BCB)、或者环氧成型模料(Epoxy Molding Compound，EMC)等。优选的，电磁屏蔽层201所形成的图案可以呈如图2所示的网格状。其中，导电线路2011将绝缘材料分成多个网格2012。通常，电磁屏蔽层201中，如果金属导电线路在布线层中占用面积比例过高，会导致布线层的热膨胀系数变大，从而导致芯片处于冷热交替、并且冷热温差较大的环境中，导致芯片由于热胀冷缩产生形变，进而导致芯片因形变过大产生损坏。由此，通过将电磁屏蔽层201所形成的图案设置成网格状，也即避免导电线路2011所占用的电磁屏蔽层201的面积比例过高，从而避免芯片形变或损坏。另外，导电线路2011所占用的电磁屏蔽层201的面积比例过低时，则无法有效的屏蔽电磁干扰信号。因此，优选的，每一个网格沿x方向的宽度或者沿y方向的宽度小于干扰信号波长的1/10，以有效屏蔽干扰信号。请继续参考图1，如图1所示的重布线层20中，除了设置屏蔽层201之外，还设置有用于与芯片10连接的导电线路202。导电线路202可以设置于相较于电磁屏蔽层201远离芯片10一侧的布线层中。重布线层20中还设置有过孔(Via)203，该过孔203中填充或电镀有导电材料，芯片10的引出端通过过孔203与导电线路202连通。
重布线层21也可以包括多层布线层。图1中示意性的示出了重布线层21包括靠近芯片10的布线层和远离芯片10的布线层该两层布线层。电磁屏蔽层211设置于重布线层21中靠近芯片10的布线层。此外，电磁屏蔽层211向芯片10的正投影至少部分覆盖芯片10，例如，如图所示的全部覆盖芯片10有助于提升电磁屏蔽效果。电磁屏蔽层211的结构以及所形成的图案可以与如图2所示的电磁屏蔽层201的结构以及所形成的图案相同，不再详细赘述。重布线层21中，除了设置电磁屏蔽层211之外，还设置有用于与芯片11连接的导电线路212。导电线路212可以设置于相较于电磁屏蔽层211远离芯片10一侧的布线层中。芯片11的引出端与导电线路212连通。需要说明的是，图1中示意性的示出了导电线路212设置于电磁屏蔽层211之上、远离芯片10一侧的布线层中。在其他可能的实现方式中，导电线路212也可以与电磁屏蔽层211设置于同一层布线层中，例如与电磁屏蔽层211之间水平间隔设置且相互隔离。
导电结构30可以为环绕芯片10的连续的结构，也可以为环绕芯片10的不连续的结构。当导电结构30为不连续的结构时，导电结构30例如可以为环绕芯片10的多个导电柱。其中，图3A和图3B为图1所示的扇出型封装结构100去除重布线层21之后的俯视图，图3A示意性的示出了导电结构30为多个导电柱的情况，图3B示意性的示出了导电结构30为连续结构的情况。导电结构30的顶面与屏蔽层211上的导电线路相连接，导电结构30的底面与屏蔽层201上的导电线路相连接，从而形成由电磁屏蔽层201、导电结构30、电磁屏蔽层201至导电结构30的电磁屏蔽结构。扇出型封装结构100中，重布线层20和重布线层21之间除了设置有导电结构30之外，还设置有用于将重布线层20上的导电线路202与重布线层21上的导电线路212连通的导电柱50。导电柱50可以是金属材料形成的金属柱，比如铜柱(copper pillar)、铝柱、银柱或者钯柱等，也可以是其他导电材料形成的柱状体，该柱状体优选为圆柱体，本申请实施例对此不做限定。从而，芯片11的引出端可以通过重布线层21上的导电线路212和导电柱50，与重布线层20上的导电线路202连接，实现芯片11与芯片10的互连。从图1、图3A和图3B中可以看出，导电柱50设置于导电结构30的外围区域，也即导电结构30将导电柱50与芯片10之间隔离开，从而避免扇出型封装结构100通电后，导电柱50上的寄生电容和寄生电感对芯片10造成电磁干扰。另外，如图1所示的重布线层20远离芯片10的表面S1，还包括用于与印刷电路板(PCB，printed circuit board)上的导电线路连接的多个导电凸块204。导电凸块204的材料可以包括但不限于：锡材料或者锡银混合材料等。该多个导电凸块204中包括用于与PCB上的公共地相连接的接地导电凸块，屏蔽层201上的导电线路通过重布线层20上的过孔与该接地导电凸块连通，从而与PCB上的公共地相连接。芯片10的公共地端也可以通过导电线路202与上述接地导电凸块连接；芯片11的公共地端也可以通过导电线路212、导电柱50以及导电线路202与上述接地导电凸块连接。多个导电凸块204中除了上述接地导电凸块之外，其余导电凸块均与重布线层20上的导电线路202连接，芯片10的引出端和芯片11的引出端均通过导电线路202以及导电凸块204与PCB上的导电线路连接。
本申请实施例所示的扇出型封装结构100中，设置于重布线层21之上的芯片11可以为简易封装后的芯片，然后通过表面贴装工艺设置于重布线层21的表面，如图1所 示。在其他可能的实现方式中，芯片11也可以是裸芯片。当芯片11为裸芯片时，芯片11的周围还设置有塑封材料60，如图4所示。在图4所示的扇出型封装结构200中，塑封材料60沉积于重布线层21以及芯片11的表面，以包裹芯片11，从而对芯片11提供支撑和保护。塑封材料60可以是与塑封材料40相同的材料。
本申请实施例中，在图4所示的扇出型封装结构的基础上，当芯片11同样为受电磁干扰影响较大的芯片时，重布线层21中还可以设置有电磁屏蔽层213，如图5所示。在图5所示的扇出型封装结构300中，电磁屏蔽层213设置于重布线层21中、相较于电磁屏蔽层211和导电线路212靠近芯片11的一侧。也即导电线路212设置于电磁屏蔽层211和电磁屏蔽层213之间。电磁屏蔽层213向芯片11的正投影至少部分覆盖芯片11，例如，如图所示的全部覆盖芯片11有助于提升电磁屏蔽效果。电磁屏蔽层213的结构以及所形成的图案可以与如图2所示的电磁屏蔽层201的结构以及所形成的图案可以相同，具体参考图2所示的电磁屏蔽层201的相关描述，不再详细赘述。通过设置电磁屏蔽层213，可以避免扇出型封装结构300工作过程中，芯片10、以及导电线路212上的寄生电容和寄生电感等对芯片11造成电磁干扰，提高芯片11工作的稳定性。
如图1、图4和图5所示的扇出型封装结构中，示出了在重布线层20和重布线层21之间封装有一个芯片。在其他可能的实现方式中，本申请实施例提供的扇出型封装结构中，重布线层20和重布线层21之间也可以设置多个芯片，如图6所示，图6为本申请实施例提供的扇出型封装结构400的一个结构示意图。与以上各实施例所述的扇出型封装结构相比，在图6所示的扇出型封装结构600中，重布线层20和重布线层21之间除了设置有芯片10之外，还设置有芯片12。芯片12与芯片10沿图6中所示的方向x(也即图6所示的水平方向)间隔设置。如图6所示，重布线层20中的导电线路202，既包括与电磁屏蔽层201设置于不同布线层中的导电线路，还包括与电磁屏蔽层201设置于同一布线层中导电线路。与电磁屏蔽层201同层设置的导电线路，设置于电磁屏蔽层201的侧边、并且与电磁屏蔽层201之间互相隔离。从而，芯片10的引出端和芯片12的引出端，通过重布线层20上的过孔，均连接至重布线层20中的导电线路202上，芯片10和芯片12之间通过导电线路202互相连通；此外，芯片10和芯片12还通过重布线层20上的过孔以及导电线路202与导电凸块204连通。另外，重布线层21中的导电线路212，既包括与电磁屏蔽层211设置于不同布线层中的导电线路，还包括与电磁屏蔽层211设置于同一布线层中导电线路；导电线路212通过导电柱50与导电线路202连通，从而芯片11通过导电线路212、导电柱50以及导电线路202，与芯片10和芯片12连通；另外，芯片11还通过导电线路212、导电柱50以及导电线路202，与导电凸块204连通。进一步的，当如图6所示的芯片12受电磁干扰影响较大时，芯片12周围也可以设置类似于芯片10周围由电磁屏蔽层201、电磁屏蔽层211以及导电结构30所组成的电磁屏蔽结构，具体设置方式参考图1中相关结构的描述，不再赘述。还需要说明的是，本申请实施例中，如图1、图4、图5和图6所示的重布线层21上设置有一个芯片。在其他可能的实现方式中，重布线层21之上也可以设置更多个芯片(例如2个或3个等)；另外，在重布线层20和重布线层21之间也可以设置更多个芯片，本申请实施例对此不做具体限定。
基于图1、图4、图5和图6所示的扇出型封装结构，本申请实施例所示的扇出型封装结构所封装的芯片可以包括但不限于：片上系统(System on chip)、存储器(Memory)、分立器件、应用处理芯片(Application Processor,AP)、微机电系统(Micro-Electro-Mechanical System，MEMS)、微波射频芯片、专用集成电路(ApplicationSpecific Integrated Circuit，简称ASIC)等芯片。上述应用处理芯片或专用集成电路在具体应用中可以是中央处理器(Central Processing Unit,CPU)、图像处理器(Graphics Processing Unit,GPU)、人工智能处理器，例如，神经网络处理器(Network Processing Unit，NPU)等。存储器可以是高速缓冲存储器(cache)、随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)或其他存储器。分立器件例如可以包括但不限于例如场效应晶体管、双极性晶体管等。例如，当采用图1、图4或图5所示的扇出型封装结构时，扇出型封装结构中所封装的芯片10可以为模拟芯片(例如分立器件、集成运算放大器、滤波器等)，芯片11可以为数字芯片(例如存储器、处理器等)；再例如，当采用图6所示的扇出型封装结构时，扇出型封装结构中所封装的芯片10和芯片11可以分别为模拟芯片和存储器，芯片12可以为处理器。
如上各实施例所述的扇出型封装结构，可以通过多种扇出型封装工艺制备而成，例如包括但不限于：先芯片正向封装工艺、后芯片正向封装工艺、先芯片倒装工艺或者后芯片倒装工艺。下面以后芯片正向封装工艺为例、以制备出的扇出型封装结构的结构如图1所示为例，结合图7所示的流程700，对制备扇出型封装结构的工艺流程进行详细描述。该工艺流程700包括如下步骤：
步骤701，提供一载板a，在载板a的表面形成重布线层21。本申请实施例中，载板a的材料可以包括但不限于：硅材料、玻璃材料或者二者混合材料等，载板a可以是晶圆级或板级的尺寸。载板a的表面涂布有键合胶。在涂布有键合胶的表面沉积绝缘材料。然后，可以采用光刻、显影、刻蚀、沉积和电镀等一种或多种标准工艺，在绝缘材料上制备多层布线层，以及连通布线层与绝缘材料表面的过孔，从而形成重布线层21。该步骤后所形成的结构如图8A所示，从图8A中可以看出，每一层布线层包括图案化的导电线路。其中，远离载板a的重布线层上所形成的导电线路为图2所示的网格状，该网格状的导电线路与网格内的绝缘材料形成电磁屏蔽层211；过孔11由绝缘材料的表面延伸至远离载板a的重布线层上，与电磁屏蔽层211上的导电线路连通；过孔12由绝缘材料的表面延伸至靠近载板a的重布线层上，与靠近载板a的重布线层上的导电线路212连通。过孔中可以沉积或者电镀导电材料。
步骤702，在重布线层21上形成导电结构30以及导电柱50。该步骤中，首先利用气相沉积(例如物理气相沉积或者化学气相沉积)的方法在重布线层21的表面沉积金属材料。该金属材料可以包括但不限于：铜、铝、银、金等材料或者金属的合金材料等。接着，在金属材料的表面沉积光刻胶。然后，采用光刻和显影等标准工艺，利用掩模版刻蚀金属材料，在重布线层21的表面、用于设置芯片10的区域(也即电磁屏蔽层211向重布线层21的表面的正投影所覆盖的区域)周围的区域，形成与过孔11连通的导电结构30。如图8B所示。该导电结构30可以为环绕用于设置芯片10的区域的多个导电柱，也可以为环绕用于设置芯片10的区域的连续的导电结构，其基于掩模板的图案确 定。另外，可以采用同一个掩模版，通过同一道光刻和显影工序，在重布线层21的表面、导电结构30的外围区域形成有多个导电柱50。该多个导电柱50与过孔12连通。
步骤703，将芯片10的背面贴装于重布线层21的表面。该步骤中，可以通过绝缘介质(例如绝缘胶)等物料将芯片10的背面贴装于重布线层21上。其中，芯片10设置于导电结构30所限定出的区域之内，如图8C所示。芯片10的有源面暴露在外面。
步骤704，在重布线层21上、芯片10、导电结构30以及导电柱50的间隙填充绝缘材料40。首先，在重布线层21暴露的表面以及芯片10的表面沉积绝缘材料40。然后，采用平坦化工艺对塑封材料进行处理，以暴露出芯片10的有源面、导电结构30的表面以及导电柱50的表面。该步骤后所形成的结构如图8D所示。
步骤705，在暴露出的芯片10的有源面、导电结构30的表面、导电柱50的表面以及芯片10的表面形成重布线层20。该步骤中，可以采用光刻、显影、刻蚀、沉积和电镀等一种或多种标准工艺，在由芯片10的有源面、导电结构30的表面、导电柱50的表面以及芯片10的表面所形成的水平面上，制备多层布线层以及连通布线层与芯片10的有源面、布线层与导电结构30、布线层与导电柱50的过孔，从而形成重布线层20。该步骤后所形成的结构如图8E所示，从图8E中可以看出，每一层布线层包括图案化的导电线路。其中，靠近芯片10的重布线层呈现的图案为图2所示的网格状，网格状的导电线路与网格内的绝缘材料形成电磁屏蔽层201，电磁屏蔽层201通过过孔与导电结构30连通，远离芯片10的重布线层上所形成的导电线路202通过过孔与多个导电柱50连通。
步骤706，在重布线层20远离芯片10的表面沉积多个用于与PCB焊接的导电凸块204。其中，导电线路202还通过过孔与导电凸块204连接。从而，芯片10的引出端通过过孔以及导电线路202与导电凸块204连通。该步骤后所形成的结构如图8F所示
步骤707，在重布线层20的表面以及导电凸块204上沉积临时键合胶13，以覆盖导电凸块204。
步骤708，在临时键合胶13上贴装载板b。该步骤后如所形成的结构图8G所示。
步骤709，去除载板a，以暴露出重布线层21的表面。
步骤710，刻蚀重布线层21，以形成多个用于连通重布线层21的表面与导电线路212的过孔。
步骤711，将芯片11倒装于重布线层21的表面。从而，芯片11的引出端与重布线层21上的导电线路212连通。芯片11的引出端通过重布线层21中的过孔以及导电线路212、导电柱50、重布线层20上的过孔以及导电线路202与芯片10连通。该步骤后如所形成的结构图8H所示。
步骤712，将载板b和临时键合胶13移除。
经过步骤701-步骤712，可以制备出如图1所示的扇出型封装结构。
进一步的，在制备出如图1所示的扇出型封装结构100的基础上，当需要制备如图4所示的扇出型封装结构200时，在上述步骤711之后、步骤712之前，还包括如下步骤：在芯片11的背面以及重布线层21暴露出的表面上沉积绝缘材料60，以对芯片11提供支撑和保护。当需要制备如图5所示的扇出型封装结构时，在上述步骤701所形成 的重布线层21中，还包括在靠近载板a的重布线层上形成电磁屏蔽层213，该电磁屏蔽层213通过重布线层21中的过孔与电磁屏蔽层211连通。当需要制备如图6所示的扇出型封装结构时，在上述步骤703中，还包括将芯片12的背面贴装于重布线层21的表面上的步骤；在上述步骤704中，还包括在芯片12的周围填充绝缘材料40的步骤。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (11)

  1. 一种扇出型封装结构，其特征在于，包括：
    第一重布线层，所述第一重布线层中包括与公共地连接的第一电磁屏蔽层；
    第二重布线层，所述第二重布线层中包括与公共地连接的第二电磁屏蔽层；
    第一芯片，设置于所述第一重布线层和所述第二重布线层之间，所述第一电磁屏蔽层和所述第二电磁屏蔽层向所述第一芯片的正投影至少部分覆盖所述第一芯片；
    环绕所述第一芯片的导电结构，沿所述第一芯片的厚度方向，所述导电结构连通所述第一电磁屏蔽层和所述第二电磁屏蔽层；
    第一塑封材料，所述第一塑封材料填充于所述第一重布线层和所述第二重布线层之间、未设置所述第一芯片和所述导电结构的区域，用于包裹所述第一芯片。
  2. 根据权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括第二芯片，沿所述第一芯片的厚度方向，所述第二芯片设置于所述第一重布线层之上。
  3. 根据权利要求2所述的扇出型封装结构，其特征在于，
    所述第一重布线层还包括与所述第一芯片连接的第一导电线路；
    所述第二重布线层还包括与所述第二芯片连接的第二导电线路；
    所述第一重布线层和所述第二重布线层之间还设置有多个导电柱，所述多个导电柱设置于所述导电结构的外围区域；
    所述第一导电线路和所述第二导电线路之间通过所述多个导电柱连通。
  4. 根据权利要求3所述的扇出型封装结构，其特征在于，所述第一导电线路包括被所述第一电磁屏蔽层的投影至少部分覆盖的第三导电线路，所述第三导电线路和所述第一电磁屏蔽层设置于所述第一重布线层中的不同层，所述第一电磁屏蔽层相对于所述第三导电线路设置于靠近所述第一芯片的一侧。
  5. 根据权利要求3或4所述的扇出型封装结构，其特征在于，所述第二导电线路包括被所述第二电磁屏蔽层的投影至少部分覆盖的第四导电线路，所述第四导电线路和所述第二电磁屏蔽层设置于所述第二重布线层中的不同层，所述第二电磁屏蔽层相对于所述第四导电线路设置于远离所述第一芯片的一侧。
  6. 根据权利要求3-5任一项所述的扇出型封装结构，其特征在于，所述第一重布线层还包括第三电磁屏蔽层，所述第三屏蔽层与所述第一导电线路以及所述第一电磁屏蔽层均不同层设置；
    相对于所述第一导电线路以及所述第一电磁屏蔽层，所述第三电磁屏蔽层设置于靠近所述第二芯片的一侧。
  7. 根据权利要求2-6任一项所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括第二塑封材料；
    所述第二塑封材料包裹所述第二芯片。
  8. 根据权利要求3-7任一项所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括第三芯片，所述第三芯片设置于所述第一重布线层和所述第二重布线层之 间、所述导电结构的外围区域，并被所述第一塑封材料所包裹；
    所述第三芯片通过所述第二导电线路与所述第一芯片连通。
  9. 根据权利要求1-8任一项所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括多个导电凸块；
    所述多个导电凸块设置于所述第二重布线层上、远离所述第一芯片的表面；
    所述多个导电凸块中包括用于与印刷电路板上的公共地相连接的接地导电凸块，所述第一电磁屏蔽层上的导电线路和所述第二电磁屏蔽层上的导电线路与所述接地导电凸块连接。
  10. 一种扇出型封装结构的制备方法，其特征在于，所述制备方法包括：
    提供一载板，在所述载板上形成第一重布线层，所述第一重布线层中包括与公共地连接的第一电磁屏蔽层；
    在所述第一重布线层上形成导电结构；
    在所述第一重布线层的表面、导电结构所环绕的区域，贴装第一芯片；
    在所述第一重布线层的表面之上、所述第一芯片与所述导电结构的间隙填充第一塑封材料；
    在所述第一芯片的有源面、所述导电结构的表面以及所述第一塑封材料的表面之上形成第二重布线层，所述第二重布线层中包括与公共地连接的第二电磁屏蔽层，所述第二电磁屏蔽层通过所述导电结构与所述第一电磁屏蔽层连通；
    移除所述载板。
  11. 根据权利要求10所述的制备方法，其特征在于，所述移除所述载板之后，所述制备方法还包括：
    在暴露出的所述第一重布线层之上贴装第二芯片。
PCT/CN2021/127671 2021-10-29 2021-10-29 扇出型芯片封装结构和制备方法 WO2023070581A1 (zh)

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CN106129020A (zh) * 2015-05-05 2016-11-16 联发科技股份有限公司 半导体封装结构
CN107248509A (zh) * 2017-07-14 2017-10-13 中芯长电半导体（江阴）有限公司 Emi防护的芯片封装结构及封装方法
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CN111933591A (zh) * 2020-09-22 2020-11-13 甬矽电子(宁波)股份有限公司 扇出型电磁屏蔽封装结构和封装方法

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