TW201705362A - 具有堆疊通孔的重佈線 - Google Patents

具有堆疊通孔的重佈線 Download PDF

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Publication number
TW201705362A
TW201705362A TW104137131A TW104137131A TW201705362A TW 201705362 A TW201705362 A TW 201705362A TW 104137131 A TW104137131 A TW 104137131A TW 104137131 A TW104137131 A TW 104137131A TW 201705362 A TW201705362 A TW 201705362A
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Taiwan
Prior art keywords
forming
metal trace
dielectric layer
top surface
opening
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TW104137131A
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English (en)
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TWI598997B (zh
Inventor
陳憲偉
黃立賢
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台灣積體電路製造股份有限公司
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Publication of TW201705362A publication Critical patent/TW201705362A/zh
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Publication of TWI598997B publication Critical patent/TWI598997B/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

一種方法包括在導電特徵上形成介電層，在該介電層形成開口，並鍍金屬材料以形成與該導電特徵電耦合的重佈線。該重佈線包括開口處的通孔以及金屬跡線。該金屬跡線包括直接位於該通孔上的第一部分，以及與該通孔偏離的第二部分。該第一部分的第一頂表面與該金屬跡線的該第二部分的第二頂表面本質上共面。

Description

具有堆疊通孔的重佈線
本揭露涉及具有堆疊通孔的重佈線。
隨著半導體技術的演進，半導體晶片/晶粒變得越來越小。同時，能需要將更多的功集成到半導體晶粒中。因此，半導體晶粒需要將越來越多的若干I/O接合墊裝入更小的區域，I/O接合墊的密度隨著時間快速上升。這樣，半導體晶粒的封裝變得更加困難，對封裝件的產量產生不利地影響。
傳統的封裝技術可以分為兩類。在第一類中，在切割之前封裝晶圓上晶粒。這種封裝技術具有一些有利特點，例如，更大的吞吐量和更低的成本。而且，需要更少的底層充填材料充或成型模料。然而，這種封裝技術也具有一些缺點。晶粒的尺寸變得越來越小，各個封裝件僅可以為扇入型的封裝件，其中每一晶粒的I/O接合墊限於直接位於各個晶粒的表面之上的區域。伴隨著受到限制的晶粒區域，I/O接合墊的數量因I/P接合墊的間距而受到限制。如果接合墊的間距減少，可能發生焊橋。此外，在固定的球尺寸的要求下，焊球必須具有一定大小，這將接著限制能夠在晶粒的表面上封裝的焊球的數目。
在另一類封裝技術中，晶粒在封裝之前從晶圓切割。這種封裝技術的有利特點是有可能形成扇出封裝件，這意味著晶粒上的I/O接合墊可以重佈在比晶粒更大的區域，從而可以增加封裝在晶粒表面上 的I/O接合墊的數目。這種封裝技術的另一個有利特點在於封裝“已知的良好晶粒”，丟棄有缺陷的晶粒，從而不會將成本和精力浪費在有缺陷的晶粒上。
根據本揭露的一些實施例，一種方法包括：在導電特徵上形成介電層，在該介電層形成開口，以及電鍍金屬材料以形成與該導電特徵電耦合的重佈線。該重佈線包括該開口處的通孔；以及金屬跡線。該金屬跡線包括直接位元於該通孔上的第一部分，以及與該通孔偏離的第二部分。該第一部分的第一頂表面與該金屬跡線的該第二部分的第二頂表面本質上共面。
根據本揭露的另外一些實施例，一種方法包括：在導電特徵上形成第一介電層，在該第一介電層形成第一開口，該導電特徵的一部分通過該第一開口暴露，電鍍包括第一通孔和第一金屬跡線的第一重佈線。該第一通孔位於該第一開口中。該第一金屬跡線其包括直接位於該第一通孔上的第一部分，以及與該第一通孔偏離的第二部分。該方法更包括在該第一金屬跡線上形成第二介電層，在該第二介電層中形成第二開口，該第一金屬跡線的該第一部分的第一頂表面通過該第二開口暴露，以及電鍍第二重佈線。該第二重佈線包括第二通孔和第二金屬跡線。該第二通孔位於該第二開口中，並且包括與該第一重佈線的該第一頂表面接觸的底表面。該第二金屬跡線包括直接位於該第二通孔上的第三部分以及與該第二通孔偏離的第四部分。
根據本揭露的另外一些實施例，一種方法包括：在封裝材料中封裝裝置晶粒，執行平坦化操作以暴露該裝置晶粒的金屬柱，形成覆蓋該裝置晶粒和該封裝材料的第一聚合物層，在該第一聚合物層中形成第一開口以暴露該金屬柱，以及形成包括第一通孔和第一金屬跡線 的第一重佈線。該第一通孔在該第一開口中。該第一金屬跡線在該第一聚合物層上。該方法更包括在該第一重佈線上形成第二聚合物層，在該第二聚合物層中形成第一開口陣列以暴露該第一重佈線，電鍍包括第一通孔陣列和第二金屬跡線的第二重佈線。該第一通孔陣列位於該第一開口陣列中。該第二金屬跡線位於該第一通孔陣列上並與該第一通孔陣列接觸。該方法更包括在該第二重佈線上形成第三聚合物層，在該第三聚合物層中形成第二開口陣列以暴露該第二重佈線；以及電鍍包括第二通孔陣列和第三金屬跡線第三重佈線。該第二通孔陣列位於該第二開口陣列中，其中該第二通孔陣列中的每一通孔以一一對應的方式覆蓋該第一通孔陣列中通孔的一者。第三金屬跡線位於該第二通孔陣列上並與該第二通孔陣列接觸。
20‧‧‧PoP封裝件
30‧‧‧載體
32‧‧‧粘合層
34‧‧‧介電層
40‧‧‧導電種晶層
42‧‧‧光罩層
44‧‧‧開口
46‧‧‧貫穿通孔
48‧‧‧裝置晶粒
50‧‧‧晶粒附接膜
51‧‧‧介電層
52‧‧‧封裝材料
54‧‧‧金屬柱
56‧‧‧介電層
56A‧‧‧頂表面
58‧‧‧開口
60‧‧‧種晶層
70A‧‧‧金屬跡線
70B‧‧‧通孔
72‧‧‧介電層
74‧‧‧開口
76‧‧‧重佈線
76A‧‧‧金屬跡線
76A2‧‧‧金屬跡線
76B‧‧‧通孔
76C‧‧‧重佈線
76D‧‧‧重佈線
76E‧‧‧重佈線
78‧‧‧介電層
80‧‧‧開口
82‧‧‧電連接器
84‧‧‧晶圓級封裝
86‧‧‧切割膠帶
87‧‧‧底膠填充
62‧‧‧圖案化光罩
64‧‧‧重佈線
64A‧‧‧金屬跡線
64A1‧‧‧頂表面
64A’‧‧‧金屬跡線部分
64A”‧‧‧金屬跡線部分
64B‧‧‧通孔
64B1‧‧‧頂表面
66‧‧‧介電層
68‧‧‧開口
70‧‧‧重佈線
88‧‧‧開口
89‧‧‧雷射束
90‧‧‧焊接區域
184‧‧‧封裝件
300‧‧‧封裝件
302‧‧‧基板
304‧‧‧裝置晶粒
△H‧‧‧高度差
T1‧‧‧厚度
T2‧‧‧厚度
Wv1‧‧‧通孔尺寸
當閱讀隨附的附圖時，從以下詳細的描述可以最清楚地理解本發明的各個方面。需要強調的是，根據本行業的標準做法，不是按比例繪製各個特徵。事實上，各個特徵的尺寸可以任意增大或減小以便進行清楚的討論。
圖1至圖21圖式說明根據一些實施例的形成封裝件的中間階段的剖面圖；圖22A、22B、22C和22D圖式說明根據一些實施例的重佈線的複數個剖面圖；圖23圖式說明根據一些實施例的形成封裝件的製程流程圖。
如下公開提供了很多不同的實施例或示例，用於實施所提供的主題的不同特徵。如下描述了元件和佈置的具體示例，以簡化本揭露。當然，它們僅僅是示例，並不是旨在限制本發明。例如，以下描 述中在第二特徵之上或在第二特徵上形成第一特徵可以包括形成直接接觸的第一特徵和第二特徵的實施例，還可以包括在第一特徵和第二特徵之間可以形成附加特徵從而使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本公開可以在各個示例中重複使用符號和/或字母。這種重複使用用於簡化和清楚的目的，其本身並不表明所述的各個實施例和/或配置之間的關係。
而且，空間關係術語，例如“之下”、“下方”、“下面”、“之上”、“上方”等，在此用於簡化描述附圖所示的一個單元或特徵對另一個單元或特徵的關係。除了附圖中描寫的方向，空間關係術語旨在包含使用或操作的裝置的不同方向。設備可以以其他方式定向(旋轉90度或者在其他方向)，並可以據此同樣地解釋本文所使用的空間關係描述語。
根據各種示例性實施例，提供一種堆疊式封裝(pack-on-package，PoP)結構/封裝件以及形成封裝件的方法。討論一些實施例的變形。貫穿各個附圖和說明性實施例，類似的參考編號被用於指定類似的元件。需要注意的是，儘管封裝件的形成作為一個示例，但是很容易將本揭露的教示用於其他積體電路元件的形成，例如，晶圓/晶粒、內插器、封裝基板等。
圖1至圖21示出了根據一些實施例的形成封裝件的中間階段的剖面圖。在隨後的討論中，參照圖23中的製程步驟討論圖1至圖21所示的製程步驟。
參照圖1，提供一載體30，並在載體30上佈置一粘合層32。載體30可以是空白玻璃載體、空白陶瓷載體等，且可以具有圓形俯視形狀的半導體晶圓的形狀。載體30有時被稱為載體晶圓。儘管可以使用其他類型的粘合劑，粘合層32可由例如光熱轉換(Light-to-Heat Conversion，LTHC)材料形成。根據本揭露的一些實施例，粘合層32 能夠在光熱下分解，從而能夠從其上形成的結構釋放載體30。
參照圖2，在粘合層32上形成一介電層34。該對應步驟如圖23的製程流程中的步驟202所示。根據本揭露的一些實施例，介電層34為聚合物形成的聚合物層，其可以是光敏聚合物，例如，聚苯並惡唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide)等。根據一些實施例，介電層34由諸如氮化矽的氮化物、諸如二氧化矽的氧化物、磷矽玻璃(PhosphoSilicate Glass，PSG)、硼矽玻璃(BoroSilicate Glass，BSG)、摻硼磷矽玻璃(Boron-doped PhosphoSilicate Glass,BPSG)等形成。
參照圖3，在介電層34上通過(例如)物理氣相沉積(physical vapor deposition，PVD)形成一導電種晶層40。該對應步驟如圖23的製程流程中的步驟206所示。導電種晶層40可以是金屬種晶層，包括銅、鋁、鈦及它們的合金或它們的多層。根據本揭露的一些實施例，導電種晶層40包括諸如鈦層的第一金屬層(未示出)以及在第一金屬層上的諸如銅層的第二金屬層(未示出)。根據本揭露的另外的實施例，導電種晶層40包括諸如銅層的單個金屬層，其可以由本質上為純銅或銅合金形成。
圖4至圖7示出了貫穿通孔的形成。如圖4所示，光罩層42(例如光阻)應用於導電種晶層40上，然後使用光學微影光罩進行圖案化。該對應步驟如圖23的製程流程中的步驟208所示。根據本揭露的一些實施例，光罩層42由乾膜形成，其層積在導電種晶層40上。根據一些實施例，光罩層42由旋轉塗布法形成。由於圖案化(暴露並顯影)，開口44在光罩層42中形成，通過開口44暴露導電種晶層40的一些部分。光罩層42的厚度被選為接近隨後放置的裝置晶粒48(圖8)的厚度。根據本揭露的一些實施例，光罩層42的厚度大於裝置晶粒48的厚度。
如圖5所示，通過電鍍在開口44中形成貫穿通孔46，電鍍可以為電鍍或無電鍍。該對應步驟如圖23的製程流程中的步驟210所示。貫穿通孔46被鍍在導電種晶層40的暴露部分。貫穿通孔46是導電的，且可以是包括銅、鋁、鎢、鎳或它們的合金的金屬通孔。貫穿通孔46的俯視圖形狀包括但不限於矩形、正方形、圓形等。貫穿通孔46的高度由隨後放置的裝置晶粒48(圖8)的厚度確定，根據本揭露的一些實施例，貫穿通孔46的高度稍稍大於或等於裝置晶粒48的厚度。
在電鍍貫穿通孔46後，移除光罩層42，所產生的結構如圖6所示。該對應步驟如圖23的製程流程中的步驟212所示。這樣，暴露了先前被光阻42覆蓋的導電種晶層40的部分。
接下來，如圖7所示，執行蝕刻步驟以移除導電種晶層40所暴露的部分，其中蝕刻可以是非等向性或等向性的蝕刻。該對應步驟如圖23的製程流程中的步驟212所示。另一方面，被貫穿通孔46覆蓋的導電種晶層40的部分保持不被蝕刻。在整個描述中，導電種晶層40剩餘的下面部分被稱為貫穿通孔46的底部部分。儘管導電種晶層40顯示為與上覆蓋的貫穿通孔46的部分具有可區分的介面，當形成導電種晶層40的材料與形成各自上覆蓋的貫穿通孔46的材料類似或相同時，部分或者所有導電種晶層40可以與貫穿通孔46合併，它們之間沒有可區分的介面。例如，導電種晶層40的銅層可以與貫穿通孔46合併而沒有可區分的介面。根據另外的實施例，導電種晶層40與相應上覆蓋的貫穿通孔46的電鍍部分存在可區分的介面。例如，導電種晶層40的鈦層可以與含銅貫穿通孔46區分開。由於對導電種晶層40進行蝕刻，暴露介電層34。
圖8示出將裝置晶粒48放置在介電層34上。該相應步驟如圖23的製程流程中的步驟214所示。裝置晶粒48通過晶粒附接膜50(為粘合膜)附著到介電層34。晶粒附接膜50的邊緣與裝置晶粒48的邊緣毗連 (對準)。需要理解的是，儘管示出了一個裝置晶粒48，但是存在放置在介電層34上的多個裝置晶粒48。多個放置的裝置晶粒48可以經佈置為包括多個行和多個列的陣列。裝置晶粒48可以包括半導體基板，其具有與相應下面的晶粒附接膜50實體接觸的背表面(朝下的表面)。裝置晶粒48在半導體基板的前表面(朝上的表面)更包括積體電路裝置(例如，有源裝置，包括諸如電晶體，未示出)。裝置晶粒48可以為邏輯晶粒，例如，中央處理單元(central processing unit，CPU)晶粒、圖形處理單元(graphic processing unit，GPU)晶粒、行動應用晶粒等。
裝置晶粒48可以包括接近其頂表面的金屬柱54。金屬柱54電耦合至裝置晶粒48內的積體電路(例如電晶體)。根據本揭露的一些示例性實施例，如圖8所示，金屬柱54被介電層51覆蓋，介電層51的頂表面高於金屬柱54的頂表面。介電層51進一步延伸至金屬柱54之間的間隙中。根據本揭露的另外的實施例，金屬柱54的頂表面與相應的介電層51的頂表面共面。根據一些示例性實施例，介電層51可以由諸如PBO的聚合物形成。金屬柱54可以為銅柱，並且還可以包括諸如鋁、鎳等的其他導電/金屬材料。
參照圖9，封裝材料52被封裝在裝置晶粒48和貫穿通孔46上。該對應步驟如圖23的製程流程中的步驟216所示。封裝材料52填充相鄰裝置晶粒48之間的間隙，圍繞每一裝置晶粒48。封裝材料52可以包括成形化合物、模底膠填充、環氧樹脂或者樹脂。在封裝製程後，封裝材料52的頂表面高於金屬柱54以及貫穿通孔46的頂端。
接下來，執行諸如化學機械拋光(chemical mechanical polish，CMP)步驟或研磨步驟的平坦化步驟以平整封裝材料52，直到暴露貫穿通孔46。該對應步驟如圖23的製程流程中的步驟216所示。所產生的結構如圖10所示。裝置晶粒48的金屬柱54由於平坦化也被暴露。由 於平坦化，貫穿通孔46的頂表面與金屬柱54的頂表面本質上處於同一水平(共面)，並且與封裝材料52的頂表面本質上處於同一水平(共面)。
圖11至圖18示出了前端RDL以及相應介電層的形成。參照圖11，形成介電層56。該對應步驟如圖23的製程流程中的步驟218所示。根據本揭露的一些實施例，介電層56由有機材料形成，其可以為諸如PBO、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)等的聚合物。根據一些實施例，介電層56由無機材料形成，例如，氮化矽、二氧化矽等。介電層56可以作為流體噴塗，然後固化。根據一些實施例，介電層56由預形成膜形成，並被層壓。在介電層56中形成開口58以暴露貫穿通孔46和金屬柱54。開口58可以通過執行光學微影製程而形成。
同樣如圖11所示，形成種晶層60，其包括延伸至開口58的部分(圖11)以及介電層56上的部分。種晶層60可以包括鈦層以及鈦層上的銅層。或者，種晶層60包括銅層而沒有鈦層。可以使用例如物理氣相沉積(physical vapor deposition，PVD)形成種晶層60。
接下來，參照圖12，在種晶層60上形成圖案化光罩62。根據一些實施例，圖案化光罩62由光阻形成，被圖案化以暴露種晶層60的一些部分。接下來，執行電鍍步驟以在圖案化光罩62的開口中形成重佈線(redistribution lines，RDL)64，其中諸如銅的金屬材料被電鍍在種晶層60所暴露的部分。該對應步驟如圖23的製程流程中的步驟220所示。RDL 64連接至金屬柱54和貫穿通孔46。RDL 64包括介電層56上的金屬跡線(包括金屬線和/金屬接合墊)64A。RDL 64更包括開口58(圖11)中的通孔64B。種晶層60被所鍍材料覆蓋的部分也被認為是RDL 64的部分。在電鍍之後，移除圖案化光罩62，顯現出下方部分的種晶層60。然後蝕刻顯現出下方部分的種晶層60，留下如圖13 所示的RDL 64。
根據本揭露的一些實施例，電鍍過程是受控制的，並且通孔64B的尺寸是選定的，從而使得RDL 64的頂表面是平坦的或本質上平坦的。圖22A、22B、22C和22D示出了通孔64B和相應連接的金屬跡線64A的一些示例性剖面圖。在這些示例中，金屬跡線64A包括與通孔64B偏離的(不直接位於通孔64B之上)金屬跡線部分64A’。金屬跡線部分64A’的頂表面64A1是平坦的，而通孔64B以及上面覆蓋的金屬跡線部分(64A”)可能具有不同的輪廓。圖22A示出共形RDL 64。RDL 64的不同部分(包括通孔64B和金屬跡線64A)具有相同(或本質上相同)的厚度T1。因此，通孔64B的頂表面64B1的最低點以高度差△H低於頂表面64A1，高度差△H等於介電層56的厚度T2。
圖22B示出了RDL 64的輪廓，其包括具有凹槽的金屬跡線64A和金屬跡線64A下的通孔64B。金屬跡線64A包括直接位於通孔64B上的部分64A”以及高於通孔64B但與64B偏離的部分64A’。金屬跡線部分64A”的頂表面64B1的最低點的中心從金屬跡線部分64A’的頂表面64A1凹入。高度差△H小於介電層56的厚度T2，並且可以小於厚度T1。在這些實施例中，頂表面64B1的最低點也可以高於介電層56的頂表面56A。
圖22C示出了RDL 64的輪廓，其包括具有隆起的金屬跡線64A和直接位於隆起下的通孔64B。金屬跡線部分64A”的頂表面64B1的中心高於金屬跡線部分64A’的頂表面64A1。隆起的最高點與頂表面64A1之間的高度差△H大於約0.5μm，並且可以大於約1μm。
圖22D示出了RDL 64的輪廓，其頂表面金屬跡線部分64A’和64A”彼此共面或本質上共面。根據本揭露的這些實施例，由於RDL 64具有本質上共面的頂表面，金屬跡線部分64A”的頂表面64B1的最高點(如果為隆起)或最低點(如果為凹槽)與金屬跡線部分64A’的 頂表面64A1之間的高度差△H(如果有)小於約1μm，並且可以小於約0.5μm。需要注意的是，RDL 64的頂表面是否被認為是(本質上上)平坦的與金屬跡線部分64A’的厚度T1有關，並且厚度T1越小，如果被認為是平坦的或本質上平坦的，所需要的高度差△H越小。在整個描述中，術語“本質上平坦”表示高度差△H小於厚度T1的20%或更小。術語“本質上平坦”也可以表示高度差△H小於厚度T1的10%或5%或更小，這取決於佈線要求。例如，當厚度T1約為2μm時，△H需要小於0.4μm或更低；而當厚度約為4μm時，△H需要小於約0.8μm。根據本揭露的一些實施例，平坦的RDL頂表面是電鍍的結果，沒有使用諸如化學機械拋光(chemical mechanical polish，CMP)或研磨的平坦化操作來實現平坦的頂表面。
根據本揭露的一些實施例，可以組合調整各種因素以獲得如圖22D所示的輪廓，其中RDL 64具有平坦的或本質上平坦的頂表面。例如，可以減少通孔尺寸Wv1(可以為長度或寬度)來獲得平坦的RDL頂表面。應該能夠理解，如果通孔尺寸Wv1太大，可以形成如圖22A所示的輪廓。隨著通孔尺寸Wv1的減小，可以獲得如圖22B所示的輪廓。但是，如果通孔尺寸太小，在通孔64B可以不理想地形成隆起(圖22C)、接縫或氣隙。因此，通孔尺寸需要在一定的範圍內。根據一些示例性實施例，為了獲得如圖22D所示的平坦頂表面，通孔尺寸Wv1可以小於約10μm。通孔尺寸Wv1也可以小於約7μm並大於約4μm。
影響RDL 64頂表面輪廓的其他因素包括鍍RDL 64(圖12)的鍍速(每單位時間增加的厚度)。低鍍速可以導致如圖22A所示的共形RDL 64。當鍍速增加時，可以獲得圖22B所示的輪廓。進一步增加鍍速可以導致圖22D所示的平坦的頂表面。在一些實施例中，進一步增加鍍速能夠引起如圖22C所示的隆起。根據一些示例性實施例，鍍速 在約0.1μm/min(微米/分鐘)至約1.0μm/min的範圍內。鍍速可以通過調整鍍電流進行測量(以及控制)，其中電流是通過各自的電鍍液實施的。在一些示例性實施例中，為了形成具有平坦頂表面的RDL，電流高於約2.0安培每平方分米(amps per square decimeter，ASD)。除了這些因素，諸如RDL 64厚度的其他因素也影響RDL 64的輪廓。應當意識到，各種因素的組合影響RDL 64的頂表面輪廓，可以通過實驗找出用於選定RDL的最佳通孔尺寸和鍍速。
參照圖13，根據一些實施例，在RDL 64上形成介電層66。該對應步驟如圖23的製程流程中的步驟222所示。介電層66可以通過從形成介電層56的相同備選材料中選擇材料而形成，並且可以通過塗佈或層壓形成。如圖14所示，介電層66中形成開口68以暴露RDL 64。
接下來，執行電鍍步驟，這一步驟的執行類似於圖12中RDL 64的形成。這樣，形成RDL 70，如圖15所示。該對應步驟如圖23的製程流程中的步驟224所示。RDL 70包括金屬跡線70A和通孔70B。類似的，當採用不同的通孔尺寸和/或不同的鍍速時，RDL 70有可能具有不同的頂表面輪廓。根據本揭露的一些實施例，如參照圖22B至圖22D所討論的，選擇諸如通孔70B尺寸以及鍍速的形成因素，從而使得RDL 70的頂表面本質上共面。
圖15示出了堆疊通孔，其中一些通孔70B與下面相應的通孔64B垂直地對準(直接位於其上)。當下面的RDL具有平坦的頂表面時，上面的RDL 70的頂表面不凹入或凸出，即使它們直接位於下面的通孔之上。如果下面的RDL 64具有如圖22A、22B或22C所示的輪廓，上面的RDL 70的輪廓可能受影響，直接位於通孔64B上的RDL 70的部分的頂表面或者凹入或者凸出。當更多的通孔直接堆疊在已經堆疊好的通孔上時，凹入效應或凸出效應可能越來越嚴重，最終凹入或凸出引起形貌可以導致上面的(或頂部)RDL破裂。在本揭露的一些實施 例中，通過使得RDL 64和70的頂表面平坦，能夠消除這樣的問題。
參照圖16，根據各種實施例，在RDL 70上形成介電層72。該對應步驟如圖23的製程流程中的步驟226所示。介電層72可以通過從形成介電層56的相同備選材料中選擇材料而形成，並且可以通過塗佈或層壓形成。然後，如圖16所示，在介電層72中形成開口74。
接下來，執行電鍍步驟，這一步驟的執行類似於圖12中RDL 64的形成。這樣，形成RDL 76(包括76C、76D和76E)，如圖17所示。該對應步驟如圖23的製程流程中的步驟228所示。RDL 76包括金屬跡線76A和通孔76B。根據本揭露的一些實施例，如參照圖22B至圖22D所討論的，選擇通孔7BB尺寸以及鍍速，從而使得RDL 76的頂表面本質上共面。
圖17進一步示出了將更多的通孔76B直接堆疊在已經堆疊好的通孔70B和64B上。而且，一些通孔76B連接至相同的金屬跡線76A。例如，如圖17所示，三個所示的通孔76B連接至相同的金屬跡線76A1，而兩個所示的通孔76B連接至相同的跡線76A2。根據一些實施例，通孔76B可以形成陣列(例如，2×2陣列，2×3陣列，或3×3陣列)。每一通孔76B可以一一對應的方式與通孔70B的一者對齊。需要理解的是，在一個晶片中，可能需要不同的通孔尺寸。例如，用於導電的通孔(例如VDD)由於更高的電流可能需要比信號通孔更大。然而，通孔尺寸的增加可能導致相同晶片上各個RDL具有不同的輪廓(圖22A至圖22D)，因此，使得堆疊通孔容易出現如前所述的通孔凹入或凸出引起的問題。在本揭露的實施例中，一旦需要更大的通孔，更大的通孔被分成更小的通孔，從而使得相同介電層(整個同一封裝件)中所有通孔的尺寸本質上均勻。例如，在整個所示的封裝件中，相同層面的通孔的尺寸範圍為期望通孔尺寸的約80%至約120%。
參照圖18，在RDL 76上形成介電層78。介電層78可以通過從形 成介電層56的相同備選材料中選擇材料而形成，並且可以通過塗佈或層壓形成。然後，在介電層78中形成開口80。
圖19示出了根據本揭露一些示例性實施例形成電連接器82。該對應步驟如圖23的製程流程中的步驟230所示。電連接器82點耦合至RDL 64/70/76、金屬柱54和/或貫穿通孔46。電連接器82的形成可以包括將焊球放置在RDL 76上，然後回焊焊球。根據本揭露的另外的實施例，電連接器82的形成包括執行電鍍步驟以在RDL 76上形成焊接區域，然而回焊該焊接區域。根據一些實施例，焊膏印刷製程用於形成電連接器82。電連接器82更包括金屬柱，或金屬柱與焊帽，其也可以通過電鍍形成。在整個描述中，包括裝置晶粒48、貫穿通孔46、封裝材料52、RDL 64/70/76、介電層56/66/72的組合結構被稱為晶圓級封裝84，其為包括多個裝置晶粒48的複合晶圓。
圖19示出了三個RDL層。根據一些實施例，根據各個封裝件的佈線要求，可以為單個RDL層、兩個RDL層或超過三個RDL層。
接下來，封裝件84從載體30(圖19)剝離。根據一個示例性脫離過程，切割膠帶86(圖20)附著至封裝件84以保護電連接器82，其中，切割膠帶86固定至切割架(未示出)。例如，通過射出UV光或雷射至粘合層32(圖19)執行剝離。例如，當粘合層32由LTHC形成時，由光或雷射產生的熱使得LTHC分解，從而載體30從晶圓級封裝件84脫離。所產生的結構如圖20所示。
圖20示出了用於在介電層34中形成開口88的圖案化。該對應步驟如圖23的製程流程中的步驟232所示。例如，當介電層34是聚合物層時，其能夠使用雷射鑽(通過雷射束89)圖案化以移除覆蓋貫穿通孔46的部分，從而通過開口88暴露貫穿通孔46。
在導電種晶層40的一部分由鈦形成的實施例中，也可以移除導電種晶層40的鈦層。例如，氟化氫(Hydrogen Fluoride，HF)氣體或 稀釋的HF溶液可以用於蝕刻鈦。暴露導電種晶層40中的銅，因此可以在其上形成隨後形成的背面RDL或諸如焊接區域的電連接器。
在隨後的步驟中，如圖20所示，將封裝件84切割為多個封裝件184，每一者包括裝置晶粒48的(至少)一個和相應的貫穿通孔46。該對應步驟如圖23的製程流程中的步驟234所示。
圖21示出將封裝件300接合至封裝件184，於是形成PoP封裝件20。該對應步驟如圖23的製程流程中的步驟236所示。封裝件300和184也被分別稱為PoP封裝件20的頂封裝件和底封裝件。在如圖21所示的示例性實施例中，封裝件184中沒有示出背面RDL，而背面RDL可以根據另外的實施例形成。接合是通過焊接區域90執行的，其將貫穿通孔46連接至上面覆蓋的封裝件300的金屬接合墊。根據本揭露的一些實施例，封裝件300包括裝置晶粒304，其可以為記憶體晶粒，例如，靜態隨機記憶體(static random access memory，SRAM)晶粒，動態隨機記憶體(dynamic random access memory，DRAM)晶粒等。在一些實施例中，記憶體晶粒也可以接合至封裝件基板302。在將頂封裝件300接合至底封裝件184後，底膠填充87填入頂封裝件300和底封裝件184之間的間隙，然後固化。
本揭露的一些實施例具有一些有利特徵。通過形成帶有通孔的RDL以及頂表面彼此本質上共面的RDL，更多的通孔可以直接堆疊在下面的通孔之上，而不用考慮高形貌引起的問題。這具有兩個有利特點。第一，如果不使用本揭露的實施例，上面覆蓋的通孔可能必須與下面的通孔偏離，以防止隨著RDL數目的增加，形貌變得越來越嚴重。在本揭露的一些實施例中，可以堆疊通孔，從而節省晶片區域。RDL可以彼此鄰近放置。第二，通過堆疊通孔，能夠縮短信號路徑，因此能夠減少由延長信號路徑引起的副作用，例如寄生電容。這對於高頻信號尤其有好處。
前面所述概括了幾個實施例的特徵，使得本領域技術人員可更好地理解本揭露的各個方面。本領域技術人員應該明白他們可以將本揭露當作基礎，用來設計或修改用於執行相同目的和/或獲得在此介紹的實施例的相同好處的其他過程和結構。本領域技術人員也可意識到這樣等同的構造並不脫離本揭露的精神和保護範圍，並且在不脫離本揭露的精神和保護範圍的情況下，他們可以在此做各種改變、替換和修改。
30‧‧‧載體
32‧‧‧粘合層
34‧‧‧介電層
46‧‧‧貫穿通孔
48‧‧‧裝置晶粒
50‧‧‧晶粒附接膜
51‧‧‧介電層
52‧‧‧封裝材料
54‧‧‧金屬柱
56‧‧‧介電層
64‧‧‧重佈線
66‧‧‧介電層

Claims (10)

  1. 一種方法，其包括：在一導電特徵上形成一第一介電層；在該第一介電層形成一第一開口；以及電鍍一金屬材料以形成與該導電特徵電耦合的一第一重佈線，其中該第一重佈線包括：在該第一開口處的一第一通孔；以及一第一金屬跡線，包括直接位於該第一通孔上的第一部分，以及與該第一通孔偏離的一第二部分，其中該第一部分的第一頂表面與該第一金屬跡線的該第二部分的一第二頂表面本質上共面。
  2. 如請求項1所述的方法，更包括：在該第一金屬跡線上形成一第二介電層；在該第二介電層中形成一第二開口，通過該第二開口暴露該第一金屬跡線的該第一部分；以及電鍍一額外的金屬材料以形成第二重佈線，其中該第二重佈線包括：在該第二開口中的一第二通孔，其中，該第二通孔包括與該第一頂表面接觸的一底表面；以及一第二金屬跡線，包括直接位於該第二通孔上的第三部分，以及與該第三通孔偏離的一第四部分，其中該第三部分的一第三頂表面與該第二金屬跡線的該第四部分的一第四頂表面本質上共面。
  3. 如請求項1所述的方法，其中不在該第一金屬跡線上執行平坦化。
  4. 如請求項1所述的方法，更包括：在一封裝材料中封裝一裝置晶粒，其中該第一介電層與該裝置晶粒和該封裝材料均重疊。
  5. 一種方法，其包括：在一導電特徵上形成一第一介電層；在該第一介電層形成一第一開口，該導電特徵的一部分通過該第一開口暴露；電鍍一第一重佈線，其包括：該第一開口中的一第一通孔；以及一第一金屬跡線，其包括直接位於該第一通孔上的一第一部分，以及與該第一通孔偏離的一第二部分；在該第一金屬跡線上形成一第二介電層；在該第二介電層中形成一第二開口，該第一金屬跡線的該第一部分的一第一頂表面通過該第二開口暴露；以及電鍍一第二重佈線，其包括：該第二開口中的一第二通孔，其中，該第二通孔包括與該第一重佈線的該第一頂表面接觸的一底表面；以及一第二金屬跡線，包括直接位於該第二通孔上的一第三部分，以及與該第二通孔偏離的一第四部分。
  6. 如請求項5所述的方法，其中，該第一頂表面與該第一金屬跡線的該第二部分的第二頂表面本質上共面，並且其中在形成該 第一金屬跡線的過程中在該第一重佈線上沒有執行平坦化。
  7. 如請求項5所述的方法，其中，該第一重佈線包括該第一介電層中的一第一通孔陣列，該第一通孔在該第一通孔陣列中，並且該第二重佈線包括該第二介電層中的一第二通孔陣列，該第二通孔在該第二通孔陣列中，且其中該第二通孔陣列中的每個通孔以一一對應的方式直接位於該第一通孔陣列的通孔的一者之上。
  8. 一種方法，其包括：在一封裝材料中封裝一裝置晶粒；執行一平坦化操作以暴露該裝置晶粒的一金屬柱；形成重疊該裝置晶粒和該封裝材料兩者的一第一聚合物層；在該第一聚合物層中形成一第一開口以暴露該金屬柱；形成第一重佈線，其包括該第一開口中的一第一通孔，以及該第一聚合物層上的一第一金屬跡線；在該第一重佈線上形成一第二聚合物層；在該第二聚合物層中形成一第一開口陣列以暴露該第一重佈線；電鍍一第二重佈線，其包括：該第一開口陣列中的一第一通孔陣列；以及位於該第一通孔陣列上並與該第一通孔陣列接觸的第二金屬跡線；在該第二重佈線上形成一第三聚合物層；在該第三聚合物層中形成一第二開口陣列以暴露該第二重佈線；以及 電鍍一第三重佈線，其包括：該第二開口陣列中的一第二通孔陣列，其中該第二通孔陣列中的每一通孔以一一對應的方式重疊該第一通孔陣列中通孔的一者；以及位於該第二通孔陣列上並與該第二通孔陣列接觸的第三金屬跡線。
  9. 如請求項8所述的方法，其中該第一重佈線之電鍍包括：在該第一聚合物層上形成一種晶層；在該種晶層上形成圖案化光罩；在該圖案化光罩的開口中並在該種晶層上電鍍該第一重佈線；移除該圖案化光罩；以及移除被所移除的該圖案化光罩覆蓋的該種晶層部分。
  10. 如請求項8所述的方法，其中，在電鍍後，該第二重佈線的整個頂表面是本質上平坦的。
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