TWI654734B - 堆疊型半導體封裝 - Google Patents

堆疊型半導體封裝

Info

Publication number
TWI654734B
TWI654734B TW104109627A TW104109627A TWI654734B TW I654734 B TWI654734 B TW I654734B TW 104109627 A TW104109627 A TW 104109627A TW 104109627 A TW104109627 A TW 104109627A TW I654734 B TWI654734 B TW I654734B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
conductive layer
stacked
sealing resin
semiconductor element
Prior art date
Application number
TW104109627A
Other languages
English (en)
Other versions
TW201537719A (zh
Inventor
宮腰武
細山田澄和
熊谷欣一
近井智哉
中村慎吾
松原寬明
作元祥太朗
Original Assignee
日商吉帝偉士股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商吉帝偉士股份有限公司 filed Critical 日商吉帝偉士股份有限公司
Publication of TW201537719A publication Critical patent/TW201537719A/zh
Application granted granted Critical
Publication of TWI654734B publication Critical patent/TWI654734B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明之一實施型態之堆疊型半導體封裝，具有第一電路基板、第一半導體封裝、第二電路基板、第二半導體封裝、密封樹脂、導電層及散熱導孔。第一半導體封裝之一第一半導體元件安裝於第一電路基板。第二半導體封裝之一第二半導體元件安裝於第二電路基板，且第二半導體封裝堆疊於第一半導體封裝。密封樹脂密封第一半導體元件。導電層接觸配置於密封樹脂。散熱導孔係與導電層連接且配置於第一電路基板上。

Description

堆疊型半導體封裝
本發明關於半導體封裝(package)之安裝技術。特別是於堆疊型半導體封裝中，關於為了減輕從下側封裝朝向上側封裝之熱量傳遞之構成。
近年來，隨著電子基器的小型化、高密度化及加速半導體元件之存取速度(access speed)等需求，使用著堆疊多個半導體封裝之封裝上封裝(package on package，POP)(例如「日本專利公開案2010-153651號公報」)。於行動電話及智慧型手機等攜帶型終端中，會使用一種半導體封裝，其中包含執行影像處理之邏輯晶片(logic chip)之封裝位於下側，包含記憶晶片(memory chip)之封裝位於上側。
如此之堆疊型半導體封裝中，晶片間的距離接近1毫米(mm)以下的程度，而有從下側的邏輯晶片所發出的熱量傳遞至上側的記憶晶片且導致上側的記憶晶片作動不良的情形。因此，冀求減輕從下側封裝朝向上側封裝之熱量傳遞。
本發明之目的，在於堆疊型半導體封裝中，提供減輕從下側晶片朝向上側晶片之熱量傳遞之半導體封裝。
本發明之一實施型態之堆疊型半導體封裝，包含第一電路基板、第一半導體封裝、第二電路基板、第二半導體封裝、密封樹脂、導電層及散熱導孔。第一半導體封裝之一第一半導體元件安裝於第一電路基板。第二半導體封裝之一第二半導體元件安裝於第二電路基板，且第二半導體封裝堆疊於第一半導體封裝。密封樹脂密封第一半導體元件。導電層接觸配置於密封樹脂。散熱導孔係與導電層連接且配置於第一電路基板上。
其中，導電層亦可配置於密封樹脂之上。
其中，第一半導體封裝亦可包括多個接合用電極端子，多個接合用電極端子亦可與第二半導體封裝連接且配置於第一半導體元件之周圍，導電層亦可配置於多個接合用電極端子之內側。
其中，導電層之材質亦可為銅或銅合金。
其中，散熱導孔亦可配置於接合用電極端子之更內側。
其中，多個接合用電極端子亦可包括一樹脂芯球。
其中，導電層亦可配置於第一半導體封裝之側面。
其中，密封樹脂亦可覆蓋導電層。
其中，導電層亦可於第一半導體元件之上配置介有一黏著劑或一間隔件(spacer)。
其中，導電層亦可為一具二層以上之配線基板。
其中，堆疊型半導體封裝亦可更包括一通孔(via)。 通孔亦可配置於具二層以上之配線基板及密封樹脂，第一電路基板及第二電路基板之間亦可介有通孔以彼此電性連接。
其中，通孔亦可配置於密封樹脂，第一電路基板及第二電路基板之間亦可介有具二層以上之配線基板之電路以彼此電性連接。
再者，本發明之一實施型態之堆疊型半導體封裝，包含一第一電路基板、一第一半導體封裝、一第二電路基板、一第二半導體封裝、一密封樹脂及一斷熱層。第一半導體封裝之一第一半導體元件安裝於第一電路基板。第二半導體封裝之一第二半導體元件安裝於第二電路基板，且第二半導體封裝堆疊於第一半導體封裝。密封樹脂密封第一半導體元件。斷熱層接觸配置於密封樹脂。
10‧‧‧第一半導體封裝
11‧‧‧第一電路基板
12‧‧‧第一半導體元件
12a‧‧‧虛線
13‧‧‧密封樹脂
14‧‧‧導電層
14a‧‧‧虛線
15‧‧‧散熱導孔
16‧‧‧通孔
17‧‧‧接合用電極端子
18‧‧‧配線
19‧‧‧導電部件
20‧‧‧第二半導體封裝
21‧‧‧第二電路基板
22‧‧‧第二半導體元件
23‧‧‧密封樹脂
31‧‧‧焊料球
32‧‧‧樹脂芯球
34‧‧‧連接線
35‧‧‧焊料球
50‧‧‧區域
60‧‧‧斷熱層
70‧‧‧配線基板
100‧‧‧堆疊型半導體封裝
第1圖為關於本發明之實施型態1之堆疊型半導體封裝之剖面圖。
第2圖為關於本發明之實施型態1之堆疊型半導體封裝之概略俯視圖。
第3圖為關於本發明之實施型態1之堆疊型半導體封裝之概略俯視圖。
第4圖為關於本發明之實施型態1之變形例1之堆疊型半導體封裝之概略俯視圖。
第5圖為關於本發明之實施型態1之變形例2之堆疊型半導體封裝之剖面圖。
第6圖為關於本發明之實施型態1之變形例2之堆疊型半導體封裝之剖面圖。
第7圖為關於本發明之實施型態2之堆疊型半導體封裝之剖面圖。
第8圖為關於本發明之實施型態2之堆疊型半導體封裝之概略俯視圖。
第9圖為關於本發明之實施型態3之堆疊型半導體封裝之剖面圖。
第10圖為關於本發明之實施型態4之堆疊型半導體封裝之剖面圖。
第11圖為關於本發明之實施型態5之堆疊型半導體封裝之剖面圖。
第12圖為關於本發明之實施型態5之堆疊型半導體封裝之概略俯視圖。
第13圖為關於本發明之實施型態6之堆疊型半導體封裝之剖面圖。
第14圖為關於本發明之實施型態6之堆疊型半導體封裝之概略俯視圖。
以下，將參照圖式說明關於本發明之堆疊型半導體 封裝。然而，本發明之堆疊型半導體封裝能夠以多種不同的態樣實施，而並非限定解釋成以下所示之實施型態之記載內容。而且，以本實施型態所參照之圖式中，同一部分或具有同樣功能之部分將附上相同符號，且將省略如此反覆的說明。
<實施型態1>
關於本發明之實施型態1之堆疊型半導體封裝100之概要，將一邊參照第1圖至第3圖一邊詳細地說明。
〔堆疊型半導體封裝之基本構成〕
第1圖繪示關於本發明之實施型態1之堆疊型半導體封裝100於第3圖中A-A’剖面之剖面圖。參照第1圖，可知第一半導體封裝10及第二半導體封裝20之間介有焊料球31以彼此接合，而令第二半導體封裝20堆疊於第一半導體封裝10之上。
第一半導體封裝10具有第一電路基板11，且一第一半導體元件12配置於第一電路基板11上。第一電路基板11可由一層或多層配線基板構成，第1圖中所繪示的是四層的。雖可例如將應用處理器(application processor)等配置為第一半導體元件12，但並非限定於此。而且，第1圖中，第一半導體元件12雖繪示一個半導體元件，但亦可於第一電路基板11上配置多個半導體元件做為第一半導體元件12。
為了覆蓋第一電路基板11及第一半導體元件12，而配置密封樹脂13。密封樹脂13能夠保護第一半導體元件12及第一電路基板11之上部避免外部水分或雜質混入，且防止第一 電路基板11翹曲。使用者能夠使用環氧樹脂(epoxy resin)、氰酸酯樹脂(cyanate ester resin)、丙烯酸樹脂(acrylic resin)、聚醯亞胺樹脂(polyimide resin)及矽氧樹脂(silicone resin)等做為密封樹脂13。
密封樹脂13之中，配置有多個通孔(via)16。通孔16之下端與配置於第一電路基板11上之電極銜接，通孔16之上端從密封樹脂13露出而做為接合用電極端子17。接合用電極端子17其上配置有焊料球31，以與配置於第二半導體封裝20之第二電路基板21下側之電極連接。亦即，通孔16電性連接第一半導體封裝10之第一電路基板11之配線及第二半導體封裝20知第二電路基板21之配線。通孔16可例如藉由此方法形成：於密封樹脂13預定的位置蝕刻形成開口部，並以金屬鍍敷或蝕刻等方式於開口部埋入金屬材料，且與配置於第一電路基板11上之電極銜接。
第二半導體封裝20具有由一層或多層配線基板構成之第二電路基板21，且一第二半導體元件22配置於第二電路基板21上。第二半導體元件22可用由銀或銅等材料製成之連接線(bonding wire)34與第二電路基板21電性連接。使用者可例如將FLASH及SDRAM等之記憶體配置為第二半導體元件22。亦可將多個相同種類或不同種類之記憶體並排配置於第二電路基板21上，而做為第二半導體元件22。另外，亦可將多個記憶體堆疊配置而做為第二半導體元件22。
為了覆蓋第二電路基板21及第二半導體元件22，而配置密封樹脂23。密封樹脂23能夠由與上述密封樹脂13同樣之材質所構成。而且，第二電路基板21之下側配置有與第二電路基板21之配線電性連接之電極。因第二電路基板21之下側之電極與第一半導體封裝10之接合用電極端子17以焊料球31連接，故第一電路基板11及第二電路基板21之各自的配線介有焊料球31以彼此電性連接。第一電路基板11之下側配置有電極，而與安裝堆疊型半導體封裝100之外部安裝基板之間介有配置於此電極之焊料球35以彼此連接。
〔為了減輕從下側之半導體元件朝向上側之半導體元件之熱量傳遞的構成〕
本發明之實施型態1之堆疊型半導體封裝100，係將導電層14及散熱導孔15配置於第一半導體封裝10。
第2圖繪示關於本發明之實施型態1之堆疊型半導體封裝100中，從上側觀看第一半導體封裝10之俯視圖。參照第2圖，多個接合用電極端子17上下左右各二列地配置於矩形的第一半導體封裝10之外周周圍。而且，如上所述，因接合用電極端子17位於通孔16(圖未繪示)的上端，故通孔16表示成以與接合用電極端子17同樣的配置。而可知導電層14係以被配置於第一半導體封裝10之外周附近之多個接合用電極端子17圍繞之方式，配置於多個接合用電極端子17之內側的區域。
第3圖為關於本發明之實施型態1之堆疊型半導體 封裝100中，從上側觀看第一半導體封裝10之俯視圖，且為穿透導電層14而繪示第一半導體元件12之平面位置之圖。以虛線14a圍繞之部分，表示配置導電層14之位置。另外，以虛線12a圍繞之部分，表示配置第一半導體元件12之位置。
參照第3圖，可知導電層14會以完全覆蓋第一半導體元件12所配置之部分的方式，配置成比第一半導體元件12所配置之部分更寬廣的大小。因第一半導體元件12具有矩形的形狀，且因導電層14配置成包圍第一半導體元件12之矩形形狀，故配置有導電層14而未配置第一半導體元件12之區域50形成為中空的矩形形狀。
散熱導孔15配置於區域50。參照第3圖，散熱導孔15雖配置於區域50之各頂點附近及各邊的中央附近之合計8個位置，但散熱導孔15所配置的個數及於區域50內之位置並非限定於此。
再次參照第1圖，可知導電層14形成於密封樹脂13之表面，亦即第一半導體封裝10之上側表面。此外，導電層14配置於第一半導體封裝10之外周附近之接合用電極端子17(通孔16)的更內側，且配置成比第一半導體元件12所配置之區域更寬廣的區域。散熱導孔15配置於配置有導電層14但未配置第一半導體元件12之區域50，且散熱導孔15之上部連接於導電層14之下側的表面。導電層14由熱傳導率高的部件製成，例如亦可使用銅或銅合金。舉例而言，以形成密封樹脂13之後於 欲形成導電層14之位置之樹脂去除，做為導電層14之形成方法。樹脂之去除方法可為機械性及化學性的，沒有特別限定的方法。之後，於所去除的凹部填充銅漿並加以固化，或者亦可用導電性黏著劑設置於與散熱導孔接觸之表面，而於凹部配置接合金屬製的板狀部件之方式形成導電層14。
散熱導孔15形成於密封樹脂13及第一電路基板11。散熱導孔15之形成方法，例如亦可先於第一電路基板11形成通孔，形成密封樹脂13之後，於密封樹脂13之預定位置，以與上述通孔16同樣的方法形成。因此，形成於第一電路基板11之通孔及形成於密封樹脂13之通孔，二者並非必要直接連接，二者之間亦可介有金屬部件或配線等。第1圖中，形成於第一電路基板11之通孔及形成於密封樹脂13之通孔之間，介有配線18。散熱導孔15之下端，亦即形成於第一電路基板11之通孔的下端，延伸至配置於第一電路基板11之下側導電部件19。導電部件19配置有焊料球35，且經由焊料球35而與堆疊型半導體封裝100之外部連接。
藉由本發明之實施型態1之堆疊型半導體封裝100，第一半導體元件12所產生的熱能夠藉由導電層14及散熱導孔15於第一半導體封裝10之下側逸散。因來自第一半導體元件12所產生的熱之一部分能夠傳遞熱量至第一半導體封裝10之下側，故能夠減輕從第一半導體元件12朝向配置於第一半導體封裝10之上側之第二半導體封裝20之第二半導體元件22之熱 量傳遞，而能夠抑制第二半導體元件22之作動不良的情形。
〔變形例1〕
關於本發明實施型態1之堆疊型半導體封裝100之變形例1，將一邊參照第4圖一邊詳細說明。
於上述實施型態1之說明中，雖說明區域50之形狀為中空的矩形形狀，但區域50之形狀並非限定於此。第2圖及第3圖中，接合用電極端子17(通孔16)於第一半導體封裝10之周邊部分配置成內側及外側之二列。相對於此，參照第4圖，是採用將第2圖及第3圖中內側的通孔16之一部分置換為散熱導孔15之構成。第4圖中，區域50之外側的形狀雖為凹凸狀，亦可為波浪狀。
藉由具有上述構成，能夠確保配置第一半導體元件12之空間更為寬廣。再者，因第一半導體元件12及散熱導孔15之間的距離能夠縮短，故第一半導體元件12所產生的熱能夠更有效果地經由導電層14及散熱導孔15朝向第一半導體封裝10之下側傳遞熱量。
〔變形例2〕
關於本發明實施型態1之堆疊型半導體封裝100之變形例2，將一邊參照第5圖及第6圖一邊詳細說明。
於上述實施型態1之說明中，說明導電層14使用如銅或銅合金等之熱傳導率高的部件。然而，本發明實施型態1之堆疊型半導體封裝100中之導電層14，並非限定於如上所述之單 一部件之構成。如第5圖及第6圖所示，能夠將具二層以上之配線基板70配置為導電層14。此場合中，第一半導體封裝10之上面整體亦可例如配置為具二層以上之配線基板。
變形例2中，第一半導體封裝10及第二半導體封裝20之間的連接可採取各種型態。參照第5圖時，可知配置於第一半導體封裝10之上面之具二層以上之配線基板70及密封樹脂13配置有通孔16，通孔16之上端及配置於第二電路基板21之下側之電極以焊料球31連接。或者如第6圖所示，可知配線基板70未配置通孔，配線基板70之下側的端子與配置於密封樹脂13之通孔16之上端連接，配線基板70之上側的端子與配置於第二電路基板21之下側之電極以焊料球31連接。此場合中，亦可於配線基板70之內部佈設配線，以令第一半導體封裝10及第二半導體封裝20之所希望的端子電性連接。
<實施型態2>
關於本發明之實施型態2之堆疊型半導體封裝100之概要，將一邊參照第7圖及第8圖一邊詳細地說明。
第7圖繪示發明之實施型態2之堆疊型半導體封裝100之剖面圖。雖然第7圖與第1圖類似，但導電層14係以不與接合用電極端子17連接之方式，配置於第一半導體封裝10之配置有接合用電極端子17之周邊部，且更配置到第一半導體封裝10之側面，於這些要點與第1圖相異。
導電層14亦可配置於第一半導體封裝10之側面， 亦即密封樹脂13及第一電路基板11之側面。如上所述，矩形形狀之第一半導體封裝10之側面存有四表面，導電層14以配置於全部四個側面為佳。延伸至側面之導電層14之形成方法，例如亦可於形成密封樹脂13之後，將黏著劑設置於與密封樹脂13接觸之表面，而於密封樹脂13及第一電路基板11之側面配置．接合金屬製的板狀部件，藉以形成導電層14。
第8圖繪示關於本發明之實施型態2之堆疊型半導體封裝100中，從上側觀看第一半導體封裝10之俯視圖。參照第8圖時，可知導電層14配置於第一半導體封裝10之上側的整體表面。然而，導電層14與接合用電極端子17之間介有密封樹脂13，而令導電層14及接合用電極端子17不會電性連接。如第8圖所示，可知導電層14配置延伸至第一半導體封裝10之外緣，配置於第一半導體封裝10之上面及側面之導電層14於第一半導體封裝10之外緣部分彼此連接。
如上所述，藉由實施型態2之堆疊型半導體封裝100，導電層除了配置於第一半導體封裝10知上面，還配置於側面。藉由此構成，第一半導體元件12所產生的熱不僅能夠藉由導電層14及散熱導孔15於第一半導體封裝10之下側逸散，還能藉由配置於第一半導體封裝10之側面之導電層14於側面傳遞熱量。因此，更能夠減輕從第一半導體封裝10之第一半導體元件12朝向第二半導體封裝20之第二半導體元件22之熱量傳遞，而能夠抑制第二半導體元件22之作動不良的情形。
而且，從朝向第一半導體封裝10之側面傳遞熱量的觀點來看，配置於側面之導電層14之面積以寬廣為佳。另外，配置於第一半導體封裝10之側面之導電層14之下端，若與安裝堆疊型半導體封裝100之安裝基板等連接，則因從側面的導電層14能夠朝向此安裝基板傳遞熱量而為佳。
<實施型態3>
關於本發明之實施型態3之堆疊型半導體封裝100之概要，將一邊參照第9圖一邊詳細地說明。
第9圖繪示發明之實施型態3之堆疊型半導體封裝100之剖面圖。雖然第9圖與第1圖類似，但第一半導體封裝10及第二半導體封裝20藉由樹脂芯球32連接，於此要點與第1圖相異。
於於第1圖中，第一半導體元件12所產生之熱之一部分經由焊料球31朝向第二半導體封裝20之第二半導體元件22傳遞熱量。實施型態3中，於第一半導體封裝10及第二半導體封裝20之連接處使用比焊料球31之熱傳導率低之樹脂芯球32。藉由如此之構成，第一半導體元件12所產生的熱不僅能夠藉由導電層14及散熱導孔15於第一半導體封裝10之下側逸散，還能夠減輕從第一半導體封裝10及第二半導體封裝20之連接部分朝向第二半導體元件22之熱量傳遞。
<實施型態4>
關於本發明之實施型態4之堆疊型半導體封裝100 之概要，將一邊參照第10圖一邊詳細地說明。
第10圖繪示發明之實施型態4之堆疊型半導體封裝100之剖面圖。雖然第10圖與第1圖類似，但與實施型態2同樣地令導電層14配置到第一半導體封裝10之側面以及與實施型態3同樣地令第一半導體封裝10及第二半導體封裝20藉由樹脂芯球32連接，於此些要點與第1圖相異。藉由具有實施型態4之構成，而能合併有實施型態2及實施型態3所說明之效果。
<實施型態5>
關於本發明之實施型態5之堆疊型半導體封裝100之概要，將一邊參照第11圖及第12圖一邊詳細地說明。
第11圖繪示發明之實施型態5之堆疊型半導體封裝100之剖面圖。雖然第11圖與第1圖類似，但導電層14並非形成於密封樹脂13之表面，而是形成於密封樹脂13之內部，於此要點相異。
導電層14例如使用金屬製之板狀部件。導電層14例如藉由銀漿等之黏著劑而配置於第一半導體元件12之上。或者，導電層14例如藉由矽膠(silicone)等之間隔件而配置於第一半導體元件12之上。於第一半導體元件12之上配置導電層14之後，再藉由密封樹脂13將導電層14埋入密封樹脂13之中。再者，於密封樹脂13預定的位置藉由蝕刻等方式形成散熱導孔15用之開口部，並藉由蝕刻移除一部分導電層14。藉由於開口部埋入金屬材料而形成散熱導孔15，且埋入密封樹脂13中之導 電層14與散熱導孔15連接。
第12圖繪示關於本發明之實施型態5之堆疊型半導體封裝100中，從上側觀看第一半導體封裝10之俯視圖。
藉由實施型態5之堆疊型半導體封裝100，因第一半導體元件12及導電層14緊密配置，而能夠令導電層14直接對第一半導體元件12所產生的熱傳遞熱量，且能夠經由散熱導孔15更有效地將熱量傳遞於第一半導體封裝10之下側。藉此，更能夠減輕從第一半導體封裝10之第一半導體元件12減朝向第二半導體封裝20之第二半導體元件22之熱量傳遞，而能夠抑制第二半導體元件22之作動不良的情形。
<實施型態6>
關於本發明之實施型態6之堆疊型半導體封裝100之概要，將一邊參照第13圖及第14圖一邊詳細地說明。
第13圖繪示發明之實施型態6之堆疊型半導體封裝100之剖面圖。比較第13圖與第1圖，第1圖雖於第一半導體封裝10之上面形成導電層14，但第13圖則是配置斷熱層60，於此要點相異。而且，第13圖中，並未配置第1圖中之散熱導孔15，於此要點也相異。
斷熱層60可例如使用無機絕緣膜等之具有低熱傳導率特性之樹脂。相對於密封樹脂13之熱傳導率約為0.6〔W/mK〕，使用於斷熱層60之具有低熱傳導率特性之樹脂之熱傳導率約為0.2〔W/mK〕。因斷熱層60的熱傳導率低於密封樹脂13之熱 傳導率，故第一半導體元件12所產生的熱會朝向密封樹脂13之橫向傳遞熱量。藉此，因能夠增加經由密封樹脂13之側面及位於密封樹脂13之下側之第一電路基板11朝向第一半導體封裝10之下側所傳遞之熱量，故能夠減輕從第一半導體封裝10之第一半導體元件12減朝向第二半導體封裝20之第二半導體元件22之熱量傳遞，而能夠抑制第二半導體元件22之作動不良的情形。
第14圖繪示關於本發明之實施型態6之堆疊型半導體封裝100中，從上側觀看第一半導體封裝10之俯視圖。比較第8圖及第14圖，第8圖中導電層1以4不與接合用電極端子17接觸之方式配置於第一半導體封裝10之整體表面，相對地第14圖中，斷熱層60與接合用電極端子17接觸且配置於第一半導體封裝10之整體表面，於此要點二者相異。
如上所述，因斷熱層60使用具有絕緣性的樹脂，而亦可與接合用電極端子17銜接。因此，第一半導體封裝之形成方法中，能夠於配置密封樹脂13之後，於密封樹脂13之上的整體表面配置斷熱層60，並能夠就此於預定位置形成開孔(hole)以配置通孔16。
<模擬>
以下，將描述解析模擬關於習知技術之POP與對應本發明之實施型態1、實施型態2及實施型態5之實施例1~3之散熱效果之結果。
〔比較例〕
比較例之解析對象為習知技術之上下二層之POP。上段封裝為216針腳(pin)之球柵陣列封裝(ball grid array，BGA)，晶片尺寸為10.0〔mm〕×10.0〔mm〕×0.10〔mmt〕，發熱量為1.5〔W〕。另外，下段封裝為312針腳之BGA，晶片尺寸為7.0〔mm〕×7.0〔mm〕×0.08〔mmt〕，發熱量為2.5〔W〕。再者，以固態技術協會(JEDEC)之標準四層基板(101.5〔mm〕×114.5〔mm〕×1.6〔mmt〕)做為安裝基板，環境溫度為攝氏25度，解析參數為Tj，即各晶片之最高溫度〔攝氏度〕。上段封裝之基板為二層，如防焊層(solder resist，SR)：0.03，銅層：0.02，芯層：0.05，銅層：0.02，SR：0.03，層厚為0.15〔mm〕。上段封裝的基板及晶片以連接線連接，連接線之線直徑為18〔μm〕，平均長度為1.5〔mm〕，數量為300條，材質為銅。上段封裝之樹脂模造(mold)之厚度為0.4〔mm〕，熱傳導率為0.6〔W/mK〕。上段封裝之基板之內配線層所覆蓋之部分的比例為頂部(L1)：30%及底部(L2)：40%。下段封裝之基板為四層，如SR：0.03，銅層：0.02，芯層：0.05，銅層：0.02，芯層：0.06，銅層：0.02，芯層：0.05，銅層：0.02，SR：0.03，層厚為0.3〔mm〕。下段封裝之基板及晶片中，其凸塊(bump)之尺寸為27×49〔μm〕，厚度為43〔μm〕，數量為742針腳，材質為銅(厚度30μm)加SnAg(厚度13μm)，SnAg與基板連接。下段封裝之樹脂模造，厚度為0.25〔mm〕，熱傳導率為0.6〔W/mK〕。下段封裝之基板之內配線層所覆蓋之部分的比例為頂部(L1)：30 %，L2：80%，L3：80%、底部(L4)：40%。連接上段封裝及下段封裝之焊料球的厚度為0.02〔mm〕，連接下段封裝及安裝基板之焊料球的厚度為0.2〔mm〕，各焊料球之熱傳導率為64.2〔W/mK〕。
〔實施例1〕
實施例1對應於本發明之實施型態1，於下段封裝的上面配置有導電層。導電層之面積為10.0〔mm〕×10.0〔mm〕，厚度為0.05〔mm〕，材質為銅(熱傳導率為390〔W/mK〕)。另外，散熱導孔的直徑為0.15〔mm〕，材質為銅，以間距0.4〔mm〕而於下段封裝之晶片周邊及於通孔16之內側之一圈完整地配置共計96個。其他的構成與比較例相同。
〔實施例2〕
實施例2對應於本發明之實施型態2，下段封裝之上面及側面配置有導電層，且側面之導電層與安裝基板連接。除了配置於側面之導電層連接於安裝基板以外，其餘皆與實施例1相同。
〔實施例3〕
實施例3對應於本發明之實施型態5，於下段封裝之密封樹脂之內部配置導電層，且導電層介有黏著材以與晶片接觸。於此，導電層之尺寸為10.0×10.0×0.1〔mm〕，材質為銅(熱傳導率為390〔W/mK〕)。而且，連接導電層及晶片之黏著劑之厚度為0.01〔mm〕，熱傳導率為60〔W/mK〕，且塗佈於晶片上面之 整體。其他的構成與實施例1相同。
〔解析結果〕
表1中，表示解析關於比較例、實施例1、實施例2及實施例3之散熱效果之結果。於此，Tj為晶片之最高溫度，θJA為以θJA=(Tj-Ta)/Power之關係式表達之熱抵抗，Ta為環境溫度(攝氏25度)，Power為上段晶片及下段晶片之合計消費電力4〔W〕。θJA變化率表示相較比較例之熱抵抗及各實施例之熱抵抗之變化率。
參照表1時，可知各實施例中之最高溫度Tj及熱抵抗θJA，皆低於比較例，而能夠抑制從下段封裝所產生的熱朝向上段封裝之熱量傳遞。實施例1(於封裝的上面配置導電層)之上段晶片中之θJA變化率為-9.9%。藉由配置導電層及散熱導孔，由於下段封裝之晶片所產生的熱能夠傳遞熱量至封裝下側，而考量到此效果。另外，比較實施例1(於封裝的上面配置導電層)及實施例2(於封裝的上面及側面配置導電層，且側面的導 電層與安裝基板連接)之上段晶片中之θJA變化率，實施例1的是-9.9%，實施例2的是-18.1%，表示實施例2能夠得到低於實施例1之二倍熱抵抗。藉由實施例2中封裝之側面配置有導電層且連接至安裝基板，由於下段封裝之晶片所產生的熱不僅經由散熱導孔還從側面的導電層朝向下側傳遞熱量，而考量到此效果差距。
比較實施例1及實施例3(於下段封裝之密封樹脂之內部配置導電層，且導電層介有黏著材以與晶片接觸)之上段晶片之θJA變化率，實施例1的是-9.9%，實施例3的是-10.2%，故實施例3被認為較實施例1更具有若干改善效果。而且，比較下段晶片之θJA變化率，實施例1的是-15.1%，實施例3的是-18.7%，故關於下段晶片之θJA變化率則是實施例3被認為較有改善效果。
以上，參照第1圖至第14圖說明本發明之實施型態1至實施型態6，且藉由模擬驗證效果。其中，本發明並非限定於上述之實施型態，在不脫離要旨的範圍中能夠予以適當變更。

Claims (13)

  1. 一種堆疊型半導體封裝，包括：一第一電路基板；一第一半導體封裝，其中一第一半導體元件安裝於該第一電路基板；一第二電路基板；一第二半導體封裝，其中一第二半導體元件安裝於該第二電路基板，且該第二半導體封裝堆疊於該第一半導體封裝；一密封樹脂，密封該第一半導體元件；一導電層，接觸於該密封樹脂，並配置於該第一半導體元件的上方，且覆蓋該第一半導體元件之一端至另一端；多個接合用電極端子，接合該第一半導體封裝與該第二半導體封裝；以及一散熱導孔(thermal via)，係與該導電層連接並配置於以將該第一半導體元件所產生的熱逸散至該第一半導體封裝之下方的方式所構成的該第一電路基板；其中該些接合用電極端子配置於該第一半導體元件之周圍；該導電層一部分之區域延長至該些接合用電極端子之區域，該散熱導孔取代該些接合用電極端子之一部分而配置。
  2. 如請求項1所述之堆疊型半導體封裝，其中該導電層配置於該密封樹脂之上。
  3. 如請求項2所述之堆疊型半導體封裝，其中該導電層配置於該些接合用電極端子之內側。
  4. 如請求項1所述之堆疊型半導體封裝，其中該導電層之材質為銅或銅合金。
  5. 如請求項2所述之堆疊型半導體封裝，其中該散熱導孔配置於該些接合用電極端子之內側。
  6. 如請求項2所述之堆疊型半導體封裝，其中該些接合用電極端子包括一樹脂芯球。
  7. 如請求項2所述之堆疊型半導體封裝，其中該導電層配置於該第一半導體封裝之側面。
  8. 如請求項1所述之堆疊型半導體封裝，其中該密封樹脂覆蓋該導電層。
  9. 如請求項8所述之堆疊型半導體封裝，其中該導電層於該第一半導體元件之上配置介有一黏著劑或一間隔件(spacer)。
  10. 如請求項2所述之堆疊型半導體封裝，其中該導電層為一具二層以上之配線基板。
  11. 如請求項10所述之堆疊型半導體封裝，更包括一通孔(via)，該通孔配置於該具二層以上之配線基板及該密封樹脂，該第一電路基板及該第二電路基板之間介有該通孔以彼此電性連接。
  12. 如請求項10所述之堆疊型半導體封裝，更包括一通孔，該通孔配置於該密封樹脂，該第一電路基板及該第二電路基板之間介有該具二層以上之配線基板之電路以彼此電性連接。
  13. 一種堆疊型半導體封裝，包括：一第一電路基板；一第一半導體封裝，其中一第一半導體元件安裝於該第一電路基板；一第二電路基板；一第二半導體封裝，其中一第二半導體元件安裝於該第二電路基板，且該第二半導體封裝堆疊於該第一半導體封裝；一密封樹脂，密封該第一半導體元件；以及一斷熱層，接觸於該密封樹脂，並配置於該第一半導體元件的上方，且由覆蓋該第一半導體元件之一端至另一端的絕緣材料所構成；其中該密封樹脂及該斷熱層堆疊於該第一半導體元件之上，覆蓋該第一半導體元件的整體表面。
TW104109627A 2014-03-28 2015-03-25 堆疊型半導體封裝 TWI654734B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2014069881 2014-03-28
JP2014-069881 2014-03-28
JP2015054934A JP6415365B2 (ja) 2014-03-28 2015-03-18 半導体パッケージ
JP2015-054934 2015-03-18

Publications (2)

Publication Number Publication Date
TW201537719A TW201537719A (zh) 2015-10-01
TWI654734B true TWI654734B (zh) 2019-03-21

Family

ID=54191440

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104109627A TWI654734B (zh) 2014-03-28 2015-03-25 堆疊型半導體封裝

Country Status (5)

Country Link
US (2) US9601450B2 (zh)
JP (1) JP6415365B2 (zh)
KR (2) KR102456366B1 (zh)
CN (2) CN111627871A (zh)
TW (1) TWI654734B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6620989B2 (ja) * 2015-05-25 2019-12-18 パナソニックＩｐマネジメント株式会社 電子部品パッケージ
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
WO2017122449A1 (ja) * 2016-01-15 2017-07-20 ソニー株式会社 半導体装置および撮像装置
JP2017175000A (ja) * 2016-03-24 2017-09-28 ローム株式会社 電子部品およびその製造方法、ならびに、インターポーザ
KR102052899B1 (ko) 2016-03-31 2019-12-06 삼성전자주식회사 전자부품 패키지
JP6770331B2 (ja) * 2016-05-02 2020-10-14 ローム株式会社 電子部品およびその製造方法
CN210692526U (zh) * 2016-08-31 2020-06-05 株式会社村田制作所 电路模块
KR102214176B1 (ko) 2017-03-21 2021-02-09 후지필름 가부시키가이샤 적층 디바이스, 적층체 및 적층 디바이스의 제조 방법
US10276536B2 (en) * 2017-04-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10461022B2 (en) * 2017-08-21 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10916488B2 (en) 2018-06-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having thermal conductive pattern surrounding the semiconductor die
JP7044653B2 (ja) * 2018-07-12 2022-03-30 アオイ電子株式会社 半導体装置および半導体装置の製造方法
JP2021129083A (ja) * 2020-02-17 2021-09-02 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10173006A (ja) * 1996-12-09 1998-06-26 Hitachi Ltd 半導体装置および半導体装置の製造方法
JP2002151633A (ja) * 2000-11-08 2002-05-24 Citizen Watch Co Ltd 樹脂封止型半導体装置
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US7061103B2 (en) * 2003-04-22 2006-06-13 Industrial Technology Research Institute Chip package structure
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP2006295119A (ja) * 2005-03-17 2006-10-26 Matsushita Electric Ind Co Ltd 積層型半導体装置
JP2007281043A (ja) * 2006-04-04 2007-10-25 Matsushita Electric Ind Co Ltd 半導体装置
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
JP2009278064A (ja) * 2008-04-17 2009-11-26 Panasonic Corp 半導体装置とその製造方法
JP5489454B2 (ja) 2008-12-25 2014-05-14 キヤノン株式会社 積層型半導体パッケージ
JP2013030593A (ja) 2011-07-28 2013-02-07 J Devices:Kk 半導体装置、該半導体装置を垂直に積層した半導体モジュール構造及びその製造方法
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8710640B2 (en) * 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with heat slug and method of manufacture thereof
JP5893387B2 (ja) 2011-12-22 2016-03-23 新光電気工業株式会社 電子装置及びその製造方法
JP6476620B2 (ja) * 2013-08-26 2019-03-06 株式会社リコー 定着装置及び画像形成装置

Also Published As

Publication number Publication date
KR102456366B1 (ko) 2022-10-19
CN111627871A (zh) 2020-09-04
KR20150112861A (ko) 2015-10-07
US10134710B2 (en) 2018-11-20
KR20220140688A (ko) 2022-10-18
TW201537719A (zh) 2015-10-01
US20150279759A1 (en) 2015-10-01
JP2015195368A (ja) 2015-11-05
US20170148766A1 (en) 2017-05-25
US9601450B2 (en) 2017-03-21
JP6415365B2 (ja) 2018-10-31
CN104966702A (zh) 2015-10-07

Similar Documents

Publication Publication Date Title
TWI654734B (zh) 堆疊型半導體封裝
US10566320B2 (en) Method for fabricating electronic package
US20150022985A1 (en) Device-embedded package substrate and semiconductor package including the same
US9000581B2 (en) Semiconductor package
US8779603B2 (en) Stacked semiconductor device with heat dissipation
JP2008091714A (ja) 半導体装置
US20120217627A1 (en) Package structure and method of fabricating the same
US7786571B2 (en) Heat-conductive package structure
KR20140057982A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
KR20120019091A (ko) 멀티-칩 패키지 및 그의 제조 방법
TW201415587A (zh) 半導體裝置的熱能管理結構及其製造方法
US20120168936A1 (en) Multi-chip stack package structure and fabrication method thereof
TW201605002A (zh) 半導體封裝
JP4919689B2 (ja) モジュール基板
US7361982B2 (en) Bumpless chip package
US10008441B2 (en) Semiconductor package
JP2009129960A (ja) 半導体装置およびその製造方法
TWI423405B (zh) 具載板之封裝結構
CN113632218A (zh) 电子装置
KR20120031817A (ko) 반도체 칩 내장 기판 및 이를 포함하는 적층 반도체 패키지
US9508639B2 (en) Package-in-substrate, semiconductor device and module
CN117766482A (zh) 一种芯片封装结构、封装模组和电子设备
JP2005183879A (ja) 高放熱型プラスチックパッケージ
JP2012256935A (ja) 樹脂封止型半導体装置
JP2012243800A (ja) 半導体装置