CN106356341A - 一种半导体装置及制造方法 - Google Patents

一种半导体装置及制造方法 Download PDF

Info

Publication number
CN106356341A
CN106356341A CN201610799678.XA CN201610799678A CN106356341A CN 106356341 A CN106356341 A CN 106356341A CN 201610799678 A CN201610799678 A CN 201610799678A CN 106356341 A CN106356341 A CN 106356341A
Authority
CN
China
Prior art keywords
layer
nano
circuit device
sintered
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610799678.XA
Other languages
English (en)
Inventor
林志荣
黄文浚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201610799678.XA priority Critical patent/CN106356341A/zh
Publication of CN106356341A publication Critical patent/CN106356341A/zh
Priority to PCT/CN2017/074449 priority patent/WO2018040519A1/zh
Priority to EP17844829.6A priority patent/EP3503176B1/en
Priority to TW106129638A priority patent/TWI650816B/zh
Priority to US16/287,629 priority patent/US20190198422A1/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3185Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • H01L21/4882Assembly of heatsink parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29172Vanadium [V] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Ceramic Engineering (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及电路领域,公开了一种半导体装置及制造方法,该装置包括:层叠设置的电路器件及散热片,以及位于电路器件及散热片之间的热界面材料层;其中,电路器件侧壁上环绕设置有封装层;热界面材料层的第一面与电路器件及封装层热耦合,第二面与散热片热耦合。在上述方案中,采用封装层及电路器件均与热界面材料层热耦合,增大了电路器件与热界面材料层的接触面积,同时,电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上,再传递到散热片上,进而提高半导体装置的散热效果。通过在电路器件的外侧环绕的一层封装层,来增大热界面材料层的铺设面积,增大了热界面材料层接触面的面积,降低了界面应力,并相应的提升了组件信赖性。

Description

一种半导体装置及制造方法
技术领域
本发明涉及半导体技术领域,尤其涉及一种电路半导体装置及制造方法。
背景技术
图1A所示为现有技术中集成电路芯片及其部分封装结构的截面示例图。该结构包括集成电路芯片1A02、热界面材料层1A04及散热器1A06。其中,热界面材料层1A04中具有以分散相形式分布的多个金属颗粒1A08,集成电路芯片1A02于工作过程中产生的热通过芯片背面的热界面材料层1A04倒入散热器1A06,但现有技术中,由于电路芯片1A02的尺寸的限定导致传递热量的效果较低,已很难满足大功率芯片的散热需求。
发明内容
本发明实施例提供一种半导体装置及制造方法。该半导体装置中,通过设置的封装层增大热界面材料层与电路器件的接触面积,大幅度提高了整体热通路的热导效能,能更好地满足大功耗电路器件的散热需求。
第一方面,本发明实施例提供了一种半导体装置,包括:层叠设置的电路器件及散热片,以及位于所述电路器件及所述散热片之间的热界面材料层;其中,
所述电路器件侧壁上环绕设置有封装层;所述电路器件包括集成电路管芯,所述集成电路管芯具有管脚,所述集成电路管芯上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁;
所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面,且所述第一面与所述电路器件及所述封装层热耦合,所述第二面与所述散热片热耦合。
在上述方案中,由于采用封装层环绕电路器件设置,并且封装层及电路器件均与热界面材料层热耦合,从而增大了电路器件与热界面材料层的接触面积,同时,电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上,再传递到散热片上,进而提高半导体装置的散热效果。同时,通过在电路器件的外侧环绕的一层封装层,来增大热界面材料层的铺设面积,增大了热界面材料层接触面的面积,降低了界面应力,并相应的提升了组件信赖性。
其中的封装层采用塑封膜层,该塑封膜层具有良好的传热效果,可以快速的将电路器件侧壁上的热量传递到热界面材料层上,进而提高了电路器件的散热效率。
其中的热界面材料层包括:第一合金层,与所述电路器件及所述封装层热耦合;纳米金属颗粒层,与所述第一合金层热耦合,所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物,所述中间混合物填充于所述多个纳米金属颗粒之间;及第二合金层,与所述纳米金属颗粒层及所述散热片热耦合。由于采用的热界面材料层中不再包含银胶类材料中的高分子类较低热导材料,而是包含纳米金属颗粒,本发明实施例中的热界面材料具有较高导热率,大幅度提高了整体热通路的热导效能,能更好地满足大功耗芯片的散热需求。
在具体设置时,所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构,所述多个纳米金属颗粒之间的接触处形成烧结连续相结构,且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。通过形成的烧结连续相结构提高了两者之间连接效果,并且提高了两者之间热传递的效果。
在一个具体的实施方案中,所述纳米金属颗粒包括银。具有良好的传热效果。并且在具体设置时,所述纳米金属颗粒的直径处于50-200纳米之间。
本实施例提供的半导体装置用于倒装芯片球栅格阵列封装结构。
其中的第一合金层包括第一接着层和第一共烧结层,所述第一接着层与所述电路器件及所述封装层热耦合,所述第一共烧结层与所述纳米金属颗粒层耦合,且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。采用上述结构,提高了第一合金层与电路器件及封装层热耦合的连接强度,并且具有良好的热传递效果。
在具体设置时,第一接着层包括以下材料中的任一种:钛、铬、镍或镍钒合金,所述第一共烧结层包括以下材料中的任一种:银、金或铜。上述材料均具有较好的热传递效果。
此外,作为一个优选的方案,所述第一合金层还包括第一缓冲层,位于所述第一接着层与所述第一共烧结层之间,所述第一缓冲层包括以下材料中的任一种:铝、铜、镍或镍钒合金。
在具体设置时,所述第二合金层包括第二接着层和第二共烧结层,所述第二接着层与所述散热片热耦合,所述第二共烧结层与所述纳米金属颗粒层热耦合,且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。采用上述结构,提高了第二合金层与散热片热耦合的连接强度,并且具有良好的热传递效果。
且在具体设置时,其中的第二接着层包括以下材料中的任一种:钛、铬、镍或镍钒合金,所述第二共烧结层包括以下材料中的任一种:银、金或铜。上述材料均具有较好的热传递效果。
作为一个优选的方案,所述第二合金层还包括第二缓冲层,位于所述第二接着层与所述第二共烧结层之间,所述第二缓冲层包括以下材料中的任一种:铝、铜、镍或镍钒合金。
其中的纳米金属颗粒的直径不大于1微米。
中间混合物可以选择不同的材料,在一个具体的实施方式中所述中间混合物包括以下材料中的任一种:空气或树脂。
本发明实施例提供了一种制造半导体装置的方法,包括:在电路器件的侧壁上环绕设置封装层;其中,所述电路器件包括集成电路管芯,所述集成电路管芯具有管脚,所述集成电路管芯上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁;
生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;
将第一面与所述电路器件及所述封装层热耦合,所述第二面与所述散热片热耦合。
在上述方案中,由于采用封装层环绕电路器件设置,并且封装层及电路器件均与热界面材料层热耦合,从而增大了电路器件与热界面材料层的接触面积,同时,电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上,再传递到散热片上,进而提高半导体装置的散热效果。同时,通过在电路器件的外侧环绕的一层封装层,来增大热界面材料层的铺设面积,增大了热界面材料层接触面的面积,降低了界面应力,并相应的提升了组件信赖性。
在具体制备时,所述生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;具体为:
生成第一合金层;
由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层,使所述中间混合物填充于所述多个纳米金属颗粒之间;
生成第二合金层,
使所述纳米金属颗粒层分别与所述第一合金层及第二合金层热耦合;其中,所述第一合金层背离所述纳米颗粒层一面为第一面,所述第二合金层背离所述纳米金属颗粒层的一面为第二面。
还包括:使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构,使所述纳米金属颗粒之间的接触处形成烧结连续相结构,且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
其中的纳米金属颗粒的直径不大于1微米。
其中的中间混合物包括以下材料中的任一种:空气或树脂。
在具体制备第一合金层时,生成第一接着层和第一共烧结层,并使所述第一接着层与所述电路器件及所述封装层热耦合,使所述第一共烧结层与所述纳米金属颗粒层耦合,且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
在具体制备第二合金层时:生成第二接着层和第二共烧结层,并使所述第二接着层与所述散热片热耦合,使所述第二共烧结层与所述纳米金属颗粒层热耦合,且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
其中的,所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料,以在所述侧壁上环绕设置所述封装层。塑封膜具有良好的热传递效果,通过设置的塑封膜制备封装层提高了电路器件的散热效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1A是现有技术中包括半导体装置的封装结构的截面示例图;
图1B是本发明第一实施例的包括半导体装置的截面示例图;
图2是本发明第一实施例提供的半导体装置的电路器件与封装层结合的示意图;
图3是第一实施例中热界面材料层与电路器件及封装层热耦合的截面示例图;
图4是图3中的第一合金层的第一实施例的截面示例图;
图5是图3中的第一合金层的第二实施例的截面示例图;
图6是图3中的第二合金层的第一实施例的截面示例图;
图7是图3中第二合金层的第二实施例的截面示例图;
图8是本发明第二实施例的一种制造半导体装置的方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
为了方便描述,本实施例定义了电路器件的侧壁,在本实施例中电路器件的侧壁是指,电路器件上与设置有管脚的一面(安装面)相邻的壁,在图1B中,图1B为本发明第一实施例提供的半导体装置的截面示例图,以半导体装置的放置方向为参考方向,该电路器件的侧壁为图1B中示出的在竖直方向的一面。
本发明实施例提供了一种半导体装置,该半导体装置包括:层叠设置的电路器件及散热片105,以及位于所述电路器件及所述散热片105之间的热界面材料层104;其中,
所述电路器件侧壁上环绕设置有封装层120;其中,所述电路器件包括集成电路管芯103,所述集成电路管芯103具有管脚,所述集成电路管芯103上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯103上与所述安装面相邻的壁;
所述热界面材料层104具有朝向所述电路器件及所述封装层120的第一面以及朝向所述散热片105的第二面,且所述第一面与所述电路器件及所述封装层120热耦合,所述第二面与所述散热片105热耦合。
一并参考图1B及图2,图1B是本发明第一实施例包括半导体装置的截面示例图。图2为本实施例中电路器件与封装层结合的俯视图。图2为以图1B所示的器件的放置方向为参考方向,从上向下看到的电路器件(集成电路管芯103)与封装层120结构的示意图。在图2中,电路器件采用规则的矩形形状,应当理解的是,图2仅仅是为了示意电路器件与封装层120之间的位置关系,其中的电路器件的形状不仅限于上述图2中的矩形形状,还可以是其他的任意形状;结合图1B及图2可以看出,本实施例提供的封装层120环绕电路器件的侧壁设置,即封装层120可以看成围绕电路器件转一周形成的一个包裹电路器件侧壁的结构。即如图1B所示,在电路器件包括集成电路管芯103及底部填充物101时,封装层120包裹住集成电路管芯103及底部填充物101的侧壁,并且封装层120的顶面(图2中能够看到的封装层的一面)与集成电路管芯103的顶面(图2中能够看到的集成电路管芯103的一面)齐平,并与集成电路管芯103的顶面共同组成与热界面材料层104连接的接触面。散热片105通过粘接胶106固定在基板107上,集成电路管芯103的管脚与基板107上的电路连接。热界面材料层104与集成电路管芯103及散热片105热耦合。在具体设置时,热界面材料层104覆盖在集成电路管芯103及封装层120的顶面(即图2中示出的一面)并热耦合,由于封装层120具有一定的厚度d(即框形面的宽度),因此,封装层120形成一个与热界面材料层104进行热耦合的框形的接触面(如图2所示),且在具体设置时,封装层120具有设定厚度d以保证能够封装住电路器件,因此,框形接触面的框边具有一定的宽度(该宽度等于封装层120的厚度),具体的,在没有封装层120时,耦合面积仅为集成电路管芯103的顶面面积,在增加上封装层120后,如图2所示,耦合面积为集成电路管芯103的顶面的面积加上封装层120顶面的面积,增大了热界面材料层104在与集成电路管芯103热耦合面的面积。此外,由于耦合面积的增大,进而增加了热界面材料层104与集成电路管芯103的连接强度,并且降低了界面应力(整体应力不变,但接触面积增大,降低单位面积下应力影响),提升组件信赖性表现。
此外,在具体设置时,由于封装层120贴附在电路器件的侧壁上,因此,在散热时,电路器件中侧壁上的热量可以通过封装层120传递到热界面材料层104上,进而扩散到散热片105上,在采用上述结构时,可以看出,电路器件的散热方式为:电路器件的顶面的热量通过热界面材料层104—散热片105的路径进行散热,电路器件的侧壁上的热量通过封装层120—热界面材料层104—散热片105的路径进行散热,从而增大了电路器件的散热面积,进而提高了电路器件的散热效果。
在一个具体的实施方式中,该封装层120采用塑胶膜层,塑胶膜层具有良好的封装效果以及热传递效果,从而可以快速的将热量传递到热界面材料层,进而提高电路器件的散热效果。
如图1B及图2所示,整个半导体装置在采用倒装芯片球栅格阵列封装结构时,包括焊球108,基板107,粘接胶106,金属凸块(BUMP)102,电路器件(如集成电路管芯103),环绕该电路器件103的封装层120(如塑封膜层),热界面材料层104及散热片105。集成电路管芯103通过金属凸块102与基板107耦合。金属凸块102由底部填充物101保护,封装层120环绕集成电路管芯103设置,且在具体设置时,本实施例中,热耦合包括不同层次,不同结构,或不同装置间有热传导的情形。更详细地,热界面材料层104可位于集成电路管芯103及散热片105之间,且集成电路管芯103的衬底与热界面材料层104热耦合,封装层也与热界面材料层104热耦合。集成电路管芯103的热量通过热界面材料层104达到散热片105。
其中,集成电路管芯103、环绕该电路器件103的封装层120、热界面材料层104及散热片105可作为一种半导体装置的部分或全部组件,且该半导体装置可用于但不限于如图所示的倒装芯片球栅格阵列封装结构。
图3是第一实施例中热界面材料层与电路器件及封装层热耦合的截面示例图;其中,图3中仅示出了图1B中热界面材料层104与集成电路管芯103连接的上半部分结构,封装层120也仅示出了封装层120的上半部分结构,该上半部分结构不包括底部填充物101。热界面材料层104与集成电路管芯103、封装层120及散热片105热耦合,包括第一合金层109、纳米金属颗粒层110及第二合金层112。
第一合金层109将集成电路管芯103及封装层120与纳米金属颗粒层110热耦合。更具体地,如图3所示,第一合金层109可位于集成电路管芯103及封装层120之上,纳米金属颗粒层110之下。即,第一合金层109可位于集成电路管芯103与纳米金属颗粒层110之间。第一合金层109增加集成电路管芯103与纳米金属颗粒层110之间的接着强度,并通过设置的封装层120增大了第一合金层109的覆盖面积,即增大了形成的第一合金层109的面积,进而提高了形成的热界面材料层的面积104。
纳米金属颗粒层110包括纳米金属颗粒及中间混合物。中间混合物包括但不限于以下材料中的任一种:空气或树脂。中间混合物用于填充于多个纳米金属颗粒之间,使多个纳米金属颗粒形成整体。纳米金属颗粒包括但不限于银。纳米金属颗粒的直径不大于1微米。在一个实施例中,纳米金属颗粒的直径处于50-200纳米之间。纳米金属颗粒层110热阻较低,形成较好的导热通路。
第二合金层112与纳米金属颗粒层110及散热片105热耦合。更具体地,如图所示,第二合金层112可位于纳米金属颗粒层110之上,散热片105之下。即,第二合金层112可位于纳米金属颗粒层110与散热片105之间。第二合金层112增加纳米金属颗粒层110与散热片105之间的接着强度。
在一个实施例中,第一合金层109与纳米金属颗粒层110的接触处形成烧结连续相结构,纳米金属颗粒之间的接触处形成烧结连续相结构,且第二合金层112与纳米金属颗粒层110的接触处形成烧结连续相结构。本文中的烧结连续相结构包括但不限于:因金属颗粒产生烧结行为,金属颗粒接口附近的金属原子扩散至金属颗粒界面融合在一起,使得金属颗粒形成一个整体的结构。
图4是图3中第一合金层109的第一实施例的截面示例图。图4也仅示出了封装层120与集成电路管芯103的上半部分结构,如图所示,第一合金层109包括第一接着层114和第一共烧结层115。本文中的共烧结层包括但不限于:在封装加工过程中产生的与热界面材料层互融的金属层,该金属层与热界面材料层中的颗粒共同烧结形成热流通路。第一接着层114与集成电路管芯103及封装层120热耦合。第一共烧结层115与纳米金属颗粒层110热耦合。第一共烧结层115与纳米金属颗粒层110的接触处形成烧结连续相结构。具体地,第一接着层114可位于集成电路管芯103及封装层120之上,第一共烧结层115可位于第一接着层114之上,纳米金属颗粒层110之下。第一接着层114包括但不限于以下材料中的任一种:钛、铬、镍或镍/钒。第一接着层114增加集成电路管芯103与第一共烧结层115之间的结合强度。第一共烧结层115包括但不限于以下材料中的任一种:银、金或铜。
图5是图3中第一合金层109的第二实施例的截面示例图。图5也仅示出了封装层120与集成电路管芯103的上半部分结构,与图3相比,图4中的第一合金层109还包括第一缓冲层116,位于所述第一接着层114与第一共烧结层115之间。第一缓冲层116包括但不限于以下材料中的任一种:铝、铜或镍。第一缓冲层116在因热处理产生的形变中提供应力缓冲功能,降低集成电路管芯103与热界面材料层114间或热界面材料层114中间产生裂缝的风险,增加该半导体装置的可靠性。
图6是图3中第二合金层112的第一实施例的截面示例图。如图所示,第二合金层112包括第二共烧结层118和第二接着层117。第二共烧结层118与纳米金属颗粒层110热耦合。第二共烧结层118与纳米金属颗粒层110的接触处形成烧结连续相结构。第二接着层117与散热片105热耦合。具体地,第二共烧结层118可位于纳米金属颗粒层110之上,第二接着层117可位于第二共烧结层118之上,散热片105之下。第二共烧结层118包括但不限于以下材料中的任一种:银、金或铜。第二接着层117包括但不限于以下材料中的任一种:钛、铬、镍或镍/钒。第二接着层117增加第二共烧结层115与散热片105之间的结合强度。
图7是图3中第二合金层112的第二实施例的截面示例图。与图6相比,图7中的第二合金层112还包括第二缓冲层119,位于第二接着层117与第二共烧结层118之间。第二缓冲层119包括但不限于以下材料中的任一种:铝、铜、镍或镍/钒。第二缓冲层119在因热处理产生的形变中提供缓冲功能,降低热界面材料层与散热片105间或热界面材料层114中间产生裂缝的风险,增加该半导体装置的可靠性。
综上,由于本发明实施例中的热界面材料层中不再包含银胶类材料中的高分子类较低热导材料,而是包含纳米金属颗粒,本发明实施例中的热界面材料具有较高导热率,大幅度提高了整体热通路的热导效能,能更好地满足大功耗芯片的散热需求,同时,通过在集成电路管芯103的外侧环绕一层封装层120,来增大热界面材料层的铺设面积,增大了热界面材料层接触面的面积,降低了界面应力,并相应的提升了组件信赖性。
图8是本发明第二实施例的一种制造半导体装置的方法的流程图700。如图所示,在步骤702中,在电路器件的侧壁上环绕设置封装层,其中,所述电路器件包括集成电路管芯,所述集成电路管芯具有管脚,所述集成电路管芯上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁;在步骤704中,生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;在步骤706中,将第一面与所述电路器件及所述封装层热耦合,所述第二面与所述散热片热耦合。
此外,所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料,以在所述侧壁上环绕设置所述封装层。塑封膜具有良好的传热效果,可以快速的将电路器件侧壁上的热量传递到热界面材料层上,进而提高了电路器件的散热效率。
在具体制备时,生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;具体为:
生成第一合金层。由相互耦合的纳米金属颗粒与中间混合物生成纳米金属颗粒层。纳米金属颗粒的直径不大于1微米,例如,纳米金属颗粒的直径处于50-200纳米之间。中间混合物包括但不限于以下材料中的任一种:空气或树脂。在一个实施例中,纳米金属颗粒包括但不限于银。生成第二合金层。使第一合金层将纳米金属颗粒层与电路器件及封装层热耦合。使第二合金层与纳米金属颗粒层及散热片热耦合。
在一个实施例中,使第一合金层与纳米金属颗粒层的接触处形成烧结连续相结构,使纳米金属颗粒之间的接触处形成烧结连续相结构,且使第二合金层与纳米金属颗粒层的接触处形成烧结连续相结构。
在一个实施例中,该方法可用于但不限于倒装芯片球栅格阵列封装结构。
在一个实施例中,生成第一合金层包括生成第一接着层和第一共烧结层,并使第一接着层与电路器件及封装层热耦合,使第一共烧结层与纳米金属颗粒层耦合,且使第一共烧结层与纳米金属颗粒层的接触处形成烧结连续相结构。第一接着层包括但不限于以下材料中的任一种:钛、铬、镍或镍/钒。第一共烧结层包括但不限于以下材料中的任一种:银、金或铜。在另一个实施例中,生成第一合金层还包括在第一接着层与第一共烧结层之间生成第一缓冲层。第一缓冲层包括但不限于以下材料中的任一种:铝、铜、镍或镍/钒。
在一个实施例中,生成第二合金层包括生成第二接着层和第二共烧结层,并使第二接着层与散热片热耦合,使第二共烧结层与纳米金属颗粒层热耦合,且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。第二接着层包括但不限于以下材料中的任一种:钛、铬、镍或镍/钒。第二共烧结层包括但不限于以下材料中的任一种:银、金或铜。在另一个实施例中,生成第二合金层还包括在第二接着层与第二共烧结层之间生成第二缓冲层。第二缓冲层包括但不限于以下材料中的任一种:铝、铜、镍或镍/钒。
电路器件可包括集成电路管芯。使第一合金层与电路器件及封装层热耦合包括使第一合金层与集成电路管芯中的衬底及封装层热耦合。
以上所揭露的仅为本发明较佳实施例而已,当然不能以此来限定本发明之权利范围,因此依本发明权利要求所作的等同变化,仍属本发明所涵盖的范围。

Claims (17)

1.一种半导体装置,其特征在于,包括:层叠设置的电路器件及散热片,以及位于所述电路器件及所述散热片之间的热界面材料层;其中,
所述电路器件侧壁上环绕设置有封装层;所述电路器件包括集成电路管芯,所述集成电路管芯具有管脚,所述集成电路管芯上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁;
所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面,且所述第一面与所述电路器件及所述封装层热耦合,所述第二面与所述散热片热耦合。
2.如权利要求1所述的半导体装置,其特征在于,所述封装层为塑封膜层。
3.如权利要求1或2所述的半导体装置,其特征在于,所述热界面材料层包括:
第一合金层,与所述电路器件及所述封装层热耦合;
纳米金属颗粒层,与所述第一合金层热耦合,所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物,所述中间混合物填充于所述多个纳米金属颗粒之间;及
第二合金层,与所述纳米金属颗粒层及所述散热片热耦合。
4.如权利要求3所述的半导体装置,其特征在于,所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构,所述多个纳米金属颗粒之间的接触处形成烧结连续相结构,且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
5.如权利要求1-4中任一项所述的半导体装置,其特征在于,用于倒装芯片球栅格阵列封装结构。
6.如权利要求3-5中任一项所述的半导体装置,其特征在于,第一合金层包括第一接着层和第一共烧结层,所述第一接着层与所述电路器件及所述封装层热耦合,所述第一共烧结层与所述纳米金属颗粒层耦合,且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
7.如权利要求6所述的半导体装置,其特征在于,所述第一接着层包括以下材料中的任一种:钛、铬、镍或镍钒合金,所述第一共烧结层包括以下材料中的任一种:银、金或铜。
8.如权利要求6或7所述的半导体装置,其特征在于,所述第一合金层还包括第一缓冲层,位于所述第一接着层与所述第一共烧结层之间,所述第一缓冲层包括以下材料中的任一种:铝、铜、镍或镍钒合金。
9.如权利要求3-8中任一项所述的半导体装置,其特征在于,所述第二合金层包括第二接着层和第二共烧结层,所述第二接着层与所述散热片热耦合,所述第二共烧结层与所述纳米金属颗粒层热耦合,且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
10.如权利要求8或9所述的半导体装置,其特征在于,所述第二合金层还包括第二缓冲层,位于所述第二接着层与所述第二共烧结层之间,所述第二缓冲层包括以下材料中的任一种:铝、铜、镍或镍钒合金。
11.如权利要求3-10中任一所述的半导体装置,其特征在于,所述中间混合物包括以下材料中的任一种:空气或树脂。
12.一种半导体装置的制造方法,其特征在于,包括:
在电路器件的侧壁上环绕设置封装层;其中,所述电路器件包括集成电路管芯,所述集成电路管芯具有管脚,所述集成电路管芯上设置所述管脚的一面为安装面,所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁;
生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;
将第一面与所述电路器件及所述封装层热耦合,所述第二面与所述散热片热耦合。
13.如权利要求12所述的制造方法,其特征在于,所述生成热界面材料层,所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面;具体为:
生成第一合金层;
由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层,使所述中间混合物填充于所述多个纳米金属颗粒之间;
生成第二合金层,
使所述纳米金属颗粒层分别与所述第一合金层及第二合金层热耦合;其中,所述第一合金层背离所述纳米颗粒层一面为第一面,所述第二合金层背离所述纳米金属颗粒层的一面为第二面。
14.如权利要求13所述的制造方法,其特征在于,还包括使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构,使所述纳米金属颗粒之间的接触处形成烧结连续相结构,且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
15.如权利要求13或14所述的制造方法,其特征在于,所述生成第一合金层包括:生成第一接着层和第一共烧结层,并使所述第一接着层与所述电路器件及所述封装层热耦合,使所述第一共烧结层与所述纳米金属颗粒层耦合,且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
16.如权利要求13-15中任一所述的制造方法,其特征在于,所述生成第二合金层包括:生成第二接着层和第二共烧结层,并使所述第二接着层与所述散热片热耦合,使所述第二共烧结层与所述纳米金属颗粒层热耦合,且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
17.如权利要求12-16所述的制造方法,其特征在于,所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料,以在所述侧壁上环绕设置所述封装层。
CN201610799678.XA 2016-08-31 2016-08-31 一种半导体装置及制造方法 Pending CN106356341A (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201610799678.XA CN106356341A (zh) 2016-08-31 2016-08-31 一种半导体装置及制造方法
PCT/CN2017/074449 WO2018040519A1 (zh) 2016-08-31 2017-02-22 一种半导体装置及制造方法
EP17844829.6A EP3503176B1 (en) 2016-08-31 2017-02-22 Semiconductor apparatus and manufacturing method
TW106129638A TWI650816B (zh) 2016-08-31 2017-08-31 半導體裝置及其製造方法
US16/287,629 US20190198422A1 (en) 2016-08-31 2019-02-27 Semiconductor apparatus and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610799678.XA CN106356341A (zh) 2016-08-31 2016-08-31 一种半导体装置及制造方法

Publications (1)

Publication Number Publication Date
CN106356341A true CN106356341A (zh) 2017-01-25

Family

ID=57858743

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610799678.XA Pending CN106356341A (zh) 2016-08-31 2016-08-31 一种半导体装置及制造方法

Country Status (5)

Country Link
US (1) US20190198422A1 (zh)
EP (1) EP3503176B1 (zh)
CN (1) CN106356341A (zh)
TW (1) TWI650816B (zh)
WO (1) WO2018040519A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018040519A1 (zh) * 2016-08-31 2018-03-08 华为技术有限公司 一种半导体装置及制造方法
CN110648924A (zh) * 2019-09-04 2020-01-03 广东芯华微电子技术有限公司 大板扇出型芯片封装结构及其制作方法
WO2021068966A1 (zh) * 2019-10-11 2021-04-15 宁波施捷电子有限公司 一种界面导热材料层及其用途
CN114787990A (zh) * 2019-12-16 2022-07-22 华为技术有限公司 芯片封装及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11621211B2 (en) 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184913A (ja) * 2001-10-22 2002-06-28 Seiko Epson Corp 半導体装置の製造方法
US20080073776A1 (en) * 2006-09-26 2008-03-27 Daewoong Suh Sintered metallic thermal interface materials for microelectronic cooling assemblies
CN104241218A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种带有散热结构的倒装芯片塑封结构及制造方法
CN105355610A (zh) * 2015-08-27 2016-02-24 华为技术有限公司 一种电路装置及制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060285480A1 (en) * 2005-06-21 2006-12-21 Janofsky Eric B Wireless local area network communications module and integrated chip package
CN100403532C (zh) * 2005-08-19 2008-07-16 南茂科技股份有限公司 散热型球格阵列封装结构
US20080023665A1 (en) * 2006-07-25 2008-01-31 Weiser Martin W Thermal interconnect and interface materials, methods of production and uses thereof
US8030757B2 (en) * 2007-06-29 2011-10-04 Intel Corporation Forming a semiconductor package including a thermal interface material
EP2188834A4 (en) * 2007-09-11 2014-03-19 Dow Corning COMPOSITE, THERMAL INTERFACE MATERIAL CONTAINING THE COMPOSITE AND METHODS FOR THE PREPARATION AND USE THEREOF
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
KR20120053332A (ko) * 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
TWI529880B (zh) * 2013-06-19 2016-04-11 日月光半導體製造股份有限公司 半導體元件,半導體封裝結構及其製造方法
TWI563615B (en) * 2015-05-05 2016-12-21 Siliconware Precision Industries Co Ltd Electronic package structure and the manufacture thereof
CN106356341A (zh) * 2016-08-31 2017-01-25 华为技术有限公司 一种半导体装置及制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184913A (ja) * 2001-10-22 2002-06-28 Seiko Epson Corp 半導体装置の製造方法
US20080073776A1 (en) * 2006-09-26 2008-03-27 Daewoong Suh Sintered metallic thermal interface materials for microelectronic cooling assemblies
CN104241218A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种带有散热结构的倒装芯片塑封结构及制造方法
CN105355610A (zh) * 2015-08-27 2016-02-24 华为技术有限公司 一种电路装置及制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018040519A1 (zh) * 2016-08-31 2018-03-08 华为技术有限公司 一种半导体装置及制造方法
CN110648924A (zh) * 2019-09-04 2020-01-03 广东芯华微电子技术有限公司 大板扇出型芯片封装结构及其制作方法
WO2021068966A1 (zh) * 2019-10-11 2021-04-15 宁波施捷电子有限公司 一种界面导热材料层及其用途
CN114787990A (zh) * 2019-12-16 2022-07-22 华为技术有限公司 芯片封装及其制作方法

Also Published As

Publication number Publication date
TW201820468A (zh) 2018-06-01
EP3503176B1 (en) 2021-01-20
EP3503176A1 (en) 2019-06-26
US20190198422A1 (en) 2019-06-27
WO2018040519A1 (zh) 2018-03-08
TWI650816B (zh) 2019-02-11
EP3503176A4 (en) 2019-08-28

Similar Documents

Publication Publication Date Title
TWI650816B (zh) 半導體裝置及其製造方法
US9583474B2 (en) Package on packaging structure and methods of making same
KR101531746B1 (ko) 패키지 온 패키지 구조 및 패키지 온 패키지 구조를 형성하는 방법
TWI556374B (zh) 封裝結構及其形成方法
CN103715150B (zh) 芯片帽及戴有芯片帽的倒装芯片封装
JP6605382B2 (ja) 半導体装置及び半導体装置の製造方法
US9666506B2 (en) Heat spreader with wiring substrate for reduced thickness
TWI644367B (zh) 一種具熱界面的裝置及製造方法
US9607923B2 (en) Electronic device having a thermal conductor made of silver between a heat sink and an electronic element, and fabrication method thereof
JP2009540572A (ja) 熱特性を向上させた、基板を用いたアレイ・パッケージの製造方法
CN101425486A (zh) 一种封装结构
CN102867793A (zh) 热界面材料及半导体封装结构
JP6469660B2 (ja) 半導体装置の製造方法
JP2011054806A (ja) 半導体装置およびその製造方法
CN109923650B (zh) 具有提高的导热性的耐应变管芯附着和制造方法
JP2013077691A (ja) 部品内蔵基板実装体及びその製造方法並びに部品内蔵基板
TW200836307A (en) Thermally enhanced quad flat no leads (QFN) IC package and method
US20090230544A1 (en) Heat sink structure and semiconductor package as well as method for configuring heat sinks on a semiconductor package
JP2010528472A (ja) 熱性能の向上のためにフタをはんだ付けされた集積回路パッケージ
TW200423342A (en) Chip package structure and process for fabricating the same
TWI536515B (zh) 具有散熱結構之半導體封裝元件及其封裝方法
TWI388041B (zh) 具散熱結構之半導體封裝件
CN211238224U (zh) 具有散热片的半导体封装结构
CN113745176A (zh) 半导体器件
KR101459566B1 (ko) 히트슬러그, 그 히트슬러그를 포함한 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170125